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61 lines
1.5 KiB
61 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
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* Copyright 2011 Florian Tobias Schandinat <[email protected]> |
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*/ |
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/* |
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* clock and PLL management functions |
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*/ |
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#ifndef __VIA_CLOCK_H__ |
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#define __VIA_CLOCK_H__ |
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#include <linux/types.h> |
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enum via_clksrc { |
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VIA_CLKSRC_X1 = 0, |
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VIA_CLKSRC_TVX1, |
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VIA_CLKSRC_TVPLL, |
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VIA_CLKSRC_DVP1TVCLKR, |
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VIA_CLKSRC_CAP0, |
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VIA_CLKSRC_CAP1, |
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}; |
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struct via_pll_config { |
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u16 multiplier; |
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u8 divisor; |
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u8 rshift; |
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}; |
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struct via_clock { |
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void (*set_primary_clock_state)(u8 state); |
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void (*set_primary_clock_source)(enum via_clksrc src, bool use_pll); |
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void (*set_primary_pll_state)(u8 state); |
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void (*set_primary_pll)(struct via_pll_config config); |
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void (*set_secondary_clock_state)(u8 state); |
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void (*set_secondary_clock_source)(enum via_clksrc src, bool use_pll); |
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void (*set_secondary_pll_state)(u8 state); |
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void (*set_secondary_pll)(struct via_pll_config config); |
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void (*set_engine_pll_state)(u8 state); |
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void (*set_engine_pll)(struct via_pll_config config); |
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}; |
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static inline u32 get_pll_internal_frequency(u32 ref_freq, |
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struct via_pll_config pll) |
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{ |
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return ref_freq / pll.divisor * pll.multiplier; |
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} |
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static inline u32 get_pll_output_frequency(u32 ref_freq, |
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struct via_pll_config pll) |
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{ |
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return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; |
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} |
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void via_clock_init(struct via_clock *clock, int gfx_chip); |
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#endif /* __VIA_CLOCK_H__ */
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