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817 lines
20 KiB
817 lines
20 KiB
/* |
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* linux/drivers/video/pxa168fb.c -- Marvell PXA168 LCD Controller |
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* |
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* Copyright (C) 2008 Marvell International Ltd. |
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* All rights reserved. |
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* |
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* 2009-02-16 adapted from original version for PXA168/910 |
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* Jun Nie <[email protected]> |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive for |
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* more details. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/string.h> |
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#include <linux/interrupt.h> |
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#include <linux/slab.h> |
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#include <linux/fb.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/uaccess.h> |
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#include <video/pxa168fb.h> |
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|
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#include "pxa168fb.h" |
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|
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#define DEFAULT_REFRESH 60 /* Hz */ |
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|
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static int determine_best_pix_fmt(struct fb_var_screeninfo *var) |
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{ |
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/* |
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* Pseudocolor mode? |
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*/ |
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if (var->bits_per_pixel == 8) |
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return PIX_FMT_PSEUDOCOLOR; |
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|
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/* |
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* Check for 565/1555. |
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*/ |
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if (var->bits_per_pixel == 16 && var->red.length <= 5 && |
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var->green.length <= 6 && var->blue.length <= 5) { |
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if (var->transp.length == 0) { |
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if (var->red.offset >= var->blue.offset) |
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return PIX_FMT_RGB565; |
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else |
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return PIX_FMT_BGR565; |
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} |
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if (var->transp.length == 1 && var->green.length <= 5) { |
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if (var->red.offset >= var->blue.offset) |
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return PIX_FMT_RGB1555; |
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else |
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return PIX_FMT_BGR1555; |
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} |
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} |
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/* |
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* Check for 888/A888. |
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*/ |
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if (var->bits_per_pixel <= 32 && var->red.length <= 8 && |
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var->green.length <= 8 && var->blue.length <= 8) { |
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if (var->bits_per_pixel == 24 && var->transp.length == 0) { |
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if (var->red.offset >= var->blue.offset) |
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return PIX_FMT_RGB888PACK; |
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else |
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return PIX_FMT_BGR888PACK; |
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} |
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if (var->bits_per_pixel == 32 && var->transp.length == 8) { |
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if (var->red.offset >= var->blue.offset) |
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return PIX_FMT_RGBA888; |
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else |
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return PIX_FMT_BGRA888; |
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} else { |
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if (var->red.offset >= var->blue.offset) |
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return PIX_FMT_RGB888UNPACK; |
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else |
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return PIX_FMT_BGR888UNPACK; |
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} |
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} |
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return -EINVAL; |
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} |
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static void set_pix_fmt(struct fb_var_screeninfo *var, int pix_fmt) |
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{ |
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switch (pix_fmt) { |
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case PIX_FMT_RGB565: |
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var->bits_per_pixel = 16; |
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var->red.offset = 11; var->red.length = 5; |
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var->green.offset = 5; var->green.length = 6; |
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var->blue.offset = 0; var->blue.length = 5; |
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var->transp.offset = 0; var->transp.length = 0; |
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break; |
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case PIX_FMT_BGR565: |
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var->bits_per_pixel = 16; |
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var->red.offset = 0; var->red.length = 5; |
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var->green.offset = 5; var->green.length = 6; |
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var->blue.offset = 11; var->blue.length = 5; |
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var->transp.offset = 0; var->transp.length = 0; |
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break; |
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case PIX_FMT_RGB1555: |
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var->bits_per_pixel = 16; |
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var->red.offset = 10; var->red.length = 5; |
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var->green.offset = 5; var->green.length = 5; |
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var->blue.offset = 0; var->blue.length = 5; |
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var->transp.offset = 15; var->transp.length = 1; |
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break; |
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case PIX_FMT_BGR1555: |
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var->bits_per_pixel = 16; |
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var->red.offset = 0; var->red.length = 5; |
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var->green.offset = 5; var->green.length = 5; |
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var->blue.offset = 10; var->blue.length = 5; |
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var->transp.offset = 15; var->transp.length = 1; |
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break; |
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case PIX_FMT_RGB888PACK: |
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var->bits_per_pixel = 24; |
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var->red.offset = 16; var->red.length = 8; |
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var->green.offset = 8; var->green.length = 8; |
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var->blue.offset = 0; var->blue.length = 8; |
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var->transp.offset = 0; var->transp.length = 0; |
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break; |
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case PIX_FMT_BGR888PACK: |
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var->bits_per_pixel = 24; |
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var->red.offset = 0; var->red.length = 8; |
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var->green.offset = 8; var->green.length = 8; |
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var->blue.offset = 16; var->blue.length = 8; |
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var->transp.offset = 0; var->transp.length = 0; |
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break; |
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case PIX_FMT_RGBA888: |
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var->bits_per_pixel = 32; |
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var->red.offset = 16; var->red.length = 8; |
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var->green.offset = 8; var->green.length = 8; |
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var->blue.offset = 0; var->blue.length = 8; |
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var->transp.offset = 24; var->transp.length = 8; |
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break; |
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case PIX_FMT_BGRA888: |
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var->bits_per_pixel = 32; |
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var->red.offset = 0; var->red.length = 8; |
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var->green.offset = 8; var->green.length = 8; |
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var->blue.offset = 16; var->blue.length = 8; |
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var->transp.offset = 24; var->transp.length = 8; |
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break; |
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case PIX_FMT_PSEUDOCOLOR: |
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var->bits_per_pixel = 8; |
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var->red.offset = 0; var->red.length = 8; |
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var->green.offset = 0; var->green.length = 8; |
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var->blue.offset = 0; var->blue.length = 8; |
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var->transp.offset = 0; var->transp.length = 0; |
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break; |
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} |
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} |
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static void set_mode(struct pxa168fb_info *fbi, struct fb_var_screeninfo *var, |
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struct fb_videomode *mode, int pix_fmt, int ystretch) |
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{ |
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struct fb_info *info = fbi->info; |
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set_pix_fmt(var, pix_fmt); |
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var->xres = mode->xres; |
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var->yres = mode->yres; |
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var->xres_virtual = max(var->xres, var->xres_virtual); |
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if (ystretch) |
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var->yres_virtual = info->fix.smem_len / |
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(var->xres_virtual * (var->bits_per_pixel >> 3)); |
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else |
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var->yres_virtual = max(var->yres, var->yres_virtual); |
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var->grayscale = 0; |
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var->accel_flags = FB_ACCEL_NONE; |
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var->pixclock = mode->pixclock; |
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var->left_margin = mode->left_margin; |
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var->right_margin = mode->right_margin; |
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var->upper_margin = mode->upper_margin; |
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var->lower_margin = mode->lower_margin; |
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var->hsync_len = mode->hsync_len; |
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var->vsync_len = mode->vsync_len; |
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var->sync = mode->sync; |
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var->vmode = FB_VMODE_NONINTERLACED; |
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var->rotate = FB_ROTATE_UR; |
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} |
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static int pxa168fb_check_var(struct fb_var_screeninfo *var, |
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struct fb_info *info) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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int pix_fmt; |
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/* |
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* Determine which pixel format we're going to use. |
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*/ |
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pix_fmt = determine_best_pix_fmt(var); |
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if (pix_fmt < 0) |
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return pix_fmt; |
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set_pix_fmt(var, pix_fmt); |
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fbi->pix_fmt = pix_fmt; |
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/* |
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* Basic geometry sanity checks. |
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*/ |
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if (var->xoffset + var->xres > var->xres_virtual) |
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return -EINVAL; |
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if (var->yoffset + var->yres > var->yres_virtual) |
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return -EINVAL; |
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if (var->xres + var->right_margin + |
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var->hsync_len + var->left_margin > 2048) |
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return -EINVAL; |
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if (var->yres + var->lower_margin + |
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var->vsync_len + var->upper_margin > 2048) |
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return -EINVAL; |
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/* |
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* Check size of framebuffer. |
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*/ |
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if (var->xres_virtual * var->yres_virtual * |
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(var->bits_per_pixel >> 3) > info->fix.smem_len) |
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return -EINVAL; |
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return 0; |
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} |
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/* |
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* The hardware clock divider has an integer and a fractional |
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* stage: |
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* |
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* clk2 = clk_in / integer_divider |
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* clk_out = clk2 * (1 - (fractional_divider >> 12)) |
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* |
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* Calculate integer and fractional divider for given clk_in |
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* and clk_out. |
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*/ |
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static void set_clock_divider(struct pxa168fb_info *fbi, |
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const struct fb_videomode *m) |
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{ |
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int divider_int; |
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int needed_pixclk; |
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u64 div_result; |
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u32 x = 0; |
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|
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/* |
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* Notice: The field pixclock is used by linux fb |
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* is in pixel second. E.g. struct fb_videomode & |
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* struct fb_var_screeninfo |
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*/ |
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/* |
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* Check input values. |
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*/ |
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if (!m || !m->pixclock || !m->refresh) { |
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dev_err(fbi->dev, "Input refresh or pixclock is wrong.\n"); |
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return; |
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} |
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/* |
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* Using PLL/AXI clock. |
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*/ |
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x = 0x80000000; |
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/* |
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* Calc divider according to refresh rate. |
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*/ |
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div_result = 1000000000000ll; |
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do_div(div_result, m->pixclock); |
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needed_pixclk = (u32)div_result; |
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divider_int = clk_get_rate(fbi->clk) / needed_pixclk; |
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/* check whether divisor is too small. */ |
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if (divider_int < 2) { |
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dev_warn(fbi->dev, "Warning: clock source is too slow. " |
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"Try smaller resolution\n"); |
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divider_int = 2; |
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} |
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/* |
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* Set setting to reg. |
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*/ |
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x |= divider_int; |
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writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); |
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} |
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static void set_dma_control0(struct pxa168fb_info *fbi) |
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{ |
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u32 x; |
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/* |
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* Set bit to enable graphics DMA. |
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*/ |
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x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); |
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x &= ~CFG_GRA_ENA_MASK; |
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x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0); |
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/* |
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* If we are in a pseudo-color mode, we need to enable |
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* palette lookup. |
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*/ |
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if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR) |
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x |= 0x10000000; |
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/* |
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* Configure hardware pixel format. |
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*/ |
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x &= ~(0xF << 16); |
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x |= (fbi->pix_fmt >> 1) << 16; |
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/* |
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* Check red and blue pixel swap. |
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* 1. source data swap |
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* 2. panel output data swap |
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*/ |
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x &= ~(1 << 12); |
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x |= ((fbi->pix_fmt & 1) ^ (fbi->panel_rbswap)) << 12; |
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writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); |
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} |
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static void set_dma_control1(struct pxa168fb_info *fbi, int sync) |
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{ |
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u32 x; |
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/* |
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* Configure default bits: vsync triggers DMA, gated clock |
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* enable, power save enable, configure alpha registers to |
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* display 100% graphics, and set pixel command. |
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*/ |
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x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); |
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x |= 0x2032ff81; |
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|
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/* |
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* We trigger DMA on the falling edge of vsync if vsync is |
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* active low, or on the rising edge if vsync is active high. |
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*/ |
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if (!(sync & FB_SYNC_VERT_HIGH_ACT)) |
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x |= 0x08000000; |
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writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); |
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} |
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static void set_graphics_start(struct fb_info *info, int xoffset, int yoffset) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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struct fb_var_screeninfo *var = &info->var; |
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int pixel_offset; |
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unsigned long addr; |
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pixel_offset = (yoffset * var->xres_virtual) + xoffset; |
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addr = fbi->fb_start_dma + (pixel_offset * (var->bits_per_pixel >> 3)); |
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writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); |
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} |
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static void set_dumb_panel_control(struct fb_info *info) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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struct pxa168fb_mach_info *mi = dev_get_platdata(fbi->dev); |
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u32 x; |
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/* |
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* Preserve enable flag. |
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*/ |
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x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; |
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x |= (fbi->is_blanked ? 0x7 : mi->dumb_mode) << 28; |
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x |= mi->gpio_output_data << 20; |
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x |= mi->gpio_output_mask << 12; |
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x |= mi->panel_rgb_reverse_lanes ? 0x00000080 : 0; |
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x |= mi->invert_composite_blank ? 0x00000040 : 0; |
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x |= (info->var.sync & FB_SYNC_COMP_HIGH_ACT) ? 0x00000020 : 0; |
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x |= mi->invert_pix_val_ena ? 0x00000010 : 0; |
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x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008; |
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x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004; |
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x |= mi->invert_pixclock ? 0x00000002 : 0; |
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writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); |
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} |
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static void set_dumb_screen_dimensions(struct fb_info *info) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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struct fb_var_screeninfo *v = &info->var; |
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int x; |
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int y; |
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x = v->xres + v->right_margin + v->hsync_len + v->left_margin; |
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y = v->yres + v->lower_margin + v->vsync_len + v->upper_margin; |
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writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); |
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} |
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static int pxa168fb_set_par(struct fb_info *info) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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struct fb_var_screeninfo *var = &info->var; |
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struct fb_videomode mode; |
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u32 x; |
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/* |
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* Set additional mode info. |
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*/ |
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if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR) |
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
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else |
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info->fix.visual = FB_VISUAL_TRUECOLOR; |
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info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; |
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info->fix.ypanstep = var->yres; |
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/* |
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* Disable panel output while we setup the display. |
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*/ |
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x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); |
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writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); |
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/* |
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* Configure global panel parameters. |
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*/ |
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writel((var->yres << 16) | var->xres, |
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fbi->reg_base + LCD_SPU_V_H_ACTIVE); |
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|
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/* |
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* convet var to video mode |
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*/ |
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fb_var_to_videomode(&mode, &info->var); |
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|
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/* Calculate clock divisor. */ |
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set_clock_divider(fbi, &mode); |
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|
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/* Configure dma ctrl regs. */ |
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set_dma_control0(fbi); |
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set_dma_control1(fbi, info->var.sync); |
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|
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/* |
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* Configure graphics DMA parameters. |
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*/ |
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x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH); |
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x = (x & ~0xFFFF) | ((var->xres_virtual * var->bits_per_pixel) >> 3); |
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writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); |
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writel((var->yres << 16) | var->xres, |
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fbi->reg_base + LCD_SPU_GRA_HPXL_VLN); |
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writel((var->yres << 16) | var->xres, |
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fbi->reg_base + LCD_SPU_GZM_HPXL_VLN); |
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|
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/* |
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* Configure dumb panel ctrl regs & timings. |
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*/ |
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set_dumb_panel_control(info); |
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set_dumb_screen_dimensions(info); |
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|
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writel((var->left_margin << 16) | var->right_margin, |
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fbi->reg_base + LCD_SPU_H_PORCH); |
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writel((var->upper_margin << 16) | var->lower_margin, |
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fbi->reg_base + LCD_SPU_V_PORCH); |
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|
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/* |
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* Re-enable panel output. |
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*/ |
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x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); |
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writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL); |
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|
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return 0; |
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} |
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static unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf) |
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{ |
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return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset; |
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} |
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|
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static u32 to_rgb(u16 red, u16 green, u16 blue) |
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{ |
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red >>= 8; |
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green >>= 8; |
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blue >>= 8; |
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|
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return (red << 16) | (green << 8) | blue; |
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} |
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|
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static int |
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pxa168fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, |
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unsigned int blue, unsigned int trans, struct fb_info *info) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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u32 val; |
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|
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if (info->var.grayscale) |
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red = green = blue = (19595 * red + 38470 * green + |
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7471 * blue) >> 16; |
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|
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if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) { |
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val = chan_to_field(red, &info->var.red); |
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val |= chan_to_field(green, &info->var.green); |
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val |= chan_to_field(blue , &info->var.blue); |
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fbi->pseudo_palette[regno] = val; |
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} |
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|
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if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) { |
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val = to_rgb(red, green, blue); |
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writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT); |
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writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL); |
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} |
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|
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return 0; |
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} |
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static int pxa168fb_blank(int blank, struct fb_info *info) |
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{ |
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struct pxa168fb_info *fbi = info->par; |
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|
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fbi->is_blanked = (blank == FB_BLANK_UNBLANK) ? 0 : 1; |
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set_dumb_panel_control(info); |
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|
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return 0; |
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} |
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|
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static int pxa168fb_pan_display(struct fb_var_screeninfo *var, |
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struct fb_info *info) |
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{ |
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set_graphics_start(info, var->xoffset, var->yoffset); |
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|
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return 0; |
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} |
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|
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static irqreturn_t pxa168fb_handle_irq(int irq, void *dev_id) |
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{ |
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struct pxa168fb_info *fbi = dev_id; |
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u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR); |
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|
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if ((isr & GRA_FRAME_IRQ0_ENA_MASK)) { |
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|
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writel(isr & (~GRA_FRAME_IRQ0_ENA_MASK), |
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fbi->reg_base + SPU_IRQ_ISR); |
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|
|
return IRQ_HANDLED; |
|
} |
|
return IRQ_NONE; |
|
} |
|
|
|
static const struct fb_ops pxa168fb_ops = { |
|
.owner = THIS_MODULE, |
|
.fb_check_var = pxa168fb_check_var, |
|
.fb_set_par = pxa168fb_set_par, |
|
.fb_setcolreg = pxa168fb_setcolreg, |
|
.fb_blank = pxa168fb_blank, |
|
.fb_pan_display = pxa168fb_pan_display, |
|
.fb_fillrect = cfb_fillrect, |
|
.fb_copyarea = cfb_copyarea, |
|
.fb_imageblit = cfb_imageblit, |
|
}; |
|
|
|
static void pxa168fb_init_mode(struct fb_info *info, |
|
struct pxa168fb_mach_info *mi) |
|
{ |
|
struct pxa168fb_info *fbi = info->par; |
|
struct fb_var_screeninfo *var = &info->var; |
|
u32 total_w, total_h, refresh; |
|
u64 div_result; |
|
const struct fb_videomode *m; |
|
|
|
/* |
|
* Set default value |
|
*/ |
|
refresh = DEFAULT_REFRESH; |
|
|
|
/* try to find best video mode. */ |
|
m = fb_find_best_mode(&info->var, &info->modelist); |
|
if (m) |
|
fb_videomode_to_var(&info->var, m); |
|
|
|
/* Init settings. */ |
|
var->xres_virtual = var->xres; |
|
var->yres_virtual = info->fix.smem_len / |
|
(var->xres_virtual * (var->bits_per_pixel >> 3)); |
|
dev_dbg(fbi->dev, "pxa168fb: find best mode: res = %dx%d\n", |
|
var->xres, var->yres); |
|
|
|
/* correct pixclock. */ |
|
total_w = var->xres + var->left_margin + var->right_margin + |
|
var->hsync_len; |
|
total_h = var->yres + var->upper_margin + var->lower_margin + |
|
var->vsync_len; |
|
|
|
div_result = 1000000000000ll; |
|
do_div(div_result, total_w * total_h * refresh); |
|
var->pixclock = (u32)div_result; |
|
} |
|
|
|
static int pxa168fb_probe(struct platform_device *pdev) |
|
{ |
|
struct pxa168fb_mach_info *mi; |
|
struct fb_info *info = 0; |
|
struct pxa168fb_info *fbi = 0; |
|
struct resource *res; |
|
struct clk *clk; |
|
int irq, ret; |
|
|
|
mi = dev_get_platdata(&pdev->dev); |
|
if (mi == NULL) { |
|
dev_err(&pdev->dev, "no platform data defined\n"); |
|
return -EINVAL; |
|
} |
|
|
|
clk = devm_clk_get(&pdev->dev, "LCDCLK"); |
|
if (IS_ERR(clk)) { |
|
dev_err(&pdev->dev, "unable to get LCDCLK"); |
|
return PTR_ERR(clk); |
|
} |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (res == NULL) { |
|
dev_err(&pdev->dev, "no IO memory defined\n"); |
|
return -ENOENT; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
dev_err(&pdev->dev, "no IRQ defined\n"); |
|
return -ENOENT; |
|
} |
|
|
|
info = framebuffer_alloc(sizeof(struct pxa168fb_info), &pdev->dev); |
|
if (info == NULL) { |
|
return -ENOMEM; |
|
} |
|
|
|
/* Initialize private data */ |
|
fbi = info->par; |
|
fbi->info = info; |
|
fbi->clk = clk; |
|
fbi->dev = info->dev = &pdev->dev; |
|
fbi->panel_rbswap = mi->panel_rbswap; |
|
fbi->is_blanked = 0; |
|
fbi->active = mi->active; |
|
|
|
/* |
|
* Initialise static fb parameters. |
|
*/ |
|
info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK | |
|
FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN; |
|
info->node = -1; |
|
strlcpy(info->fix.id, mi->id, 16); |
|
info->fix.type = FB_TYPE_PACKED_PIXELS; |
|
info->fix.type_aux = 0; |
|
info->fix.xpanstep = 0; |
|
info->fix.ypanstep = 0; |
|
info->fix.ywrapstep = 0; |
|
info->fix.mmio_start = res->start; |
|
info->fix.mmio_len = resource_size(res); |
|
info->fix.accel = FB_ACCEL_NONE; |
|
info->fbops = &pxa168fb_ops; |
|
info->pseudo_palette = fbi->pseudo_palette; |
|
|
|
/* |
|
* Map LCD controller registers. |
|
*/ |
|
fbi->reg_base = devm_ioremap(&pdev->dev, res->start, |
|
resource_size(res)); |
|
if (fbi->reg_base == NULL) { |
|
ret = -ENOMEM; |
|
goto failed_free_info; |
|
} |
|
|
|
/* |
|
* Allocate framebuffer memory. |
|
*/ |
|
info->fix.smem_len = PAGE_ALIGN(DEFAULT_FB_SIZE); |
|
|
|
info->screen_base = dma_alloc_wc(fbi->dev, info->fix.smem_len, |
|
&fbi->fb_start_dma, GFP_KERNEL); |
|
if (info->screen_base == NULL) { |
|
ret = -ENOMEM; |
|
goto failed_free_info; |
|
} |
|
|
|
info->fix.smem_start = (unsigned long)fbi->fb_start_dma; |
|
set_graphics_start(info, 0, 0); |
|
|
|
/* |
|
* Set video mode according to platform data. |
|
*/ |
|
set_mode(fbi, &info->var, mi->modes, mi->pix_fmt, 1); |
|
|
|
fb_videomode_to_modelist(mi->modes, mi->num_modes, &info->modelist); |
|
|
|
/* |
|
* init video mode data. |
|
*/ |
|
pxa168fb_init_mode(info, mi); |
|
|
|
/* |
|
* Fill in sane defaults. |
|
*/ |
|
ret = pxa168fb_check_var(&info->var, info); |
|
if (ret) |
|
goto failed_free_fbmem; |
|
|
|
/* |
|
* enable controller clock |
|
*/ |
|
clk_prepare_enable(fbi->clk); |
|
|
|
pxa168fb_set_par(info); |
|
|
|
/* |
|
* Configure default register values. |
|
*/ |
|
writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR); |
|
writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL); |
|
writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1); |
|
writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN); |
|
writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0); |
|
writel(CFG_CSB_256x32(0x1)|CFG_CSB_256x24(0x1)|CFG_CSB_256x8(0x1), |
|
fbi->reg_base + LCD_SPU_SRAM_PARA1); |
|
|
|
/* |
|
* Allocate color map. |
|
*/ |
|
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { |
|
ret = -ENOMEM; |
|
goto failed_free_clk; |
|
} |
|
|
|
/* |
|
* Register irq handler. |
|
*/ |
|
ret = devm_request_irq(&pdev->dev, irq, pxa168fb_handle_irq, |
|
IRQF_SHARED, info->fix.id, fbi); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "unable to request IRQ\n"); |
|
ret = -ENXIO; |
|
goto failed_free_cmap; |
|
} |
|
|
|
/* |
|
* Enable GFX interrupt |
|
*/ |
|
writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA); |
|
|
|
/* |
|
* Register framebuffer. |
|
*/ |
|
ret = register_framebuffer(info); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to register pxa168-fb: %d\n", ret); |
|
ret = -ENXIO; |
|
goto failed_free_cmap; |
|
} |
|
|
|
platform_set_drvdata(pdev, fbi); |
|
return 0; |
|
|
|
failed_free_cmap: |
|
fb_dealloc_cmap(&info->cmap); |
|
failed_free_clk: |
|
clk_disable_unprepare(fbi->clk); |
|
failed_free_fbmem: |
|
dma_free_wc(fbi->dev, info->fix.smem_len, |
|
info->screen_base, fbi->fb_start_dma); |
|
failed_free_info: |
|
framebuffer_release(info); |
|
|
|
dev_err(&pdev->dev, "frame buffer device init failed with %d\n", ret); |
|
return ret; |
|
} |
|
|
|
static int pxa168fb_remove(struct platform_device *pdev) |
|
{ |
|
struct pxa168fb_info *fbi = platform_get_drvdata(pdev); |
|
struct fb_info *info; |
|
unsigned int data; |
|
|
|
if (!fbi) |
|
return 0; |
|
|
|
/* disable DMA transfer */ |
|
data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); |
|
data &= ~CFG_GRA_ENA_MASK; |
|
writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0); |
|
|
|
info = fbi->info; |
|
|
|
unregister_framebuffer(info); |
|
|
|
writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA); |
|
|
|
if (info->cmap.len) |
|
fb_dealloc_cmap(&info->cmap); |
|
|
|
dma_free_wc(fbi->dev, info->fix.smem_len, |
|
info->screen_base, info->fix.smem_start); |
|
|
|
clk_disable_unprepare(fbi->clk); |
|
|
|
framebuffer_release(info); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver pxa168fb_driver = { |
|
.driver = { |
|
.name = "pxa168-fb", |
|
}, |
|
.probe = pxa168fb_probe, |
|
.remove = pxa168fb_remove, |
|
}; |
|
|
|
module_platform_driver(pxa168fb_driver); |
|
|
|
MODULE_AUTHOR("Lennert Buytenhek <[email protected]> " |
|
"Green Wan <[email protected]>"); |
|
MODULE_DESCRIPTION("Framebuffer driver for PXA168/910"); |
|
MODULE_LICENSE("GPL");
|
|
|