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189 lines
5.5 KiB
189 lines
5.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* drivers/video/geode/video_cs5530.c |
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* -- CS5530 video device |
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* |
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* Copyright (C) 2005 Arcom Control Systems Ltd. |
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* |
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* Based on AMD's original 2.4 driver: |
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* Copyright (C) 2004 Advanced Micro Devices, Inc. |
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*/ |
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#include <linux/fb.h> |
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#include <linux/delay.h> |
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#include <asm/io.h> |
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#include <asm/delay.h> |
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#include "geodefb.h" |
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#include "video_cs5530.h" |
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/* |
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* CS5530 PLL table. This maps pixclocks to the appropriate PLL register |
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* value. |
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*/ |
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struct cs5530_pll_entry { |
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long pixclock; /* ps */ |
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u32 pll_value; |
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}; |
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static const struct cs5530_pll_entry cs5530_pll_table[] = { |
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{ 39721, 0x31C45801, }, /* 25.1750 MHz */ |
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{ 35308, 0x20E36802, }, /* 28.3220 */ |
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{ 31746, 0x33915801, }, /* 31.5000 */ |
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{ 27777, 0x31EC4801, }, /* 36.0000 */ |
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{ 26666, 0x21E22801, }, /* 37.5000 */ |
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{ 25000, 0x33088801, }, /* 40.0000 */ |
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{ 22271, 0x33E22801, }, /* 44.9000 */ |
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{ 20202, 0x336C4801, }, /* 49.5000 */ |
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{ 20000, 0x23088801, }, /* 50.0000 */ |
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{ 19860, 0x23088801, }, /* 50.3500 */ |
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{ 18518, 0x3708A801, }, /* 54.0000 */ |
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{ 17777, 0x23E36802, }, /* 56.2500 */ |
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{ 17733, 0x23E36802, }, /* 56.3916 */ |
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{ 17653, 0x23E36802, }, /* 56.6444 */ |
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{ 16949, 0x37C45801, }, /* 59.0000 */ |
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{ 15873, 0x23EC4801, }, /* 63.0000 */ |
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{ 15384, 0x37911801, }, /* 65.0000 */ |
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{ 14814, 0x37963803, }, /* 67.5000 */ |
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{ 14124, 0x37058803, }, /* 70.8000 */ |
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{ 13888, 0x3710C805, }, /* 72.0000 */ |
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{ 13333, 0x37E22801, }, /* 75.0000 */ |
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{ 12698, 0x27915801, }, /* 78.7500 */ |
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{ 12500, 0x37D8D802, }, /* 80.0000 */ |
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{ 11135, 0x27588802, }, /* 89.8000 */ |
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{ 10582, 0x27EC4802, }, /* 94.5000 */ |
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{ 10101, 0x27AC6803, }, /* 99.0000 */ |
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{ 10000, 0x27088801, }, /* 100.0000 */ |
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{ 9259, 0x2710C805, }, /* 108.0000 */ |
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{ 8888, 0x27E36802, }, /* 112.5000 */ |
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{ 7692, 0x27C58803, }, /* 130.0000 */ |
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{ 7407, 0x27316803, }, /* 135.0000 */ |
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{ 6349, 0x2F915801, }, /* 157.5000 */ |
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{ 6172, 0x2F08A801, }, /* 162.0000 */ |
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{ 5714, 0x2FB11802, }, /* 175.0000 */ |
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{ 5291, 0x2FEC4802, }, /* 189.0000 */ |
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{ 4950, 0x2F963803, }, /* 202.0000 */ |
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{ 4310, 0x2FB1B802, }, /* 232.0000 */ |
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}; |
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static void cs5530_set_dclk_frequency(struct fb_info *info) |
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{ |
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struct geodefb_par *par = info->par; |
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int i; |
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u32 value; |
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long min, diff; |
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/* Search the table for the closest pixclock. */ |
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value = cs5530_pll_table[0].pll_value; |
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min = cs5530_pll_table[0].pixclock - info->var.pixclock; |
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if (min < 0) min = -min; |
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for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) { |
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diff = cs5530_pll_table[i].pixclock - info->var.pixclock; |
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if (diff < 0L) diff = -diff; |
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if (diff < min) { |
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min = diff; |
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value = cs5530_pll_table[i].pll_value; |
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} |
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} |
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writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG); |
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writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */ |
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udelay(500); /* wait for PLL to settle */ |
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writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */ |
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writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */ |
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} |
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static void cs5530_configure_display(struct fb_info *info) |
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{ |
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struct geodefb_par *par = info->par; |
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u32 dcfg; |
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dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); |
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/* Clear bits from existing mode. */ |
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dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK |
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| CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL |
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| CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN |
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| CS5530_DCFG_DAC_PWR_EN | CS5530_DCFG_VSYNC_EN |
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| CS5530_DCFG_HSYNC_EN); |
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/* Set default sync skew and power sequence delays. */ |
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dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT |
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| CS5530_DCFG_GV_PAL_BYP); |
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/* Enable DACs, hsync and vsync for CRTs */ |
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if (par->enable_crt) { |
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dcfg |= CS5530_DCFG_DAC_PWR_EN; |
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dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN; |
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} |
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/* Enable panel power and data if using a flat panel. */ |
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if (par->panel_x > 0) { |
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dcfg |= CS5530_DCFG_FP_PWR_EN; |
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dcfg |= CS5530_DCFG_FP_DATA_EN; |
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} |
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/* Sync polarities. */ |
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if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) |
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dcfg |= CS5530_DCFG_CRT_HSYNC_POL; |
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if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) |
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dcfg |= CS5530_DCFG_CRT_VSYNC_POL; |
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writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); |
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} |
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static int cs5530_blank_display(struct fb_info *info, int blank_mode) |
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{ |
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struct geodefb_par *par = info->par; |
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u32 dcfg; |
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int blank, hsync, vsync; |
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switch (blank_mode) { |
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case FB_BLANK_UNBLANK: |
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blank = 0; hsync = 1; vsync = 1; |
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break; |
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case FB_BLANK_NORMAL: |
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blank = 1; hsync = 1; vsync = 1; |
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break; |
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case FB_BLANK_VSYNC_SUSPEND: |
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blank = 1; hsync = 1; vsync = 0; |
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break; |
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case FB_BLANK_HSYNC_SUSPEND: |
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blank = 1; hsync = 0; vsync = 1; |
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break; |
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case FB_BLANK_POWERDOWN: |
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blank = 1; hsync = 0; vsync = 0; |
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break; |
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default: |
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return -EINVAL; |
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} |
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dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); |
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dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN |
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| CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN |
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| CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN); |
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if (par->enable_crt) { |
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if (!blank) |
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dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN; |
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if (hsync) |
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dcfg |= CS5530_DCFG_HSYNC_EN; |
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if (vsync) |
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dcfg |= CS5530_DCFG_VSYNC_EN; |
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} |
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if (par->panel_x > 0) { |
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if (!blank) |
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dcfg |= CS5530_DCFG_FP_DATA_EN; |
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if (hsync && vsync) |
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dcfg |= CS5530_DCFG_FP_PWR_EN; |
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} |
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writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); |
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return 0; |
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} |
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const struct geode_vid_ops cs5530_vid_ops = { |
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.set_dclk = cs5530_set_dclk_frequency, |
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.configure_display = cs5530_configure_display, |
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.blank_display = cs5530_blank_display, |
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};
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