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672 lines
20 KiB
672 lines
20 KiB
/* |
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* Common utility functions for VGA-based graphics cards. |
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* |
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* Copyright (c) 2006-2007 Ondrej Zajicek <[email protected]> |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive for |
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* more details. |
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* |
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* Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/fb.h> |
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#include <linux/svga.h> |
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#include <asm/types.h> |
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#include <asm/io.h> |
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/* Write a CRT register value spread across multiple registers */ |
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void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) |
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{ |
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u8 regval, bitval, bitnum; |
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while (regset->regnum != VGA_REGSET_END_VAL) { |
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regval = vga_rcrt(regbase, regset->regnum); |
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bitnum = regset->lowbit; |
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while (bitnum <= regset->highbit) { |
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bitval = 1 << bitnum; |
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regval = regval & ~bitval; |
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if (value & 1) regval = regval | bitval; |
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bitnum ++; |
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value = value >> 1; |
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} |
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vga_wcrt(regbase, regset->regnum, regval); |
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regset ++; |
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} |
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} |
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/* Write a sequencer register value spread across multiple registers */ |
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void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) |
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{ |
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u8 regval, bitval, bitnum; |
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while (regset->regnum != VGA_REGSET_END_VAL) { |
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regval = vga_rseq(regbase, regset->regnum); |
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bitnum = regset->lowbit; |
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while (bitnum <= regset->highbit) { |
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bitval = 1 << bitnum; |
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regval = regval & ~bitval; |
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if (value & 1) regval = regval | bitval; |
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bitnum ++; |
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value = value >> 1; |
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} |
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vga_wseq(regbase, regset->regnum, regval); |
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regset ++; |
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} |
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} |
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static unsigned int svga_regset_size(const struct vga_regset *regset) |
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{ |
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u8 count = 0; |
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while (regset->regnum != VGA_REGSET_END_VAL) { |
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count += regset->highbit - regset->lowbit + 1; |
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regset ++; |
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} |
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return 1 << count; |
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} |
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/* ------------------------------------------------------------------------- */ |
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/* Set graphics controller registers to sane values */ |
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void svga_set_default_gfx_regs(void __iomem *regbase) |
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{ |
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/* All standard GFX registers (GR00 - GR08) */ |
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vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00); |
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vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00); |
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vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00); |
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vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00); |
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vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00); |
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vga_wgfx(regbase, VGA_GFX_MODE, 0x00); |
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/* vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */ |
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/* vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */ |
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vga_wgfx(regbase, VGA_GFX_MISC, 0x05); |
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/* vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */ |
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vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F); |
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vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF); |
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} |
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/* Set attribute controller registers to sane values */ |
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void svga_set_default_atc_regs(void __iomem *regbase) |
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{ |
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u8 count; |
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vga_r(regbase, 0x3DA); |
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vga_w(regbase, VGA_ATT_W, 0x00); |
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/* All standard ATC registers (AR00 - AR14) */ |
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for (count = 0; count <= 0xF; count ++) |
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svga_wattr(regbase, count, count); |
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svga_wattr(regbase, VGA_ATC_MODE, 0x01); |
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/* svga_wattr(regbase, VGA_ATC_MODE, 0x41); */ |
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svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00); |
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svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F); |
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svga_wattr(regbase, VGA_ATC_PEL, 0x00); |
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svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00); |
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vga_r(regbase, 0x3DA); |
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vga_w(regbase, VGA_ATT_W, 0x20); |
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} |
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/* Set sequencer registers to sane values */ |
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void svga_set_default_seq_regs(void __iomem *regbase) |
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{ |
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/* Standard sequencer registers (SR01 - SR04), SR00 is not set */ |
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vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS); |
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vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES); |
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vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00); |
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/* vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */ |
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vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE); |
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} |
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/* Set CRTC registers to sane values */ |
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void svga_set_default_crt_regs(void __iomem *regbase) |
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{ |
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/* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */ |
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svga_wcrt_mask(regbase, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ |
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vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0); |
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svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F); |
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vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0); |
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vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3); |
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} |
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void svga_set_textmode_vga_regs(void __iomem *regbase) |
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{ |
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/* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ |
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vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM); |
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vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03); |
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vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */ |
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vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f); |
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svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f); |
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vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d); |
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vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e); |
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vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00); |
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vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00); |
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vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */ |
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vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */ |
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vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00); |
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vga_r(regbase, 0x3DA); |
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vga_w(regbase, VGA_ATT_W, 0x00); |
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svga_wattr(regbase, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ |
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svga_wattr(regbase, 0x13, 0x08); /* Horizontal Pixel Panning Register */ |
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vga_r(regbase, 0x3DA); |
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vga_w(regbase, VGA_ATT_W, 0x20); |
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} |
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#if 0 |
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void svga_dump_var(struct fb_var_screeninfo *var, int node) |
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{ |
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pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode); |
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pr_debug("fb%d: var.xres : %d\n", node, var->xres); |
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pr_debug("fb%d: var.yres : %d\n", node, var->yres); |
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pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel); |
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pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual); |
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pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual); |
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pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin); |
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pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin); |
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pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin); |
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pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin); |
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pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len); |
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pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len); |
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pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync); |
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pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock); |
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} |
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#endif /* 0 */ |
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/* ------------------------------------------------------------------------- */ |
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void svga_settile(struct fb_info *info, struct fb_tilemap *map) |
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{ |
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const u8 *font = map->data; |
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u8 __iomem *fb = (u8 __iomem *)info->screen_base; |
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int i, c; |
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if ((map->width != 8) || (map->height != 16) || |
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(map->depth != 1) || (map->length != 256)) { |
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fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", |
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map->width, map->height, map->depth, map->length); |
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return; |
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} |
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fb += 2; |
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for (c = 0; c < map->length; c++) { |
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for (i = 0; i < map->height; i++) { |
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fb_writeb(font[i], fb + i * 4); |
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// fb[i * 4] = font[i]; |
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} |
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fb += 128; |
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font += map->height; |
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} |
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} |
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/* Copy area in text (tileblit) mode */ |
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void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area) |
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{ |
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int dx, dy; |
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/* colstride is halved in this function because u16 are used */ |
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int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); |
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int rowstride = colstride * (info->var.xres_virtual / 8); |
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u16 __iomem *fb = (u16 __iomem *) info->screen_base; |
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u16 __iomem *src, *dst; |
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if ((area->sy > area->dy) || |
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((area->sy == area->dy) && (area->sx > area->dx))) { |
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src = fb + area->sx * colstride + area->sy * rowstride; |
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dst = fb + area->dx * colstride + area->dy * rowstride; |
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} else { |
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src = fb + (area->sx + area->width - 1) * colstride |
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+ (area->sy + area->height - 1) * rowstride; |
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dst = fb + (area->dx + area->width - 1) * colstride |
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+ (area->dy + area->height - 1) * rowstride; |
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colstride = -colstride; |
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rowstride = -rowstride; |
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} |
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for (dy = 0; dy < area->height; dy++) { |
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u16 __iomem *src2 = src; |
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u16 __iomem *dst2 = dst; |
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for (dx = 0; dx < area->width; dx++) { |
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fb_writew(fb_readw(src2), dst2); |
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// *dst2 = *src2; |
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src2 += colstride; |
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dst2 += colstride; |
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} |
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src += rowstride; |
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dst += rowstride; |
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} |
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} |
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/* Fill area in text (tileblit) mode */ |
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void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect) |
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{ |
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int dx, dy; |
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int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); |
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int rowstride = colstride * (info->var.xres_virtual / 8); |
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int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg); |
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u8 __iomem *fb = (u8 __iomem *)info->screen_base; |
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fb += rect->sx * colstride + rect->sy * rowstride; |
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for (dy = 0; dy < rect->height; dy++) { |
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u8 __iomem *fb2 = fb; |
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for (dx = 0; dx < rect->width; dx++) { |
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fb_writeb(rect->index, fb2); |
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fb_writeb(attr, fb2 + 1); |
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fb2 += colstride; |
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} |
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fb += rowstride; |
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} |
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} |
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/* Write text in text (tileblit) mode */ |
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void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit) |
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{ |
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int dx, dy, i; |
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int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); |
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int rowstride = colstride * (info->var.xres_virtual / 8); |
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int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg); |
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u8 __iomem *fb = (u8 __iomem *)info->screen_base; |
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fb += blit->sx * colstride + blit->sy * rowstride; |
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i=0; |
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for (dy=0; dy < blit->height; dy ++) { |
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u8 __iomem *fb2 = fb; |
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for (dx = 0; dx < blit->width; dx ++) { |
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fb_writeb(blit->indices[i], fb2); |
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fb_writeb(attr, fb2 + 1); |
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fb2 += colstride; |
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i ++; |
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if (i == blit->length) return; |
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} |
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fb += rowstride; |
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} |
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} |
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/* Set cursor in text (tileblit) mode */ |
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void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor) |
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{ |
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u8 cs = 0x0d; |
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u8 ce = 0x0e; |
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u16 pos = cursor->sx + (info->var.xoffset / 8) |
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+ (cursor->sy + (info->var.yoffset / 16)) |
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* (info->var.xres_virtual / 8); |
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if (! cursor -> mode) |
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return; |
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svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */ |
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if (cursor -> shape == FB_TILE_CURSOR_NONE) |
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return; |
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switch (cursor -> shape) { |
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case FB_TILE_CURSOR_UNDERLINE: |
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cs = 0x0d; |
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break; |
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case FB_TILE_CURSOR_LOWER_THIRD: |
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cs = 0x09; |
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break; |
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case FB_TILE_CURSOR_LOWER_HALF: |
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cs = 0x07; |
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break; |
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case FB_TILE_CURSOR_TWO_THIRDS: |
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cs = 0x05; |
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break; |
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case FB_TILE_CURSOR_BLOCK: |
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cs = 0x01; |
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break; |
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} |
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/* set cursor position */ |
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vga_wcrt(regbase, 0x0E, pos >> 8); |
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vga_wcrt(regbase, 0x0F, pos & 0xFF); |
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vga_wcrt(regbase, 0x0B, ce); /* set cursor end */ |
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vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */ |
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} |
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int svga_get_tilemax(struct fb_info *info) |
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{ |
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return 256; |
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} |
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/* Get capabilities of accelerator based on the mode */ |
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void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps, |
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struct fb_var_screeninfo *var) |
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{ |
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if (var->bits_per_pixel == 0) { |
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/* can only support 256 8x16 bitmap */ |
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caps->x = 1 << (8 - 1); |
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caps->y = 1 << (16 - 1); |
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caps->len = 256; |
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} else { |
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caps->x = (var->bits_per_pixel == 4) ? 1 << (8 - 1) : ~(u32)0; |
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caps->y = ~(u32)0; |
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caps->len = ~(u32)0; |
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} |
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} |
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EXPORT_SYMBOL(svga_get_caps); |
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/* ------------------------------------------------------------------------- */ |
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/* |
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* Compute PLL settings (M, N, R) |
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* F_VCO = (F_BASE * M) / N |
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* F_OUT = F_VCO / (2^R) |
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*/ |
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static inline u32 abs_diff(u32 a, u32 b) |
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{ |
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return (a > b) ? (a - b) : (b - a); |
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} |
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int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) |
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{ |
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u16 am, an, ar; |
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u32 f_vco, f_current, delta_current, delta_best; |
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pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted); |
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ar = pll->r_max; |
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f_vco = f_wanted << ar; |
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/* overflow check */ |
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if ((f_vco >> ar) != f_wanted) |
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return -EINVAL; |
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/* It is usually better to have greater VCO clock |
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because of better frequency stability. |
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So first try r_max, then r smaller. */ |
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while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { |
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ar--; |
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f_vco = f_vco >> 1; |
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} |
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/* VCO bounds check */ |
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if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) |
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return -EINVAL; |
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delta_best = 0xFFFFFFFF; |
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*m = 0; |
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*n = 0; |
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*r = ar; |
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am = pll->m_min; |
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an = pll->n_min; |
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while ((am <= pll->m_max) && (an <= pll->n_max)) { |
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f_current = (pll->f_base * am) / an; |
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delta_current = abs_diff (f_current, f_vco); |
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if (delta_current < delta_best) { |
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delta_best = delta_current; |
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*m = am; |
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*n = an; |
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} |
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if (f_current <= f_vco) { |
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am ++; |
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} else { |
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an ++; |
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} |
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} |
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f_current = (pll->f_base * *m) / *n; |
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pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current); |
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pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r); |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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/* Check CRT timing values */ |
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int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node) |
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{ |
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u32 value; |
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var->xres = (var->xres+7)&~7; |
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var->left_margin = (var->left_margin+7)&~7; |
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var->right_margin = (var->right_margin+7)&~7; |
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var->hsync_len = (var->hsync_len+7)&~7; |
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|
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/* Check horizontal total */ |
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value = var->xres + var->left_margin + var->right_margin + var->hsync_len; |
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if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs)) |
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return -EINVAL; |
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|
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/* Check horizontal display and blank start */ |
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value = var->xres; |
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if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs)) |
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return -EINVAL; |
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if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs)) |
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return -EINVAL; |
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|
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/* Check horizontal sync start */ |
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value = var->xres + var->right_margin; |
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if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs)) |
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return -EINVAL; |
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|
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/* Check horizontal blank end (or length) */ |
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value = var->left_margin + var->right_margin + var->hsync_len; |
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if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs))) |
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return -EINVAL; |
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|
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/* Check horizontal sync end (or length) */ |
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value = var->hsync_len; |
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if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs))) |
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return -EINVAL; |
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|
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/* Check vertical total */ |
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value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; |
|
if ((value - 1) >= svga_regset_size(tm->v_total_regs)) |
|
return -EINVAL; |
|
|
|
/* Check vertical display and blank start */ |
|
value = var->yres; |
|
if ((value - 1) >= svga_regset_size(tm->v_display_regs)) |
|
return -EINVAL; |
|
if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs)) |
|
return -EINVAL; |
|
|
|
/* Check vertical sync start */ |
|
value = var->yres + var->lower_margin; |
|
if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs)) |
|
return -EINVAL; |
|
|
|
/* Check vertical blank end (or length) */ |
|
value = var->upper_margin + var->lower_margin + var->vsync_len; |
|
if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs))) |
|
return -EINVAL; |
|
|
|
/* Check vertical sync end (or length) */ |
|
value = var->vsync_len; |
|
if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs))) |
|
return -EINVAL; |
|
|
|
return 0; |
|
} |
|
|
|
/* Set CRT timing registers */ |
|
void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm, |
|
struct fb_var_screeninfo *var, |
|
u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) |
|
{ |
|
u8 regval; |
|
u32 value; |
|
|
|
value = var->xres + var->left_margin + var->right_margin + var->hsync_len; |
|
value = (value * hmul) / hdiv; |
|
pr_debug("fb%d: horizontal total : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5); |
|
|
|
value = var->xres; |
|
value = (value * hmul) / hdiv; |
|
pr_debug("fb%d: horizontal display : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1); |
|
|
|
value = var->xres; |
|
value = (value * hmul) / hdiv; |
|
pr_debug("fb%d: horizontal blank start: %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder); |
|
|
|
value = var->xres + var->left_margin + var->right_margin + var->hsync_len; |
|
value = (value * hmul) / hdiv; |
|
pr_debug("fb%d: horizontal blank end : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder); |
|
|
|
value = var->xres + var->right_margin; |
|
value = (value * hmul) / hdiv; |
|
pr_debug("fb%d: horizontal sync start : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8)); |
|
|
|
value = var->xres + var->right_margin + var->hsync_len; |
|
value = (value * hmul) / hdiv; |
|
pr_debug("fb%d: horizontal sync end : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8)); |
|
|
|
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; |
|
value = (value * vmul) / vdiv; |
|
pr_debug("fb%d: vertical total : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->v_total_regs, value - 2); |
|
|
|
value = var->yres; |
|
value = (value * vmul) / vdiv; |
|
pr_debug("fb%d: vertical display : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->v_display_regs, value - 1); |
|
|
|
value = var->yres; |
|
value = (value * vmul) / vdiv; |
|
pr_debug("fb%d: vertical blank start : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->v_blank_start_regs, value); |
|
|
|
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; |
|
value = (value * vmul) / vdiv; |
|
pr_debug("fb%d: vertical blank end : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2); |
|
|
|
value = var->yres + var->lower_margin; |
|
value = (value * vmul) / vdiv; |
|
pr_debug("fb%d: vertical sync start : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->v_sync_start_regs, value); |
|
|
|
value = var->yres + var->lower_margin + var->vsync_len; |
|
value = (value * vmul) / vdiv; |
|
pr_debug("fb%d: vertical sync end : %d\n", node, value); |
|
svga_wcrt_multi(regbase, tm->v_sync_end_regs, value); |
|
|
|
/* Set horizontal and vertical sync pulse polarity in misc register */ |
|
|
|
regval = vga_r(regbase, VGA_MIS_R); |
|
if (var->sync & FB_SYNC_HOR_HIGH_ACT) { |
|
pr_debug("fb%d: positive horizontal sync\n", node); |
|
regval = regval & ~0x80; |
|
} else { |
|
pr_debug("fb%d: negative horizontal sync\n", node); |
|
regval = regval | 0x80; |
|
} |
|
if (var->sync & FB_SYNC_VERT_HIGH_ACT) { |
|
pr_debug("fb%d: positive vertical sync\n", node); |
|
regval = regval & ~0x40; |
|
} else { |
|
pr_debug("fb%d: negative vertical sync\n\n", node); |
|
regval = regval | 0x40; |
|
} |
|
vga_w(regbase, VGA_MIS_W, regval); |
|
} |
|
|
|
|
|
/* ------------------------------------------------------------------------- */ |
|
|
|
|
|
static inline int match_format(const struct svga_fb_format *frm, |
|
struct fb_var_screeninfo *var) |
|
{ |
|
int i = 0; |
|
int stored = -EINVAL; |
|
|
|
while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL) |
|
{ |
|
if ((var->bits_per_pixel == frm->bits_per_pixel) && |
|
(var->red.length <= frm->red.length) && |
|
(var->green.length <= frm->green.length) && |
|
(var->blue.length <= frm->blue.length) && |
|
(var->transp.length <= frm->transp.length) && |
|
(var->nonstd == frm->nonstd)) |
|
return i; |
|
if (var->bits_per_pixel == frm->bits_per_pixel) |
|
stored = i; |
|
i++; |
|
frm++; |
|
} |
|
return stored; |
|
} |
|
|
|
int svga_match_format(const struct svga_fb_format *frm, |
|
struct fb_var_screeninfo *var, |
|
struct fb_fix_screeninfo *fix) |
|
{ |
|
int i = match_format(frm, var); |
|
|
|
if (i >= 0) { |
|
var->bits_per_pixel = frm[i].bits_per_pixel; |
|
var->red = frm[i].red; |
|
var->green = frm[i].green; |
|
var->blue = frm[i].blue; |
|
var->transp = frm[i].transp; |
|
var->nonstd = frm[i].nonstd; |
|
if (fix != NULL) { |
|
fix->type = frm[i].type; |
|
fix->type_aux = frm[i].type_aux; |
|
fix->visual = frm[i].visual; |
|
fix->xpanstep = frm[i].xpanstep; |
|
} |
|
} |
|
|
|
return i; |
|
} |
|
|
|
|
|
EXPORT_SYMBOL(svga_wcrt_multi); |
|
EXPORT_SYMBOL(svga_wseq_multi); |
|
|
|
EXPORT_SYMBOL(svga_set_default_gfx_regs); |
|
EXPORT_SYMBOL(svga_set_default_atc_regs); |
|
EXPORT_SYMBOL(svga_set_default_seq_regs); |
|
EXPORT_SYMBOL(svga_set_default_crt_regs); |
|
EXPORT_SYMBOL(svga_set_textmode_vga_regs); |
|
|
|
EXPORT_SYMBOL(svga_settile); |
|
EXPORT_SYMBOL(svga_tilecopy); |
|
EXPORT_SYMBOL(svga_tilefill); |
|
EXPORT_SYMBOL(svga_tileblit); |
|
EXPORT_SYMBOL(svga_tilecursor); |
|
EXPORT_SYMBOL(svga_get_tilemax); |
|
|
|
EXPORT_SYMBOL(svga_compute_pll); |
|
EXPORT_SYMBOL(svga_check_timings); |
|
EXPORT_SYMBOL(svga_set_timings); |
|
EXPORT_SYMBOL(svga_match_format); |
|
|
|
MODULE_AUTHOR("Ondrej Zajicek <[email protected]>"); |
|
MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards"); |
|
MODULE_LICENSE("GPL");
|
|
|