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301 lines
8.2 KiB
301 lines
8.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2021 The Linux Foundation. All rights reserved. |
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* |
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* lpass-cdc-dma.c -- ALSA SoC CDC DMA CPU DAI driver for QTi LPASS |
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*/ |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/export.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dai.h> |
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#include "lpass-lpaif-reg.h" |
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#include "lpass.h" |
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#define CODEC_MEM_HZ_NORMAL 153600000 |
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enum codec_dma_interfaces { |
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LPASS_CDC_DMA_INTERFACE1 = 1, |
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LPASS_CDC_DMA_INTERFACE2, |
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LPASS_CDC_DMA_INTERFACE3, |
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LPASS_CDC_DMA_INTERFACE4, |
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LPASS_CDC_DMA_INTERFACE5, |
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LPASS_CDC_DMA_INTERFACE6, |
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LPASS_CDC_DMA_INTERFACE7, |
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LPASS_CDC_DMA_INTERFACE8, |
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LPASS_CDC_DMA_INTERFACE9, |
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LPASS_CDC_DMA_INTERFACE10, |
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}; |
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static void __lpass_get_dmactl_handle(struct snd_pcm_substream *substream, struct snd_soc_dai *dai, |
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struct lpaif_dmactl **dmactl, int *id) |
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{ |
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); |
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struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0); |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct snd_pcm_runtime *rt = substream->runtime; |
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struct lpass_pcm_data *pcm_data = rt->private_data; |
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struct lpass_variant *v = drvdata->variant; |
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unsigned int dai_id = cpu_dai->driver->id; |
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switch (dai_id) { |
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: |
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*dmactl = drvdata->rxtx_rd_dmactl; |
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*id = pcm_data->dma_ch; |
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break; |
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: |
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*dmactl = drvdata->rxtx_wr_dmactl; |
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*id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start; |
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break; |
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case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: |
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*dmactl = drvdata->va_wr_dmactl; |
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*id = pcm_data->dma_ch - v->va_wrdma_channel_start; |
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break; |
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default: |
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dev_err(soc_runtime->dev, "invalid dai id for dma ctl: %d\n", dai_id); |
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break; |
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} |
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} |
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static int __lpass_get_codec_dma_intf_type(int dai_id) |
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{ |
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int ret; |
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switch (dai_id) { |
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case LPASS_CDC_DMA_RX0: |
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case LPASS_CDC_DMA_TX0: |
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case LPASS_CDC_DMA_VA_TX0: |
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ret = LPASS_CDC_DMA_INTERFACE1; |
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break; |
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case LPASS_CDC_DMA_RX1: |
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case LPASS_CDC_DMA_TX1: |
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case LPASS_CDC_DMA_VA_TX1: |
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ret = LPASS_CDC_DMA_INTERFACE2; |
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break; |
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case LPASS_CDC_DMA_RX2: |
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case LPASS_CDC_DMA_TX2: |
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case LPASS_CDC_DMA_VA_TX2: |
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ret = LPASS_CDC_DMA_INTERFACE3; |
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break; |
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case LPASS_CDC_DMA_RX3: |
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case LPASS_CDC_DMA_TX3: |
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case LPASS_CDC_DMA_VA_TX3: |
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ret = LPASS_CDC_DMA_INTERFACE4; |
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break; |
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case LPASS_CDC_DMA_RX4: |
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case LPASS_CDC_DMA_TX4: |
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case LPASS_CDC_DMA_VA_TX4: |
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ret = LPASS_CDC_DMA_INTERFACE5; |
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break; |
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case LPASS_CDC_DMA_RX5: |
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case LPASS_CDC_DMA_TX5: |
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case LPASS_CDC_DMA_VA_TX5: |
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ret = LPASS_CDC_DMA_INTERFACE6; |
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break; |
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case LPASS_CDC_DMA_RX6: |
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case LPASS_CDC_DMA_TX6: |
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case LPASS_CDC_DMA_VA_TX6: |
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ret = LPASS_CDC_DMA_INTERFACE7; |
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break; |
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case LPASS_CDC_DMA_RX7: |
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case LPASS_CDC_DMA_TX7: |
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case LPASS_CDC_DMA_VA_TX7: |
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ret = LPASS_CDC_DMA_INTERFACE8; |
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break; |
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case LPASS_CDC_DMA_RX8: |
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case LPASS_CDC_DMA_TX8: |
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case LPASS_CDC_DMA_VA_TX8: |
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ret = LPASS_CDC_DMA_INTERFACE9; |
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break; |
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case LPASS_CDC_DMA_RX9: |
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ret = LPASS_CDC_DMA_INTERFACE10; |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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return ret; |
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} |
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static int __lpass_platform_codec_intf_init(struct snd_soc_dai *dai, |
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struct snd_pcm_substream *substream) |
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{ |
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); |
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struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0); |
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struct lpaif_dmactl *dmactl = NULL; |
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struct device *dev = soc_runtime->dev; |
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int ret, id, codec_intf; |
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unsigned int dai_id = cpu_dai->driver->id; |
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codec_intf = __lpass_get_codec_dma_intf_type(dai_id); |
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if (codec_intf < 0) { |
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dev_err(dev, "failed to get codec_intf: %d\n", codec_intf); |
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return codec_intf; |
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} |
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__lpass_get_dmactl_handle(substream, dai, &dmactl, &id); |
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if (!dmactl) |
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return -EINVAL; |
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ret = regmap_fields_write(dmactl->codec_intf, id, codec_intf); |
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if (ret) { |
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dev_err(dev, "error writing to dmactl codec_intf reg field: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_fields_write(dmactl->codec_fs_sel, id, 0x0); |
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if (ret) { |
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dev_err(dev, "error writing to dmactl codec_fs_sel reg field: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_fields_write(dmactl->codec_fs_delay, id, 0x0); |
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if (ret) { |
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dev_err(dev, "error writing to dmactl codec_fs_delay reg field: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_fields_write(dmactl->codec_pack, id, 0x1); |
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if (ret) { |
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dev_err(dev, "error writing to dmactl codec_pack reg field: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_ON); |
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if (ret) { |
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dev_err(dev, "error writing to dmactl codec_enable reg field: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int lpass_cdc_dma_daiops_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); |
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switch (dai->id) { |
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: |
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: |
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clk_set_rate(drvdata->codec_mem0, CODEC_MEM_HZ_NORMAL); |
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clk_prepare_enable(drvdata->codec_mem0); |
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break; |
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case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0: |
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clk_set_rate(drvdata->va_mem0, CODEC_MEM_HZ_NORMAL); |
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clk_prepare_enable(drvdata->va_mem0); |
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break; |
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default: |
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dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id); |
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break; |
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} |
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return 0; |
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} |
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static void lpass_cdc_dma_daiops_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); |
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); |
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switch (dai->id) { |
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: |
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: |
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clk_disable_unprepare(drvdata->codec_mem0); |
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break; |
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case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0: |
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clk_disable_unprepare(drvdata->va_mem0); |
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break; |
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default: |
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dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id); |
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break; |
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} |
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} |
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static int lpass_cdc_dma_daiops_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); |
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struct lpaif_dmactl *dmactl = NULL; |
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unsigned int ret, regval; |
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unsigned int channels = params_channels(params); |
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int id; |
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switch (channels) { |
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case 1: |
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regval = LPASS_CDC_DMA_INTF_ONE_CHANNEL; |
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break; |
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case 2: |
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regval = LPASS_CDC_DMA_INTF_TWO_CHANNEL; |
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break; |
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case 4: |
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regval = LPASS_CDC_DMA_INTF_FOUR_CHANNEL; |
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break; |
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case 6: |
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regval = LPASS_CDC_DMA_INTF_SIX_CHANNEL; |
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break; |
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case 8: |
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regval = LPASS_CDC_DMA_INTF_EIGHT_CHANNEL; |
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break; |
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default: |
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dev_err(soc_runtime->dev, "invalid PCM config\n"); |
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return -EINVAL; |
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} |
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__lpass_get_dmactl_handle(substream, dai, &dmactl, &id); |
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if (!dmactl) |
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return -EINVAL; |
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ret = regmap_fields_write(dmactl->codec_channel, id, regval); |
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if (ret) { |
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dev_err(soc_runtime->dev, |
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"error writing to dmactl codec_channel reg field: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int lpass_cdc_dma_daiops_trigger(struct snd_pcm_substream *substream, |
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int cmd, struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); |
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struct lpaif_dmactl *dmactl; |
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int ret = 0, id; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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__lpass_platform_codec_intf_init(dai, substream); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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__lpass_get_dmactl_handle(substream, dai, &dmactl, &id); |
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if (!dmactl) |
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return -EINVAL; |
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ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_OFF); |
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if (ret) { |
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dev_err(soc_runtime->dev, |
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"error writing to dmactl codec_enable reg: %d\n", ret); |
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return ret; |
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} |
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break; |
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default: |
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ret = -EINVAL; |
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dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, cmd); |
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break; |
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} |
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return ret; |
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} |
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const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops = { |
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.startup = lpass_cdc_dma_daiops_startup, |
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.shutdown = lpass_cdc_dma_daiops_shutdown, |
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.hw_params = lpass_cdc_dma_daiops_hw_params, |
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.trigger = lpass_cdc_dma_daiops_trigger, |
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}; |
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EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cdc_dma_dai_ops); |
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MODULE_DESCRIPTION("QTi LPASS CDC DMA Driver"); |
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MODULE_LICENSE("GPL");
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