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207 lines
5.2 KiB
207 lines
5.2 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* skl.h - HD Audio skylake definitions. |
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* |
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* Copyright (C) 2015 Intel Corp |
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* Author: Jeeja KP <[email protected]> |
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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* |
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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*/ |
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#ifndef __SOUND_SOC_SKL_H |
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#define __SOUND_SOC_SKL_H |
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#include <sound/hda_register.h> |
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#include <sound/hdaudio_ext.h> |
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#include <sound/hda_codec.h> |
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#include <sound/soc.h> |
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#include "skl-ssp-clk.h" |
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#include "skl-sst-ipc.h" |
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#define SKL_SUSPEND_DELAY 2000 |
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#define SKL_MAX_ASTATE_CFG 3 |
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#define AZX_PCIREG_PGCTL 0x44 |
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#define AZX_PGCTL_LSRMD_MASK (1 << 4) |
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#define AZX_PGCTL_ADSPPGD BIT(2) |
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#define AZX_PCIREG_CGCTL 0x48 |
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#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) |
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#define AZX_CGCTL_ADSPDCGE BIT(1) |
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/* D0I3C Register fields */ |
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#define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */ |
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#define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */ |
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#define SKL_MAX_DMACTRL_CFG 18 |
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#define DMA_CLK_CONTROLS 1 |
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#define DMA_TRANSMITION_START 2 |
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#define DMA_TRANSMITION_STOP 3 |
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#define AZX_VS_EM2_DUM BIT(23) |
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#define AZX_REG_VS_EM2_L1SEN BIT(13) |
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struct skl_debug; |
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struct skl_astate_param { |
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u32 kcps; |
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u32 clk_src; |
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}; |
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struct skl_astate_config { |
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u32 count; |
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struct skl_astate_param astate_table[]; |
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}; |
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struct skl_fw_config { |
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struct skl_astate_config *astate_cfg; |
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}; |
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struct skl_dev { |
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struct hda_bus hbus; |
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struct pci_dev *pci; |
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unsigned int init_done:1; /* delayed init status */ |
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struct platform_device *dmic_dev; |
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struct platform_device *i2s_dev; |
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struct platform_device *clk_dev; |
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struct snd_soc_component *component; |
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struct snd_soc_dai_driver *dais; |
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struct nhlt_acpi_table *nhlt; /* nhlt ptr */ |
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struct list_head ppl_list; |
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struct list_head bind_list; |
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const char *fw_name; |
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char tplg_name[64]; |
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unsigned short pci_id; |
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int supend_active; |
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struct work_struct probe_work; |
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struct skl_debug *debugfs; |
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u8 nr_modules; |
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struct skl_module **modules; |
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bool use_tplg_pcm; |
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struct skl_fw_config cfg; |
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struct snd_soc_acpi_mach *mach; |
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struct device *dev; |
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struct sst_dsp *dsp; |
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/* boot */ |
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wait_queue_head_t boot_wait; |
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bool boot_complete; |
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/* module load */ |
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wait_queue_head_t mod_load_wait; |
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bool mod_load_complete; |
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bool mod_load_status; |
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/* IPC messaging */ |
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struct sst_generic_ipc ipc; |
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/* callback for miscbdge */ |
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void (*enable_miscbdcge)(struct device *dev, bool enable); |
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/* Is CGCTL.MISCBDCGE disabled */ |
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bool miscbdcg_disabled; |
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/* Populate module information */ |
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struct list_head uuid_list; |
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/* Is firmware loaded */ |
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bool fw_loaded; |
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/* first boot ? */ |
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bool is_first_boot; |
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/* multi-core */ |
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struct skl_dsp_cores cores; |
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/* library info */ |
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struct skl_lib_info lib_info[SKL_MAX_LIB]; |
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int lib_count; |
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/* Callback to update D0i3C register */ |
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void (*update_d0i3c)(struct device *dev, bool enable); |
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struct skl_d0i3_data d0i3; |
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const struct skl_dsp_ops *dsp_ops; |
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/* Callback to update dynamic clock and power gating registers */ |
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void (*clock_power_gating)(struct device *dev, bool enable); |
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}; |
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#define skl_to_bus(s) (&(s)->hbus.core) |
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#define bus_to_skl(bus) container_of(bus, struct skl_dev, hbus.core) |
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#define skl_to_hbus(s) (&(s)->hbus) |
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#define hbus_to_skl(hbus) container_of((hbus), struct skl_dev, (hbus)) |
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/* to pass dai dma data */ |
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struct skl_dma_params { |
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u32 format; |
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u8 stream_tag; |
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}; |
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struct skl_machine_pdata { |
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bool use_tplg_pcm; /* use dais and dai links from topology */ |
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}; |
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struct skl_dsp_ops { |
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int id; |
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unsigned int num_cores; |
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struct skl_dsp_loader_ops (*loader_ops)(void); |
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int (*init)(struct device *dev, void __iomem *mmio_base, |
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int irq, const char *fw_name, |
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struct skl_dsp_loader_ops loader_ops, |
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struct skl_dev **skl_sst); |
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int (*init_fw)(struct device *dev, struct skl_dev *skl); |
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void (*cleanup)(struct device *dev, struct skl_dev *skl); |
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}; |
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int skl_platform_unregister(struct device *dev); |
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int skl_platform_register(struct device *dev); |
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int skl_nhlt_update_topology_bin(struct skl_dev *skl); |
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int skl_init_dsp(struct skl_dev *skl); |
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int skl_free_dsp(struct skl_dev *skl); |
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int skl_suspend_late_dsp(struct skl_dev *skl); |
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int skl_suspend_dsp(struct skl_dev *skl); |
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int skl_resume_dsp(struct skl_dev *skl); |
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void skl_cleanup_resources(struct skl_dev *skl); |
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const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id); |
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void skl_update_d0i3c(struct device *dev, bool enable); |
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int skl_nhlt_create_sysfs(struct skl_dev *skl); |
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void skl_nhlt_remove_sysfs(struct skl_dev *skl); |
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void skl_get_clks(struct skl_dev *skl, struct skl_ssp_clk *ssp_clks); |
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struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id); |
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int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps, |
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u32 caps_size, u32 node_id); |
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struct skl_module_cfg; |
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#ifdef CONFIG_DEBUG_FS |
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struct skl_debug *skl_debugfs_init(struct skl_dev *skl); |
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void skl_debugfs_exit(struct skl_dev *skl); |
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void skl_debug_init_module(struct skl_debug *d, |
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struct snd_soc_dapm_widget *w, |
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struct skl_module_cfg *mconfig); |
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#else |
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static inline struct skl_debug *skl_debugfs_init(struct skl_dev *skl) |
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{ |
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return NULL; |
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} |
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static inline void skl_debugfs_exit(struct skl_dev *skl) |
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{} |
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static inline void skl_debug_init_module(struct skl_debug *d, |
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struct snd_soc_dapm_widget *w, |
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struct skl_module_cfg *mconfig) |
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{} |
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#endif |
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#endif /* __SOUND_SOC_SKL_H */
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