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256 lines
7.7 KiB
256 lines
7.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Skylake SST DSP Support |
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* |
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* Copyright (C) 2014-15, Intel Corporation. |
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*/ |
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#ifndef __SKL_SST_DSP_H__ |
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#define __SKL_SST_DSP_H__ |
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#include <linux/interrupt.h> |
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#include <linux/uuid.h> |
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#include <linux/firmware.h> |
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#include <sound/memalloc.h> |
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#include "skl-sst-cldma.h" |
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struct sst_dsp; |
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struct sst_dsp_device; |
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struct skl_lib_info; |
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struct skl_dev; |
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/* Intel HD Audio General DSP Registers */ |
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#define SKL_ADSP_GEN_BASE 0x0 |
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#define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) |
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#define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) |
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#define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) |
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#define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) |
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#define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) |
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/* Intel HD Audio Inter-Processor Communication Registers */ |
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#define SKL_ADSP_IPC_BASE 0x40 |
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#define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) |
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#define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) |
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#define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) |
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#define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) |
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#define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) |
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/* HIPCI */ |
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#define SKL_ADSP_REG_HIPCI_BUSY BIT(31) |
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/* HIPCIE */ |
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#define SKL_ADSP_REG_HIPCIE_DONE BIT(30) |
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/* HIPCCTL */ |
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#define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) |
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#define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) |
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/* HIPCT */ |
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#define SKL_ADSP_REG_HIPCT_BUSY BIT(31) |
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/* FW base IDs */ |
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#define SKL_INSTANCE_ID 0 |
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#define SKL_BASE_FW_MODULE_ID 0 |
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/* Intel HD Audio SRAM Window 1 */ |
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#define SKL_ADSP_SRAM1_BASE 0xA000 |
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#define SKL_ADSP_MMIO_LEN 0x10000 |
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#define SKL_ADSP_W0_STAT_SZ 0x1000 |
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#define SKL_ADSP_W0_UP_SZ 0x1000 |
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#define SKL_ADSP_W1_SZ 0x1000 |
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#define SKL_FW_STS_MASK 0xf |
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#define SKL_FW_INIT 0x1 |
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#define SKL_FW_RFW_START 0xf |
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#define BXT_FW_ROM_INIT_RETRY 3 |
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#define BXT_INIT_TIMEOUT 300 |
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#define SKL_ADSPIC_IPC 1 |
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#define SKL_ADSPIS_IPC 1 |
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/* Core ID of core0 */ |
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#define SKL_DSP_CORE0_ID 0 |
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/* Mask for a given core index, c = 0.. number of supported cores - 1 */ |
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#define SKL_DSP_CORE_MASK(c) BIT(c) |
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/* |
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* Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately |
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* since Core0 is primary core and it is used often |
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*/ |
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#define SKL_DSP_CORE0_MASK BIT(0) |
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/* |
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* Mask for a given number of cores |
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* nc = number of supported cores |
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*/ |
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#define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0) |
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/* ADSPCS - Audio DSP Control & Status */ |
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/* |
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* Core Reset - asserted high |
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* CRST Mask for a given core mask pattern, cm |
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*/ |
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#define SKL_ADSPCS_CRST_SHIFT 0 |
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#define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT) |
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/* |
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* Core run/stall - when set to '1' core is stalled |
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* CSTALL Mask for a given core mask pattern, cm |
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*/ |
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#define SKL_ADSPCS_CSTALL_SHIFT 8 |
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#define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT) |
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/* |
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* Set Power Active - when set to '1' turn cores on |
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* SPA Mask for a given core mask pattern, cm |
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*/ |
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#define SKL_ADSPCS_SPA_SHIFT 16 |
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#define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT) |
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/* |
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* Current Power Active - power status of cores, set by hardware |
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* CPA Mask for a given core mask pattern, cm |
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*/ |
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#define SKL_ADSPCS_CPA_SHIFT 24 |
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#define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT) |
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/* DSP Core state */ |
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enum skl_dsp_states { |
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SKL_DSP_RUNNING = 1, |
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/* Running in D0i3 state; can be in streaming or non-streaming D0i3 */ |
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SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/ |
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SKL_DSP_RESET, |
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}; |
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/* D0i3 substates */ |
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enum skl_dsp_d0i3_states { |
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SKL_DSP_D0I3_NONE = -1, /* No D0i3 */ |
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SKL_DSP_D0I3_NON_STREAMING = 0, |
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SKL_DSP_D0I3_STREAMING = 1, |
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}; |
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struct skl_dsp_fw_ops { |
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int (*load_fw)(struct sst_dsp *ctx); |
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/* FW module parser/loader */ |
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int (*load_library)(struct sst_dsp *ctx, |
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struct skl_lib_info *linfo, int lib_count); |
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int (*parse_fw)(struct sst_dsp *ctx); |
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int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id); |
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int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id); |
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int (*set_state_D0i3)(struct sst_dsp *ctx); |
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int (*set_state_D0i0)(struct sst_dsp *ctx); |
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unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); |
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int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name); |
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int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); |
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}; |
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struct skl_dsp_loader_ops { |
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int stream_tag; |
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int (*alloc_dma_buf)(struct device *dev, |
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struct snd_dma_buffer *dmab, size_t size); |
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int (*free_dma_buf)(struct device *dev, |
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struct snd_dma_buffer *dmab); |
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int (*prepare)(struct device *dev, unsigned int format, |
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unsigned int byte_size, |
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struct snd_dma_buffer *bufp); |
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int (*trigger)(struct device *dev, bool start, int stream_tag); |
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int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab, |
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int stream_tag); |
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}; |
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#define MAX_INSTANCE_BUFF 2 |
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struct uuid_module { |
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guid_t uuid; |
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int id; |
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int is_loadable; |
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int max_instance; |
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u64 pvt_id[MAX_INSTANCE_BUFF]; |
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int *instance_id; |
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struct list_head list; |
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}; |
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struct skl_load_module_info { |
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u16 mod_id; |
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const struct firmware *fw; |
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}; |
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struct skl_module_table { |
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struct skl_load_module_info *mod_info; |
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unsigned int usage_cnt; |
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struct list_head list; |
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}; |
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void skl_cldma_process_intr(struct sst_dsp *ctx); |
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void skl_cldma_int_disable(struct sst_dsp *ctx); |
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int skl_cldma_prepare(struct sst_dsp *ctx); |
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int skl_cldma_wait_interruptible(struct sst_dsp *ctx); |
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void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); |
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struct sst_dsp *skl_dsp_ctx_init(struct device *dev, |
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struct sst_dsp_device *sst_dev, int irq); |
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int skl_dsp_acquire_irq(struct sst_dsp *sst); |
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bool is_skl_dsp_running(struct sst_dsp *ctx); |
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unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx); |
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void skl_dsp_init_core_state(struct sst_dsp *ctx); |
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int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); |
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int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); |
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int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask); |
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int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask); |
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int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx, |
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unsigned int core_mask); |
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int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask); |
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irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); |
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int skl_dsp_wake(struct sst_dsp *ctx); |
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int skl_dsp_sleep(struct sst_dsp *ctx); |
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void skl_dsp_free(struct sst_dsp *dsp); |
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int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id); |
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int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id); |
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int skl_dsp_boot(struct sst_dsp *ctx); |
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int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, |
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const char *fw_name, struct skl_dsp_loader_ops dsp_ops, |
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struct skl_dev **dsp); |
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int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, |
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const char *fw_name, struct skl_dsp_loader_ops dsp_ops, |
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struct skl_dev **dsp); |
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int skl_sst_init_fw(struct device *dev, struct skl_dev *skl); |
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int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl); |
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void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); |
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void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); |
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int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, |
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unsigned int offset, int index); |
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int skl_get_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int instance_id); |
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int skl_put_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int *pvt_id); |
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int skl_get_pvt_instance_id_map(struct skl_dev *skl, |
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int module_id, int instance_id); |
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void skl_freeup_uuid_list(struct skl_dev *skl); |
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int skl_dsp_strip_extended_manifest(struct firmware *fw); |
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void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data); |
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int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name, |
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struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp, |
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struct sst_dsp_device *skl_dev); |
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int skl_prepare_lib_load(struct skl_dev *skl, struct skl_lib_info *linfo, |
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struct firmware *stripped_fw, |
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unsigned int hdr_offset, int index); |
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void skl_release_library(struct skl_lib_info *linfo, int lib_count); |
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#endif /*__SKL_SST_DSP_H__*/
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