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442 lines
11 KiB
442 lines
11 KiB
/* |
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* pata_sil680.c - SIL680 PATA for new ATA layer |
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* (C) 2005 Red Hat Inc |
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* |
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* based upon |
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* |
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* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 |
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* |
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* Copyright (C) 2001-2002 Andre Hedrick <[email protected]> |
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* Copyright (C) 2003 Red Hat <[email protected]> |
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* |
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* May be copied or modified under the terms of the GNU General Public License |
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* |
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* Documentation publicly available. |
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* |
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* If you have strange problems with nVidia chipset systems please |
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* see the SI support documentation and update your system BIOS |
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* if necessary |
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* |
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* TODO |
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* If we know all our devices are LBA28 (or LBA28 sized) we could use |
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* the command fifo mode. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#define DRV_NAME "pata_sil680" |
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#define DRV_VERSION "0.4.9" |
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#define SIL680_MMIO_BAR 5 |
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/** |
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* sil680_selreg - return register base |
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* @ap: ATA interface |
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* @r: config offset |
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* |
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* Turn a config register offset into the right address in PCI space |
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* to access the control register in question. |
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* |
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* Thankfully this is a configuration operation so isn't performance |
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* criticial. |
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*/ |
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static unsigned long sil680_selreg(struct ata_port *ap, int r) |
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{ |
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unsigned long base = 0xA0 + r; |
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base += (ap->port_no << 4); |
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return base; |
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} |
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/** |
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* sil680_seldev - return register base |
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* @ap: ATA interface |
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* @adev: ATA device |
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* @r: config offset |
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* |
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* Turn a config register offset into the right address in PCI space |
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* to access the control register in question including accounting for |
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* the unit shift. |
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*/ |
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static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) |
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{ |
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unsigned long base = 0xA0 + r; |
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base += (ap->port_no << 4); |
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base |= adev->devno ? 2 : 0; |
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return base; |
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} |
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/** |
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* sil680_cable_detect - cable detection |
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* @ap: ATA port |
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* |
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* Perform cable detection. The SIL680 stores this in PCI config |
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* space for us. |
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*/ |
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static int sil680_cable_detect(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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unsigned long addr = sil680_selreg(ap, 0); |
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u8 ata66; |
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pci_read_config_byte(pdev, addr, &ata66); |
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if (ata66 & 1) |
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return ATA_CBL_PATA80; |
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else |
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return ATA_CBL_PATA40; |
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} |
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/** |
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* sil680_set_piomode - set PIO mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* |
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* Program the SIL680 registers for PIO mode. Note that the task speed |
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* registers are shared between the devices so we must pick the lowest |
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* mode for command work. |
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*/ |
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static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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static const u16 speed_p[5] = { |
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0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 |
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}; |
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static const u16 speed_t[5] = { |
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0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 |
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}; |
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unsigned long tfaddr = sil680_selreg(ap, 0x02); |
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unsigned long addr = sil680_seldev(ap, adev, 0x04); |
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unsigned long addr_mask = 0x80 + 4 * ap->port_no; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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int pio = adev->pio_mode - XFER_PIO_0; |
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int lowest_pio = pio; |
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int port_shift = 4 * adev->devno; |
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u16 reg; |
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u8 mode; |
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struct ata_device *pair = ata_dev_pair(adev); |
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if (pair != NULL && adev->pio_mode > pair->pio_mode) |
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lowest_pio = pair->pio_mode - XFER_PIO_0; |
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pci_write_config_word(pdev, addr, speed_p[pio]); |
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pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); |
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pci_read_config_word(pdev, tfaddr-2, ®); |
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pci_read_config_byte(pdev, addr_mask, &mode); |
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reg &= ~0x0200; /* Clear IORDY */ |
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mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ |
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if (ata_pio_need_iordy(adev)) { |
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reg |= 0x0200; /* Enable IORDY */ |
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mode |= 1 << port_shift; |
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} |
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pci_write_config_word(pdev, tfaddr-2, reg); |
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pci_write_config_byte(pdev, addr_mask, mode); |
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} |
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/** |
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* sil680_set_dmamode - set DMA mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* |
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* Program the MWDMA/UDMA modes for the sil680 chipset. |
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* |
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* The MWDMA mode values are pulled from a lookup table |
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* while the chipset uses mode number for UDMA. |
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*/ |
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static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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static const u8 ultra_table[2][7] = { |
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{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ |
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{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ |
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}; |
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static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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unsigned long ma = sil680_seldev(ap, adev, 0x08); |
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unsigned long ua = sil680_seldev(ap, adev, 0x0C); |
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unsigned long addr_mask = 0x80 + 4 * ap->port_no; |
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int port_shift = adev->devno * 4; |
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u8 scsc, mode; |
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u16 multi, ultra; |
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pci_read_config_byte(pdev, 0x8A, &scsc); |
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pci_read_config_byte(pdev, addr_mask, &mode); |
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pci_read_config_word(pdev, ma, &multi); |
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pci_read_config_word(pdev, ua, &ultra); |
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/* Mask timing bits */ |
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ultra &= ~0x3F; |
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mode &= ~(0x03 << port_shift); |
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/* Extract scsc */ |
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scsc = (scsc & 0x30) ? 1 : 0; |
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if (adev->dma_mode >= XFER_UDMA_0) { |
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multi = 0x10C1; |
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ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; |
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mode |= (0x03 << port_shift); |
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} else { |
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multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; |
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mode |= (0x02 << port_shift); |
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} |
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pci_write_config_byte(pdev, addr_mask, mode); |
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pci_write_config_word(pdev, ma, multi); |
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pci_write_config_word(pdev, ua, ultra); |
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} |
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/** |
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* sil680_sff_exec_command - issue ATA command to host controller |
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* @ap: port to which command is being issued |
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* @tf: ATA taskfile register set |
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* |
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* Issues ATA command, with proper synchronization with interrupt |
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* handler / other threads. Use our MMIO space for PCI posting to avoid |
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* a hideously slow cycle all the way to the device. |
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* |
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* LOCKING: |
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* spin_lock_irqsave(host lock) |
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*/ |
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static void sil680_sff_exec_command(struct ata_port *ap, |
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const struct ata_taskfile *tf) |
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{ |
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iowrite8(tf->command, ap->ioaddr.command_addr); |
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ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
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} |
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static bool sil680_sff_irq_check(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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unsigned long addr = sil680_selreg(ap, 1); |
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u8 val; |
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pci_read_config_byte(pdev, addr, &val); |
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return val & 0x08; |
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} |
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static struct scsi_host_template sil680_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations sil680_port_ops = { |
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.inherits = &ata_bmdma32_port_ops, |
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.sff_exec_command = sil680_sff_exec_command, |
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.sff_irq_check = sil680_sff_irq_check, |
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.cable_detect = sil680_cable_detect, |
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.set_piomode = sil680_set_piomode, |
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.set_dmamode = sil680_set_dmamode, |
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}; |
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/** |
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* sil680_init_chip - chip setup |
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* @pdev: PCI device |
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* @try_mmio: Indicates to caller whether MMIO should be attempted |
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* |
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* Perform all the chip setup which must be done both when the device |
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* is powered up on boot and when we resume in case we resumed from RAM. |
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* Returns the final clock settings. |
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*/ |
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static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio) |
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{ |
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u8 tmpbyte = 0; |
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/* FIXME: double check */ |
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, |
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pdev->revision ? 1 : 255); |
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pci_write_config_byte(pdev, 0x80, 0x00); |
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pci_write_config_byte(pdev, 0x84, 0x00); |
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pci_read_config_byte(pdev, 0x8A, &tmpbyte); |
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dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
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tmpbyte & 1, tmpbyte & 0x30); |
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*try_mmio = 0; |
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#ifdef CONFIG_PPC |
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if (machine_is(cell)) |
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*try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5); |
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#endif |
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switch (tmpbyte & 0x30) { |
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case 0x00: |
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/* 133 clock attempt to force it on */ |
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pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); |
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break; |
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case 0x30: |
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/* if clocking is disabled */ |
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/* 133 clock attempt to force it on */ |
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pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); |
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break; |
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case 0x10: |
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/* 133 already */ |
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break; |
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case 0x20: |
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/* BIOS set PCI x2 clocking */ |
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break; |
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} |
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pci_read_config_byte(pdev, 0x8A, &tmpbyte); |
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dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
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tmpbyte & 1, tmpbyte & 0x30); |
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pci_write_config_byte(pdev, 0xA1, 0x72); |
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pci_write_config_word(pdev, 0xA2, 0x328A); |
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pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); |
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pci_write_config_dword(pdev, 0xA8, 0x43924392); |
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pci_write_config_dword(pdev, 0xAC, 0x40094009); |
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pci_write_config_byte(pdev, 0xB1, 0x72); |
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pci_write_config_word(pdev, 0xB2, 0x328A); |
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pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); |
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pci_write_config_dword(pdev, 0xB8, 0x43924392); |
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pci_write_config_dword(pdev, 0xBC, 0x40094009); |
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switch (tmpbyte & 0x30) { |
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case 0x00: |
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dev_info(&pdev->dev, "sil680: 100MHz clock.\n"); |
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break; |
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case 0x10: |
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dev_info(&pdev->dev, "sil680: 133MHz clock.\n"); |
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break; |
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case 0x20: |
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dev_info(&pdev->dev, "sil680: Using PCI clock.\n"); |
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break; |
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/* This last case is _NOT_ ok */ |
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case 0x30: |
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dev_err(&pdev->dev, "sil680: Clock disabled ?\n"); |
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} |
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return tmpbyte & 0x30; |
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} |
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static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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static const struct ata_port_info info = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &sil680_port_ops |
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}; |
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static const struct ata_port_info info_slow = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &sil680_port_ops |
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}; |
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const struct ata_port_info *ppi[] = { &info, NULL }; |
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struct ata_host *host; |
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void __iomem *mmio_base; |
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int rc, try_mmio; |
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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switch (sil680_init_chip(pdev, &try_mmio)) { |
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case 0: |
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ppi[0] = &info_slow; |
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break; |
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case 0x30: |
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return -ENODEV; |
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} |
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if (!try_mmio) |
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goto use_ioports; |
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/* Try to acquire MMIO resources and fallback to PIO if |
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* that fails |
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*/ |
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rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); |
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if (rc) |
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goto use_ioports; |
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/* Allocate host and set it up */ |
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); |
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if (!host) |
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return -ENOMEM; |
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host->iomap = pcim_iomap_table(pdev); |
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/* Setup DMA masks */ |
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rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
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if (rc) |
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return rc; |
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pci_set_master(pdev); |
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/* Get MMIO base and initialize port addresses */ |
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mmio_base = host->iomap[SIL680_MMIO_BAR]; |
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host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; |
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host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; |
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host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; |
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host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; |
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ata_sff_std_ports(&host->ports[0]->ioaddr); |
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host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; |
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host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; |
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host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; |
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host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; |
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ata_sff_std_ports(&host->ports[1]->ioaddr); |
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/* Register & activate */ |
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return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
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IRQF_SHARED, &sil680_sht); |
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use_ioports: |
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return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int sil680_reinit_one(struct pci_dev *pdev) |
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{ |
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struct ata_host *host = pci_get_drvdata(pdev); |
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int try_mmio, rc; |
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rc = ata_pci_device_do_resume(pdev); |
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if (rc) |
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return rc; |
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sil680_init_chip(pdev, &try_mmio); |
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ata_host_resume(host); |
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return 0; |
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} |
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#endif |
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static const struct pci_device_id sil680[] = { |
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{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, |
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{ }, |
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}; |
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static struct pci_driver sil680_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = sil680, |
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.probe = sil680_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = sil680_reinit_one, |
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#endif |
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}; |
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module_pci_driver(sil680_pci_driver); |
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MODULE_AUTHOR("Alan Cox"); |
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MODULE_DESCRIPTION("low-level driver for SI680 PATA"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, sil680); |
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MODULE_VERSION(DRV_VERSION);
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