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314 lines
8.8 KiB
314 lines
8.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ixp4xx PATA/Compact Flash driver |
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* Copyright (C) 2006-07 Tower Technologies |
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* Author: Alessandro Zummo <[email protected]> |
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* |
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* An ATA driver to handle a Compact Flash connected |
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* to the ixp4xx expansion bus in TrueIDE mode. The CF |
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* must have it chip selects connected to two CS lines |
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* on the ixp4xx. In the irq is not available, you might |
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* want to modify both this driver and libata to run in |
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* polling mode. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/libata.h> |
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#include <linux/irq.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <scsi/scsi_host.h> |
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#define DRV_NAME "pata_ixp4xx_cf" |
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#define DRV_VERSION "1.0" |
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struct ixp4xx_pata { |
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struct ata_host *host; |
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struct regmap *rmap; |
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u32 cmd_csreg; |
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void __iomem *cmd; |
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void __iomem *ctl; |
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}; |
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#define IXP4XX_EXP_TIMING_STRIDE 0x04 |
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/* The timings for the chipselect is in bits 29..16 */ |
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#define IXP4XX_EXP_T1_T5_MASK GENMASK(29, 16) |
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#define IXP4XX_EXP_PIO_0_8 0x0a470000 |
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#define IXP4XX_EXP_PIO_1_8 0x06430000 |
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#define IXP4XX_EXP_PIO_2_8 0x02410000 |
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#define IXP4XX_EXP_PIO_3_8 0x00820000 |
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#define IXP4XX_EXP_PIO_4_8 0x00400000 |
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#define IXP4XX_EXP_PIO_0_16 0x29640000 |
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#define IXP4XX_EXP_PIO_1_16 0x05030000 |
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#define IXP4XX_EXP_PIO_2_16 0x00b20000 |
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#define IXP4XX_EXP_PIO_3_16 0x00820000 |
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#define IXP4XX_EXP_PIO_4_16 0x00400000 |
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#define IXP4XX_EXP_BW_MASK (BIT(6)|BIT(0)) |
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#define IXP4XX_EXP_BYTE_RD16 BIT(6) /* Byte reads on half-word devices */ |
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#define IXP4XX_EXP_BYTE_EN BIT(0) /* Use 8bit data bus if set */ |
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static void ixp4xx_set_8bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode) |
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{ |
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switch (pio_mode) { |
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case XFER_PIO_0: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_8); |
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break; |
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case XFER_PIO_1: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_8); |
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break; |
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case XFER_PIO_2: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_8); |
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break; |
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case XFER_PIO_3: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_8); |
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break; |
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case XFER_PIO_4: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_8); |
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break; |
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default: |
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break; |
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} |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16|IXP4XX_EXP_BYTE_EN); |
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} |
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static void ixp4xx_set_16bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode) |
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{ |
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switch (pio_mode){ |
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case XFER_PIO_0: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_16); |
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break; |
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case XFER_PIO_1: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_16); |
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break; |
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case XFER_PIO_2: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_16); |
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break; |
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case XFER_PIO_3: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_16); |
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break; |
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case XFER_PIO_4: |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_16); |
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break; |
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default: |
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break; |
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} |
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regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg, |
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IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16); |
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} |
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/* This sets up the timing on the chipselect CMD accordingly */ |
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static void ixp4xx_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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struct ixp4xx_pata *ixpp = ap->host->private_data; |
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ata_dev_info(adev, "configured for PIO%d 8bit\n", |
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adev->pio_mode - XFER_PIO_0); |
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ixp4xx_set_8bit_timing(ixpp, adev->pio_mode); |
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} |
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static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc, |
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unsigned char *buf, unsigned int buflen, int rw) |
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{ |
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unsigned int i; |
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unsigned int words = buflen >> 1; |
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u16 *buf16 = (u16 *) buf; |
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struct ata_device *adev = qc->dev; |
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struct ata_port *ap = qc->dev->link->ap; |
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void __iomem *mmio = ap->ioaddr.data_addr; |
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struct ixp4xx_pata *ixpp = ap->host->private_data; |
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unsigned long flags; |
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ata_dev_dbg(adev, "%s %d bytes\n", (rw == READ) ? "READ" : "WRITE", |
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buflen); |
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spin_lock_irqsave(ap->lock, flags); |
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/* set the expansion bus in 16bit mode and restore |
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* 8 bit mode after the transaction. |
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*/ |
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ixp4xx_set_16bit_timing(ixpp, adev->pio_mode); |
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udelay(5); |
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/* Transfer multiple of 2 bytes */ |
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if (rw == READ) |
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for (i = 0; i < words; i++) |
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buf16[i] = readw(mmio); |
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else |
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for (i = 0; i < words; i++) |
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writew(buf16[i], mmio); |
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/* Transfer trailing 1 byte, if any. */ |
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if (unlikely(buflen & 0x01)) { |
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u16 align_buf[1] = { 0 }; |
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unsigned char *trailing_buf = buf + buflen - 1; |
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if (rw == READ) { |
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align_buf[0] = readw(mmio); |
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memcpy(trailing_buf, align_buf, 1); |
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} else { |
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memcpy(align_buf, trailing_buf, 1); |
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writew(align_buf[0], mmio); |
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} |
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words++; |
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} |
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ixp4xx_set_8bit_timing(ixpp, adev->pio_mode); |
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udelay(5); |
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spin_unlock_irqrestore(ap->lock, flags); |
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return words << 1; |
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} |
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static struct scsi_host_template ixp4xx_sht = { |
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ATA_PIO_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations ixp4xx_port_ops = { |
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.inherits = &ata_sff_port_ops, |
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.sff_data_xfer = ixp4xx_mmio_data_xfer, |
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.cable_detect = ata_cable_40wire, |
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.set_piomode = ixp4xx_set_piomode, |
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}; |
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static struct ata_port_info ixp4xx_port_info = { |
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.flags = ATA_FLAG_NO_ATAPI, |
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.pio_mask = ATA_PIO4, |
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.port_ops = &ixp4xx_port_ops, |
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}; |
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static void ixp4xx_setup_port(struct ata_port *ap, |
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struct ixp4xx_pata *ixpp, |
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unsigned long raw_cmd, unsigned long raw_ctl) |
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{ |
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struct ata_ioports *ioaddr = &ap->ioaddr; |
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raw_ctl += 0x06; |
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ioaddr->cmd_addr = ixpp->cmd; |
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ioaddr->altstatus_addr = ixpp->ctl + 0x06; |
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ioaddr->ctl_addr = ixpp->ctl + 0x06; |
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ata_sff_std_ports(ioaddr); |
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if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { |
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/* adjust the addresses to handle the address swizzling of the |
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* ixp4xx in little endian mode. |
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*/ |
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*(unsigned long *)&ioaddr->data_addr ^= 0x02; |
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*(unsigned long *)&ioaddr->cmd_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->altstatus_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->ctl_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->error_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->feature_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->nsect_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->lbal_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->lbam_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->lbah_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->device_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->status_addr ^= 0x03; |
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*(unsigned long *)&ioaddr->command_addr ^= 0x03; |
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raw_cmd ^= 0x03; |
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raw_ctl ^= 0x03; |
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} |
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ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", raw_cmd, raw_ctl); |
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} |
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static int ixp4xx_pata_probe(struct platform_device *pdev) |
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{ |
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struct resource *cmd, *ctl; |
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struct ata_port_info pi = ixp4xx_port_info; |
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const struct ata_port_info *ppi[] = { &pi, NULL }; |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct ixp4xx_pata *ixpp; |
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u32 csindex; |
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int ret; |
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int irq; |
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cmd = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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ctl = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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if (!cmd || !ctl) |
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return -EINVAL; |
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ixpp = devm_kzalloc(dev, sizeof(*ixpp), GFP_KERNEL); |
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if (!ixpp) |
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return -ENOMEM; |
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ixpp->rmap = syscon_node_to_regmap(np->parent); |
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if (IS_ERR(ixpp->rmap)) |
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return dev_err_probe(dev, PTR_ERR(ixpp->rmap), "no regmap\n"); |
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/* Inspect our address to figure out what chipselect the CMD is on */ |
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ret = of_property_read_u32_index(np, "reg", 0, &csindex); |
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if (ret) |
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return dev_err_probe(dev, ret, "can't inspect CMD address\n"); |
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dev_info(dev, "using CS%d for PIO timing configuration\n", csindex); |
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ixpp->cmd_csreg = csindex * IXP4XX_EXP_TIMING_STRIDE; |
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ixpp->host = ata_host_alloc_pinfo(dev, ppi, 1); |
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if (!ixpp->host) |
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return -ENOMEM; |
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ixpp->host->private_data = ixpp; |
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ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); |
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if (ret) |
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return ret; |
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ixpp->cmd = devm_ioremap_resource(dev, cmd); |
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ixpp->ctl = devm_ioremap_resource(dev, ctl); |
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if (IS_ERR(ixpp->cmd) || IS_ERR(ixpp->ctl)) |
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return -ENOMEM; |
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irq = platform_get_irq(pdev, 0); |
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if (irq > 0) |
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irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
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else if (irq < 0) |
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return irq; |
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else |
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return -EINVAL; |
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/* Just one port to set up */ |
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ixp4xx_setup_port(ixpp->host->ports[0], ixpp, cmd->start, ctl->start); |
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ata_print_version_once(dev, DRV_VERSION); |
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return ata_host_activate(ixpp->host, irq, ata_sff_interrupt, 0, &ixp4xx_sht); |
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} |
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static const struct of_device_id ixp4xx_pata_of_match[] = { |
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{ .compatible = "intel,ixp4xx-compact-flash", }, |
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{ /* sentinel */ } |
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}; |
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static struct platform_driver ixp4xx_pata_platform_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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.of_match_table = ixp4xx_pata_of_match, |
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}, |
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.probe = ixp4xx_pata_probe, |
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.remove = ata_platform_remove_one, |
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}; |
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module_platform_driver(ixp4xx_pata_platform_driver); |
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MODULE_AUTHOR("Alessandro Zummo <[email protected]>"); |
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MODULE_DESCRIPTION("low-level driver for ixp4xx Compact Flash PATA"); |
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MODULE_LICENSE("GPL"); |
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MODULE_VERSION(DRV_VERSION); |
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MODULE_ALIAS("platform:" DRV_NAME);
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