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594 lines
15 KiB
594 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Broadcom SATA3 AHCI Controller Driver |
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* |
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* Copyright © 2009-2015 Broadcom Corporation |
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*/ |
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|
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#include <linux/ahci_platform.h> |
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#include <linux/compiler.h> |
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#include <linux/device.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/libata.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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#include <linux/string.h> |
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#include "ahci.h" |
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|
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#define DRV_NAME "brcm-ahci" |
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|
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#define SATA_TOP_CTRL_VERSION 0x0 |
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#define SATA_TOP_CTRL_BUS_CTRL 0x4 |
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#define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */ |
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#define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */ |
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#define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */ |
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#define PIODATA_ENDIAN_SHIFT 6 |
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#define ENDIAN_SWAP_NONE 0 |
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#define ENDIAN_SWAP_FULL 2 |
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#define SATA_TOP_CTRL_TP_CTRL 0x8 |
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#define SATA_TOP_CTRL_PHY_CTRL 0xc |
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#define SATA_TOP_CTRL_PHY_CTRL_1 0x0 |
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#define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14) |
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#define SATA_TOP_CTRL_PHY_CTRL_2 0x4 |
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#define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0) |
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#define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1) |
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#define SATA_TOP_CTRL_2_SW_RST_RX BIT(2) |
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#define SATA_TOP_CTRL_2_SW_RST_TX BIT(3) |
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#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14) |
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#define SATA_TOP_CTRL_PHY_OFFS 0x8 |
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#define SATA_TOP_MAX_PHYS 2 |
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#define SATA_FIRST_PORT_CTRL 0x700 |
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#define SATA_NEXT_PORT_CTRL_OFFSET 0x80 |
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#define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18) |
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/* On big-endian MIPS, buses are reversed to big endian, so switch them back */ |
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#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) |
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#define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */ |
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#define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */ |
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#else |
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#define DATA_ENDIAN 0 |
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#define MMIO_ENDIAN 0 |
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#endif |
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#define BUS_CTRL_ENDIAN_CONF \ |
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((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \ |
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(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \ |
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(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT)) |
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#define BUS_CTRL_ENDIAN_NSP_CONF \ |
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(0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT) |
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#define BUS_CTRL_ENDIAN_CONF_MASK \ |
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(0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT | \ |
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0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT) |
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enum brcm_ahci_version { |
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BRCM_SATA_BCM7425 = 1, |
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BRCM_SATA_BCM7445, |
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BRCM_SATA_NSP, |
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BRCM_SATA_BCM7216, |
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}; |
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enum brcm_ahci_quirks { |
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BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0), |
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}; |
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struct brcm_ahci_priv { |
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struct device *dev; |
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void __iomem *top_ctrl; |
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u32 port_mask; |
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u32 quirks; |
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enum brcm_ahci_version version; |
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struct reset_control *rcdev_rescal; |
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struct reset_control *rcdev_ahci; |
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}; |
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static inline u32 brcm_sata_readreg(void __iomem *addr) |
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{ |
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/* |
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* MIPS endianness is configured by boot strap, which also reverses all |
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* bus endianness (i.e., big-endian CPU + big endian bus ==> native |
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* endian I/O). |
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* |
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* Other architectures (e.g., ARM) either do not support big endian, or |
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* else leave I/O in little endian mode. |
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*/ |
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
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return __raw_readl(addr); |
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else |
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return readl_relaxed(addr); |
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} |
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static inline void brcm_sata_writereg(u32 val, void __iomem *addr) |
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{ |
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/* See brcm_sata_readreg() comments */ |
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
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__raw_writel(val, addr); |
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else |
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writel_relaxed(val, addr); |
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} |
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static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv) |
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{ |
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struct brcm_ahci_priv *priv = hpriv->plat_data; |
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u32 port_ctrl, host_caps; |
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int i; |
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/* Enable support for ALPM */ |
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host_caps = readl(hpriv->mmio + HOST_CAP); |
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if (!(host_caps & HOST_CAP_ALPM)) |
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hpriv->flags |= AHCI_HFLAG_YES_ALPM; |
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|
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/* |
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* Adjust timeout to allow PLL sufficient time to lock while waking |
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* up from slumber mode. |
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*/ |
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for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL; |
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i < SATA_TOP_MAX_PHYS; |
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i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) { |
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if (priv->port_mask & BIT(i)) |
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writel(0xff1003fc, |
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hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl)); |
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} |
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} |
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static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port) |
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{ |
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void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + |
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(port * SATA_TOP_CTRL_PHY_OFFS); |
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void __iomem *p; |
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u32 reg; |
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if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) |
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return; |
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/* clear PHY_DEFAULT_POWER_STATE */ |
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p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; |
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reg = brcm_sata_readreg(p); |
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reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; |
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brcm_sata_writereg(reg, p); |
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|
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/* reset the PHY digital logic */ |
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p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; |
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reg = brcm_sata_readreg(p); |
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reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | |
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SATA_TOP_CTRL_2_SW_RST_RX); |
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reg |= SATA_TOP_CTRL_2_SW_RST_TX; |
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brcm_sata_writereg(reg, p); |
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reg = brcm_sata_readreg(p); |
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reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; |
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brcm_sata_writereg(reg, p); |
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reg = brcm_sata_readreg(p); |
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reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; |
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brcm_sata_writereg(reg, p); |
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(void)brcm_sata_readreg(p); |
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} |
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static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port) |
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{ |
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void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + |
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(port * SATA_TOP_CTRL_PHY_OFFS); |
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void __iomem *p; |
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u32 reg; |
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if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) |
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return; |
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/* power-off the PHY digital logic */ |
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p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; |
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reg = brcm_sata_readreg(p); |
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reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | |
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SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX | |
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SATA_TOP_CTRL_2_PHY_GLOBAL_RESET); |
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brcm_sata_writereg(reg, p); |
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/* set PHY_DEFAULT_POWER_STATE */ |
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p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; |
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reg = brcm_sata_readreg(p); |
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reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; |
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brcm_sata_writereg(reg, p); |
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} |
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static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv) |
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{ |
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int i; |
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for (i = 0; i < SATA_TOP_MAX_PHYS; i++) |
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if (priv->port_mask & BIT(i)) |
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brcm_sata_phy_enable(priv, i); |
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} |
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static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv) |
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{ |
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int i; |
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for (i = 0; i < SATA_TOP_MAX_PHYS; i++) |
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if (priv->port_mask & BIT(i)) |
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brcm_sata_phy_disable(priv, i); |
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} |
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static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv, |
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struct brcm_ahci_priv *priv) |
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{ |
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u32 impl; |
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impl = readl(hpriv->mmio + HOST_PORTS_IMPL); |
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if (fls(impl) > SATA_TOP_MAX_PHYS) |
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dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n", |
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impl); |
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else if (!impl) |
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dev_info(priv->dev, "no ports found\n"); |
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return impl; |
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} |
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static void brcm_sata_init(struct brcm_ahci_priv *priv) |
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{ |
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void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL; |
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u32 data; |
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/* Configure endianness */ |
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data = brcm_sata_readreg(ctrl); |
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data &= ~BUS_CTRL_ENDIAN_CONF_MASK; |
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if (priv->version == BRCM_SATA_NSP) |
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data |= BUS_CTRL_ENDIAN_NSP_CONF; |
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else |
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data |= BUS_CTRL_ENDIAN_CONF; |
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brcm_sata_writereg(data, ctrl); |
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} |
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static unsigned int brcm_ahci_read_id(struct ata_device *dev, |
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struct ata_taskfile *tf, __le16 *id) |
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{ |
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struct ata_port *ap = dev->link->ap; |
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struct ata_host *host = ap->host; |
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struct ahci_host_priv *hpriv = host->private_data; |
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struct brcm_ahci_priv *priv = hpriv->plat_data; |
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void __iomem *mmio = hpriv->mmio; |
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unsigned int err_mask; |
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unsigned long flags; |
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int i, rc; |
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u32 ctl; |
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/* Try to read the device ID and, if this fails, proceed with the |
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* recovery sequence below |
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*/ |
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err_mask = ata_do_dev_read_id(dev, tf, id); |
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if (likely(!err_mask)) |
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return err_mask; |
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/* Disable host interrupts */ |
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spin_lock_irqsave(&host->lock, flags); |
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ctl = readl(mmio + HOST_CTL); |
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ctl &= ~HOST_IRQ_EN; |
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writel(ctl, mmio + HOST_CTL); |
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readl(mmio + HOST_CTL); /* flush */ |
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spin_unlock_irqrestore(&host->lock, flags); |
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/* Perform the SATA PHY reset sequence */ |
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brcm_sata_phy_disable(priv, ap->port_no); |
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/* Reset the SATA clock */ |
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ahci_platform_disable_clks(hpriv); |
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msleep(10); |
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ahci_platform_enable_clks(hpriv); |
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msleep(10); |
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/* Bring the PHY back on */ |
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brcm_sata_phy_enable(priv, ap->port_no); |
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/* Re-initialize and calibrate the PHY */ |
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for (i = 0; i < hpriv->nports; i++) { |
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rc = phy_init(hpriv->phys[i]); |
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if (rc) |
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goto disable_phys; |
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rc = phy_calibrate(hpriv->phys[i]); |
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if (rc) { |
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phy_exit(hpriv->phys[i]); |
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goto disable_phys; |
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} |
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} |
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/* Re-enable host interrupts */ |
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spin_lock_irqsave(&host->lock, flags); |
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ctl = readl(mmio + HOST_CTL); |
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ctl |= HOST_IRQ_EN; |
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writel(ctl, mmio + HOST_CTL); |
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readl(mmio + HOST_CTL); /* flush */ |
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spin_unlock_irqrestore(&host->lock, flags); |
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return ata_do_dev_read_id(dev, tf, id); |
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disable_phys: |
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while (--i >= 0) { |
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phy_power_off(hpriv->phys[i]); |
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phy_exit(hpriv->phys[i]); |
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} |
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return AC_ERR_OTHER; |
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} |
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static void brcm_ahci_host_stop(struct ata_host *host) |
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{ |
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struct ahci_host_priv *hpriv = host->private_data; |
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ahci_platform_disable_resources(hpriv); |
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} |
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static struct ata_port_operations ahci_brcm_platform_ops = { |
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.inherits = &ahci_ops, |
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.host_stop = brcm_ahci_host_stop, |
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.read_id = brcm_ahci_read_id, |
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}; |
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static const struct ata_port_info ahci_brcm_port_info = { |
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.flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, |
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.link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, |
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.pio_mask = ATA_PIO4, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &ahci_brcm_platform_ops, |
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}; |
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static int brcm_ahci_suspend(struct device *dev) |
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{ |
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struct ata_host *host = dev_get_drvdata(dev); |
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struct ahci_host_priv *hpriv = host->private_data; |
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struct brcm_ahci_priv *priv = hpriv->plat_data; |
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int ret; |
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brcm_sata_phys_disable(priv); |
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if (IS_ENABLED(CONFIG_PM_SLEEP)) |
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ret = ahci_platform_suspend(dev); |
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else |
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ret = 0; |
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reset_control_assert(priv->rcdev_ahci); |
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reset_control_rearm(priv->rcdev_rescal); |
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return ret; |
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} |
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static int __maybe_unused brcm_ahci_resume(struct device *dev) |
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{ |
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struct ata_host *host = dev_get_drvdata(dev); |
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struct ahci_host_priv *hpriv = host->private_data; |
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struct brcm_ahci_priv *priv = hpriv->plat_data; |
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int ret = 0; |
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ret = reset_control_deassert(priv->rcdev_ahci); |
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if (ret) |
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return ret; |
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ret = reset_control_reset(priv->rcdev_rescal); |
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if (ret) |
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return ret; |
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/* Make sure clocks are turned on before re-configuration */ |
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ret = ahci_platform_enable_clks(hpriv); |
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if (ret) |
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return ret; |
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ret = ahci_platform_enable_regulators(hpriv); |
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if (ret) |
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goto out_disable_clks; |
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brcm_sata_init(priv); |
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brcm_sata_phys_enable(priv); |
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brcm_sata_alpm_init(hpriv); |
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/* Since we had to enable clocks earlier on, we cannot use |
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* ahci_platform_resume() as-is since a second call to |
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* ahci_platform_enable_resources() would bump up the resources |
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* (regulators, clocks, PHYs) count artificially so we copy the part |
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* after ahci_platform_enable_resources(). |
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*/ |
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ret = ahci_platform_enable_phys(hpriv); |
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if (ret) |
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goto out_disable_phys; |
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ret = ahci_platform_resume_host(dev); |
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if (ret) |
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goto out_disable_platform_phys; |
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/* We resumed so update PM runtime state */ |
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pm_runtime_disable(dev); |
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pm_runtime_set_active(dev); |
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pm_runtime_enable(dev); |
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return 0; |
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out_disable_platform_phys: |
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ahci_platform_disable_phys(hpriv); |
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out_disable_phys: |
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brcm_sata_phys_disable(priv); |
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ahci_platform_disable_regulators(hpriv); |
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out_disable_clks: |
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ahci_platform_disable_clks(hpriv); |
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return ret; |
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} |
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static struct scsi_host_template ahci_platform_sht = { |
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AHCI_SHT(DRV_NAME), |
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}; |
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static const struct of_device_id ahci_of_match[] = { |
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{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425}, |
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{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445}, |
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{.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445}, |
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{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP}, |
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{.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216}, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, ahci_of_match); |
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static int brcm_ahci_probe(struct platform_device *pdev) |
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{ |
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const struct of_device_id *of_id; |
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struct device *dev = &pdev->dev; |
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struct brcm_ahci_priv *priv; |
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struct ahci_host_priv *hpriv; |
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struct resource *res; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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of_id = of_match_node(ahci_of_match, pdev->dev.of_node); |
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if (!of_id) |
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return -ENODEV; |
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priv->version = (enum brcm_ahci_version)of_id->data; |
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priv->dev = dev; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl"); |
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priv->top_ctrl = devm_ioremap_resource(dev, res); |
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if (IS_ERR(priv->top_ctrl)) |
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return PTR_ERR(priv->top_ctrl); |
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if (priv->version == BRCM_SATA_BCM7216) { |
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priv->rcdev_rescal = devm_reset_control_get_optional_shared( |
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&pdev->dev, "rescal"); |
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if (IS_ERR(priv->rcdev_rescal)) |
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return PTR_ERR(priv->rcdev_rescal); |
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} |
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priv->rcdev_ahci = devm_reset_control_get_optional(&pdev->dev, "ahci"); |
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if (IS_ERR(priv->rcdev_ahci)) |
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return PTR_ERR(priv->rcdev_ahci); |
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hpriv = ahci_platform_get_resources(pdev, 0); |
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if (IS_ERR(hpriv)) |
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return PTR_ERR(hpriv); |
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hpriv->plat_data = priv; |
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hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO; |
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switch (priv->version) { |
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case BRCM_SATA_BCM7425: |
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hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE; |
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fallthrough; |
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case BRCM_SATA_NSP: |
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hpriv->flags |= AHCI_HFLAG_NO_NCQ; |
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priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE; |
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break; |
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default: |
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break; |
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} |
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ret = reset_control_reset(priv->rcdev_rescal); |
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if (ret) |
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return ret; |
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ret = reset_control_deassert(priv->rcdev_ahci); |
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if (ret) |
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return ret; |
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ret = ahci_platform_enable_clks(hpriv); |
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if (ret) |
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goto out_reset; |
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ret = ahci_platform_enable_regulators(hpriv); |
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if (ret) |
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goto out_disable_clks; |
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|
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/* Must be first so as to configure endianness including that |
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* of the standard AHCI register space. |
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*/ |
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brcm_sata_init(priv); |
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|
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/* Initializes priv->port_mask which is used below */ |
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priv->port_mask = brcm_ahci_get_portmask(hpriv, priv); |
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if (!priv->port_mask) { |
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ret = -ENODEV; |
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goto out_disable_regulators; |
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} |
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|
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/* Must be done before ahci_platform_enable_phys() */ |
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brcm_sata_phys_enable(priv); |
|
|
|
brcm_sata_alpm_init(hpriv); |
|
|
|
ret = ahci_platform_enable_phys(hpriv); |
|
if (ret) |
|
goto out_disable_phys; |
|
|
|
ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info, |
|
&ahci_platform_sht); |
|
if (ret) |
|
goto out_disable_platform_phys; |
|
|
|
dev_info(dev, "Broadcom AHCI SATA3 registered\n"); |
|
|
|
return 0; |
|
|
|
out_disable_platform_phys: |
|
ahci_platform_disable_phys(hpriv); |
|
out_disable_phys: |
|
brcm_sata_phys_disable(priv); |
|
out_disable_regulators: |
|
ahci_platform_disable_regulators(hpriv); |
|
out_disable_clks: |
|
ahci_platform_disable_clks(hpriv); |
|
out_reset: |
|
reset_control_assert(priv->rcdev_ahci); |
|
reset_control_rearm(priv->rcdev_rescal); |
|
return ret; |
|
} |
|
|
|
static int brcm_ahci_remove(struct platform_device *pdev) |
|
{ |
|
struct ata_host *host = dev_get_drvdata(&pdev->dev); |
|
struct ahci_host_priv *hpriv = host->private_data; |
|
struct brcm_ahci_priv *priv = hpriv->plat_data; |
|
int ret; |
|
|
|
brcm_sata_phys_disable(priv); |
|
|
|
ret = ata_platform_remove_one(pdev); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static void brcm_ahci_shutdown(struct platform_device *pdev) |
|
{ |
|
int ret; |
|
|
|
/* All resources releasing happens via devres, but our device, unlike a |
|
* proper remove is not disappearing, therefore using |
|
* brcm_ahci_suspend() here which does explicit power management is |
|
* appropriate. |
|
*/ |
|
ret = brcm_ahci_suspend(&pdev->dev); |
|
if (ret) |
|
dev_err(&pdev->dev, "failed to shutdown\n"); |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume); |
|
|
|
static struct platform_driver brcm_ahci_driver = { |
|
.probe = brcm_ahci_probe, |
|
.remove = brcm_ahci_remove, |
|
.shutdown = brcm_ahci_shutdown, |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = ahci_of_match, |
|
.pm = &ahci_brcm_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(brcm_ahci_driver); |
|
|
|
MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver"); |
|
MODULE_AUTHOR("Brian Norris"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:sata-brcmstb");
|
|
|