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160 lines
5.2 KiB
160 lines
5.2 KiB
.. SPDX-License-Identifier: GPL-2.0 |
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IRQ chip model (hierarchy) of LoongArch |
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======================================= |
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Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together |
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with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core |
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Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended |
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I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), |
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PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller |
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in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). |
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CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package |
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controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., |
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in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, |
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and there are two models of hierarchy (legacy model and extended model). |
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Legacy IRQ model |
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================ |
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go |
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to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices |
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interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go |
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to LIOINTC, and then CPUINTC:: |
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+-----+ +---------+ +-------+ |
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| IPI | --> | CPUINTC | <-- | Timer | |
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+-----+ +---------+ +-------+ |
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^ |
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| |
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+---------+ +-------+ |
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| LIOINTC | <-- | UARTs | |
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+---------+ +-------+ |
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^ |
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| |
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+-----------+ |
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| HTVECINTC | |
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+-----------+ |
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^ ^ |
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| | |
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+---------+ +---------+ |
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| PCH-PIC | | PCH-MSI | |
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+---------+ +---------+ |
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^ ^ ^ |
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| | | |
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+---------+ +---------+ +---------+ |
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| PCH-LPC | | Devices | | Devices | |
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+---------+ +---------+ +---------+ |
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^ |
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| |
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+---------+ |
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| Devices | |
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+---------+ |
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Extended IRQ model |
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================== |
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go |
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to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices |
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interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to |
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to CPUINTC directly:: |
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+-----+ +---------+ +-------+ |
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| IPI | --> | CPUINTC | <-- | Timer | |
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+-----+ +---------+ +-------+ |
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^ ^ |
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| | |
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+---------+ +---------+ +-------+ |
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| EIOINTC | | LIOINTC | <-- | UARTs | |
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+---------+ +---------+ +-------+ |
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^ ^ |
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| | |
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+---------+ +---------+ |
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| PCH-PIC | | PCH-MSI | |
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+---------+ +---------+ |
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^ ^ ^ |
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+---------+ +---------+ +---------+ |
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| PCH-LPC | | Devices | | Devices | |
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+---------+ +---------+ +---------+ |
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^ |
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+---------+ |
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| Devices | |
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+---------+ |
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ACPI-related definitions |
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======================== |
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CPUINTC:: |
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ACPI_MADT_TYPE_CORE_PIC; |
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struct acpi_madt_core_pic; |
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enum acpi_madt_core_pic_version; |
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LIOINTC:: |
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ACPI_MADT_TYPE_LIO_PIC; |
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struct acpi_madt_lio_pic; |
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enum acpi_madt_lio_pic_version; |
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EIOINTC:: |
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ACPI_MADT_TYPE_EIO_PIC; |
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struct acpi_madt_eio_pic; |
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enum acpi_madt_eio_pic_version; |
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HTVECINTC:: |
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ACPI_MADT_TYPE_HT_PIC; |
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struct acpi_madt_ht_pic; |
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enum acpi_madt_ht_pic_version; |
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PCH-PIC:: |
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ACPI_MADT_TYPE_BIO_PIC; |
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struct acpi_madt_bio_pic; |
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enum acpi_madt_bio_pic_version; |
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PCH-MSI:: |
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ACPI_MADT_TYPE_MSI_PIC; |
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struct acpi_madt_msi_pic; |
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enum acpi_madt_msi_pic_version; |
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PCH-LPC:: |
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ACPI_MADT_TYPE_LPC_PIC; |
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struct acpi_madt_lpc_pic; |
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enum acpi_madt_lpc_pic_version; |
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References |
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========== |
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Documentation of Loongson-3A5000: |
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese) |
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English) |
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Documentation of Loongson's LS7A chipset: |
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese) |
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English) |
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.. Note:: |
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- CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described |
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in Section 7.4 of "LoongArch Reference Manual, Vol 1"; |
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- LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of |
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"Loongson 3A5000 Processor Reference Manual"; |
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- EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of |
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"Loongson 3A5000 Processor Reference Manual"; |
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- HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of |
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"Loongson 3A5000 Processor Reference Manual"; |
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- PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of |
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"Loongson 7A1000 Bridge User Manual"; |
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- PCH-LPC is "LPC Interrupts" described in Section 24.3 of |
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"Loongson 7A1000 Bridge User Manual".
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