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580 lines
14 KiB
580 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* AMx3 Wkup M3 IPC driver |
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* |
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* Copyright (C) 2015 Texas Instruments, Inc. |
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* |
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* Dave Gerlach <[email protected]> |
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*/ |
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|
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#include <linux/err.h> |
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#include <linux/kernel.h> |
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#include <linux/kthread.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/omap-mailbox.h> |
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#include <linux/platform_device.h> |
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#include <linux/remoteproc.h> |
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#include <linux/suspend.h> |
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#include <linux/wkup_m3_ipc.h> |
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#define AM33XX_CTRL_IPC_REG_COUNT 0x8 |
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#define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m)) |
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/* AM33XX M3_TXEV_EOI register */ |
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#define AM33XX_CONTROL_M3_TXEV_EOI 0x00 |
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#define AM33XX_M3_TXEV_ACK (0x1 << 0) |
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#define AM33XX_M3_TXEV_ENABLE (0x0 << 0) |
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#define IPC_CMD_DS0 0x4 |
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#define IPC_CMD_STANDBY 0xc |
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#define IPC_CMD_IDLE 0x10 |
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#define IPC_CMD_RESET 0xe |
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#define DS_IPC_DEFAULT 0xffffffff |
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#define M3_VERSION_UNKNOWN 0x0000ffff |
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#define M3_BASELINE_VERSION 0x191 |
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#define M3_STATUS_RESP_MASK (0xffff << 16) |
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#define M3_FW_VERSION_MASK 0xffff |
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#define M3_WAKE_SRC_MASK 0xff |
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#define M3_STATE_UNKNOWN 0 |
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#define M3_STATE_RESET 1 |
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#define M3_STATE_INITED 2 |
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#define M3_STATE_MSG_FOR_LP 3 |
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#define M3_STATE_MSG_FOR_RESET 4 |
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static struct wkup_m3_ipc *m3_ipc_state; |
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static const struct wkup_m3_wakeup_src wakeups[] = { |
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{.irq_nr = 16, .src = "PRCM"}, |
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{.irq_nr = 35, .src = "USB0_PHY"}, |
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{.irq_nr = 36, .src = "USB1_PHY"}, |
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{.irq_nr = 40, .src = "I2C0"}, |
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{.irq_nr = 41, .src = "RTC Timer"}, |
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{.irq_nr = 42, .src = "RTC Alarm"}, |
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{.irq_nr = 43, .src = "Timer0"}, |
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{.irq_nr = 44, .src = "Timer1"}, |
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{.irq_nr = 45, .src = "UART"}, |
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{.irq_nr = 46, .src = "GPIO0"}, |
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{.irq_nr = 48, .src = "MPU_WAKE"}, |
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{.irq_nr = 49, .src = "WDT0"}, |
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{.irq_nr = 50, .src = "WDT1"}, |
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{.irq_nr = 51, .src = "ADC_TSC"}, |
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{.irq_nr = 0, .src = "Unknown"}, |
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}; |
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static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc) |
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{ |
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writel(AM33XX_M3_TXEV_ACK, |
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m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI); |
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} |
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static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc) |
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{ |
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writel(AM33XX_M3_TXEV_ENABLE, |
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m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI); |
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} |
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static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc, |
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u32 val, int ipc_reg_num) |
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{ |
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if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT, |
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"ipc register operation out of range")) |
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return; |
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writel(val, m3_ipc->ipc_mem_base + |
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AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num)); |
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} |
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static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc, |
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int ipc_reg_num) |
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{ |
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if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT, |
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"ipc register operation out of range")) |
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return 0; |
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return readl(m3_ipc->ipc_mem_base + |
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AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num)); |
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} |
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static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc) |
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{ |
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int val; |
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val = wkup_m3_ctrl_ipc_read(m3_ipc, 2); |
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return val & M3_FW_VERSION_MASK; |
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} |
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static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data) |
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{ |
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struct wkup_m3_ipc *m3_ipc = ipc_data; |
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struct device *dev = m3_ipc->dev; |
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int ver = 0; |
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am33xx_txev_eoi(m3_ipc); |
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switch (m3_ipc->state) { |
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case M3_STATE_RESET: |
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ver = wkup_m3_fw_version_read(m3_ipc); |
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if (ver == M3_VERSION_UNKNOWN || |
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ver < M3_BASELINE_VERSION) { |
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dev_warn(dev, "CM3 Firmware Version %x not supported\n", |
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ver); |
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} else { |
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dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver); |
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} |
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m3_ipc->state = M3_STATE_INITED; |
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complete(&m3_ipc->sync_complete); |
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break; |
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case M3_STATE_MSG_FOR_RESET: |
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m3_ipc->state = M3_STATE_INITED; |
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complete(&m3_ipc->sync_complete); |
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break; |
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case M3_STATE_MSG_FOR_LP: |
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complete(&m3_ipc->sync_complete); |
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break; |
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case M3_STATE_UNKNOWN: |
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dev_warn(dev, "Unknown CM3 State\n"); |
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} |
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am33xx_txev_enable(m3_ipc); |
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return IRQ_HANDLED; |
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} |
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static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc) |
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{ |
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struct device *dev = m3_ipc->dev; |
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mbox_msg_t dummy_msg = 0; |
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int ret; |
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if (!m3_ipc->mbox) { |
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dev_err(dev, |
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"No IPC channel to communicate with wkup_m3!\n"); |
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return -EIO; |
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} |
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/* |
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* Write a dummy message to the mailbox in order to trigger the RX |
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* interrupt to alert the M3 that data is available in the IPC |
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* registers. We must enable the IRQ here and disable it after in |
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* the RX callback to avoid multiple interrupts being received |
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* by the CM3. |
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*/ |
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ret = mbox_send_message(m3_ipc->mbox, &dummy_msg); |
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if (ret < 0) { |
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dev_err(dev, "%s: mbox_send_message() failed: %d\n", |
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__func__, ret); |
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return ret; |
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} |
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ret = wait_for_completion_timeout(&m3_ipc->sync_complete, |
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msecs_to_jiffies(500)); |
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if (!ret) { |
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dev_err(dev, "MPU<->CM3 sync failure\n"); |
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m3_ipc->state = M3_STATE_UNKNOWN; |
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return -EIO; |
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} |
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mbox_client_txdone(m3_ipc->mbox, 0); |
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return 0; |
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} |
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static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc) |
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{ |
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struct device *dev = m3_ipc->dev; |
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mbox_msg_t dummy_msg = 0; |
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int ret; |
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if (!m3_ipc->mbox) { |
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dev_err(dev, |
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"No IPC channel to communicate with wkup_m3!\n"); |
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return -EIO; |
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} |
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ret = mbox_send_message(m3_ipc->mbox, &dummy_msg); |
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if (ret < 0) { |
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dev_err(dev, "%s: mbox_send_message() failed: %d\n", |
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__func__, ret); |
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return ret; |
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} |
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mbox_client_txdone(m3_ipc->mbox, 0); |
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return 0; |
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} |
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static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc) |
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{ |
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return ((m3_ipc->state != M3_STATE_RESET) && |
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(m3_ipc->state != M3_STATE_UNKNOWN)); |
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} |
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/* Public functions */ |
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/** |
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* wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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* @mem_type: memory type value read directly from emif |
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* |
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* wkup_m3 must know what memory type is in use to properly suspend |
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* and resume. |
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*/ |
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static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type) |
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{ |
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m3_ipc->mem_type = mem_type; |
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} |
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/** |
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* wkup_m3_set_resume_address - Pass wkup_m3 resume address |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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* @addr: Physical address from which resume code should execute |
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*/ |
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static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr) |
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{ |
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m3_ipc->resume_addr = (unsigned long)addr; |
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} |
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/** |
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* wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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* |
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* Returns code representing the status of a low power mode transition. |
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* 0 - Successful transition |
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* 1 - Failure to transition to low power state |
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*/ |
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static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc) |
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{ |
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unsigned int i; |
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int val; |
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val = wkup_m3_ctrl_ipc_read(m3_ipc, 1); |
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i = M3_STATUS_RESP_MASK & val; |
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i >>= __ffs(M3_STATUS_RESP_MASK); |
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return i; |
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} |
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/** |
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* wkup_m3_prepare_low_power - Request preparation for transition to |
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* low power state |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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* @state: A kernel suspend state to enter, either MEM or STANDBY |
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* |
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* Returns 0 if preparation was successful, otherwise returns error code |
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*/ |
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static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state) |
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{ |
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struct device *dev = m3_ipc->dev; |
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int m3_power_state; |
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int ret = 0; |
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if (!wkup_m3_is_available(m3_ipc)) |
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return -ENODEV; |
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switch (state) { |
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case WKUP_M3_DEEPSLEEP: |
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m3_power_state = IPC_CMD_DS0; |
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break; |
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case WKUP_M3_STANDBY: |
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m3_power_state = IPC_CMD_STANDBY; |
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break; |
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case WKUP_M3_IDLE: |
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m3_power_state = IPC_CMD_IDLE; |
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break; |
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default: |
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return 1; |
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} |
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/* Program each required IPC register then write defaults to others */ |
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0); |
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1); |
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type, 4); |
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2); |
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3); |
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5); |
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6); |
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7); |
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m3_ipc->state = M3_STATE_MSG_FOR_LP; |
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if (state == WKUP_M3_IDLE) |
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ret = wkup_m3_ping_noirq(m3_ipc); |
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else |
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ret = wkup_m3_ping(m3_ipc); |
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if (ret) { |
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dev_err(dev, "Unable to ping CM3\n"); |
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return ret; |
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} |
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return 0; |
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} |
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/** |
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* wkup_m3_finish_low_power - Return m3 to reset state |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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* |
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* Returns 0 if reset was successful, otherwise returns error code |
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*/ |
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static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc) |
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{ |
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struct device *dev = m3_ipc->dev; |
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int ret = 0; |
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if (!wkup_m3_is_available(m3_ipc)) |
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return -ENODEV; |
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wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1); |
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2); |
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m3_ipc->state = M3_STATE_MSG_FOR_RESET; |
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ret = wkup_m3_ping(m3_ipc); |
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if (ret) { |
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dev_err(dev, "Unable to ping CM3\n"); |
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return ret; |
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} |
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return 0; |
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} |
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/** |
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* wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3 |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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*/ |
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static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc) |
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{ |
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unsigned int wakeup_src_idx; |
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int j, val; |
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val = wkup_m3_ctrl_ipc_read(m3_ipc, 6); |
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wakeup_src_idx = val & M3_WAKE_SRC_MASK; |
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for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) { |
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if (wakeups[j].irq_nr == wakeup_src_idx) |
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return wakeups[j].src; |
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} |
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return wakeups[j].src; |
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} |
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/** |
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* wkup_m3_set_rtc_only - Set the rtc_only flag |
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* @m3_ipc: Pointer to wkup_m3_ipc context |
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*/ |
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static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc) |
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{ |
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if (m3_ipc_state) |
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m3_ipc_state->is_rtc_only = true; |
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} |
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static struct wkup_m3_ipc_ops ipc_ops = { |
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.set_mem_type = wkup_m3_set_mem_type, |
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.set_resume_address = wkup_m3_set_resume_address, |
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.prepare_low_power = wkup_m3_prepare_low_power, |
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.finish_low_power = wkup_m3_finish_low_power, |
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.request_pm_status = wkup_m3_request_pm_status, |
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.request_wake_src = wkup_m3_request_wake_src, |
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.set_rtc_only = wkup_m3_set_rtc_only, |
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}; |
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/** |
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* wkup_m3_ipc_get - Return handle to wkup_m3_ipc |
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* |
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* Returns NULL if the wkup_m3 is not yet available, otherwise returns |
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* pointer to wkup_m3_ipc struct. |
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*/ |
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struct wkup_m3_ipc *wkup_m3_ipc_get(void) |
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{ |
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if (m3_ipc_state) |
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get_device(m3_ipc_state->dev); |
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else |
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return NULL; |
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return m3_ipc_state; |
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} |
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EXPORT_SYMBOL_GPL(wkup_m3_ipc_get); |
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/** |
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* wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get |
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* @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get |
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*/ |
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void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc) |
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{ |
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if (m3_ipc_state) |
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put_device(m3_ipc_state->dev); |
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} |
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EXPORT_SYMBOL_GPL(wkup_m3_ipc_put); |
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static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc) |
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{ |
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struct device *dev = m3_ipc->dev; |
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int ret; |
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init_completion(&m3_ipc->sync_complete); |
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ret = rproc_boot(m3_ipc->rproc); |
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if (ret) |
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dev_err(dev, "rproc_boot failed\n"); |
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else |
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m3_ipc_state = m3_ipc; |
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do_exit(0); |
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} |
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static int wkup_m3_ipc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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int irq, ret; |
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phandle rproc_phandle; |
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struct rproc *m3_rproc; |
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struct resource *res; |
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struct task_struct *task; |
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struct wkup_m3_ipc *m3_ipc; |
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m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL); |
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if (!m3_ipc) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(m3_ipc->ipc_mem_base)) { |
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dev_err(dev, "could not ioremap ipc_mem\n"); |
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return PTR_ERR(m3_ipc->ipc_mem_base); |
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} |
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irq = platform_get_irq(pdev, 0); |
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if (!irq) { |
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dev_err(&pdev->dev, "no irq resource\n"); |
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return -ENXIO; |
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} |
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ret = devm_request_irq(dev, irq, wkup_m3_txev_handler, |
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0, "wkup_m3_txev", m3_ipc); |
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if (ret) { |
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dev_err(dev, "request_irq failed\n"); |
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return ret; |
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} |
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m3_ipc->mbox_client.dev = dev; |
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m3_ipc->mbox_client.tx_done = NULL; |
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m3_ipc->mbox_client.tx_prepare = NULL; |
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m3_ipc->mbox_client.rx_callback = NULL; |
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m3_ipc->mbox_client.tx_block = false; |
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m3_ipc->mbox_client.knows_txdone = false; |
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m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0); |
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|
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if (IS_ERR(m3_ipc->mbox)) { |
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dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n", |
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PTR_ERR(m3_ipc->mbox)); |
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return PTR_ERR(m3_ipc->mbox); |
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} |
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if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) { |
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dev_err(&pdev->dev, "could not get rproc phandle\n"); |
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ret = -ENODEV; |
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goto err_free_mbox; |
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} |
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m3_rproc = rproc_get_by_phandle(rproc_phandle); |
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if (!m3_rproc) { |
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dev_err(&pdev->dev, "could not get rproc handle\n"); |
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ret = -EPROBE_DEFER; |
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goto err_free_mbox; |
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} |
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m3_ipc->rproc = m3_rproc; |
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m3_ipc->dev = dev; |
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m3_ipc->state = M3_STATE_RESET; |
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|
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m3_ipc->ops = &ipc_ops; |
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|
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/* |
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* Wait for firmware loading completion in a thread so we |
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* can boot the wkup_m3 as soon as it's ready without holding |
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* up kernel boot |
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*/ |
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task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc, |
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"wkup_m3_rproc_loader"); |
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|
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if (IS_ERR(task)) { |
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dev_err(dev, "can't create rproc_boot thread\n"); |
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ret = PTR_ERR(task); |
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goto err_put_rproc; |
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} |
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|
|
return 0; |
|
|
|
err_put_rproc: |
|
rproc_put(m3_rproc); |
|
err_free_mbox: |
|
mbox_free_channel(m3_ipc->mbox); |
|
return ret; |
|
} |
|
|
|
static int wkup_m3_ipc_remove(struct platform_device *pdev) |
|
{ |
|
mbox_free_channel(m3_ipc_state->mbox); |
|
|
|
rproc_shutdown(m3_ipc_state->rproc); |
|
rproc_put(m3_ipc_state->rproc); |
|
|
|
m3_ipc_state = NULL; |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev) |
|
{ |
|
/* |
|
* Nothing needs to be done on suspend even with rtc_only flag set |
|
*/ |
|
return 0; |
|
} |
|
|
|
static int __maybe_unused wkup_m3_ipc_resume(struct device *dev) |
|
{ |
|
if (m3_ipc_state->is_rtc_only) { |
|
rproc_shutdown(m3_ipc_state->rproc); |
|
rproc_boot(m3_ipc_state->rproc); |
|
} |
|
|
|
m3_ipc_state->is_rtc_only = false; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops wkup_m3_ipc_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume) |
|
}; |
|
|
|
static const struct of_device_id wkup_m3_ipc_of_match[] = { |
|
{ .compatible = "ti,am3352-wkup-m3-ipc", }, |
|
{ .compatible = "ti,am4372-wkup-m3-ipc", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match); |
|
|
|
static struct platform_driver wkup_m3_ipc_driver = { |
|
.probe = wkup_m3_ipc_probe, |
|
.remove = wkup_m3_ipc_remove, |
|
.driver = { |
|
.name = "wkup_m3_ipc", |
|
.of_match_table = wkup_m3_ipc_of_match, |
|
.pm = &wkup_m3_ipc_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(wkup_m3_ipc_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("wkup m3 remote processor ipc driver"); |
|
MODULE_AUTHOR("Dave Gerlach <[email protected]>");
|
|
|