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155 lines
5.0 KiB
155 lines
5.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright © 2009 - Maxim Levitsky |
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* driver for Ricoh xD readers |
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*/ |
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#include <linux/pci.h> |
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#include <linux/completion.h> |
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#include <linux/workqueue.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/spinlock.h> |
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/* nand interface + ecc |
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byte write/read does one cycle on nand data lines. |
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dword write/read does 4 cycles |
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if R852_CTL_ECC_ACCESS is set in R852_CTL, then dword read reads |
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results of ecc correction, if DMA read was done before. |
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If write was done two dword reads read generated ecc checksums |
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*/ |
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#define R852_DATALINE 0x00 |
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/* control register */ |
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#define R852_CTL 0x04 |
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#define R852_CTL_COMMAND 0x01 /* send command (#CLE)*/ |
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#define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/ |
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#define R852_CTL_ON 0x04 /* only seem to controls the hd led, */ |
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/* but has to be set on start...*/ |
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#define R852_CTL_RESET 0x08 /* unknown, set only on start once*/ |
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#define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/ |
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#define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */ |
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#define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/ |
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#define R852_CTL_WRITE 0x80 /* set when performing writes (#WP) */ |
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/* card detection status */ |
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#define R852_CARD_STA 0x05 |
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#define R852_CARD_STA_CD 0x01 /* state of #CD line, same as 0x04 */ |
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#define R852_CARD_STA_RO 0x02 /* card is readonly */ |
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#define R852_CARD_STA_PRESENT 0x04 /* card is present (#CD) */ |
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#define R852_CARD_STA_ABSENT 0x08 /* card is absent */ |
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#define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */ |
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/* card detection irq status & enable*/ |
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#define R852_CARD_IRQ_STA 0x06 /* IRQ status */ |
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#define R852_CARD_IRQ_ENABLE 0x07 /* IRQ enable */ |
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#define R852_CARD_IRQ_CD 0x01 /* fire when #CD lights, same as 0x04*/ |
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#define R852_CARD_IRQ_REMOVE 0x04 /* detect card removal */ |
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#define R852_CARD_IRQ_INSERT 0x08 /* detect card insert */ |
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#define R852_CARD_IRQ_UNK1 0x10 /* unknown */ |
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#define R852_CARD_IRQ_GENABLE 0x80 /* general enable */ |
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#define R852_CARD_IRQ_MASK 0x1D |
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/* hardware enable */ |
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#define R852_HW 0x08 |
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#define R852_HW_ENABLED 0x01 /* hw enabled */ |
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#define R852_HW_UNKNOWN 0x80 |
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/* dma capabilities */ |
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#define R852_DMA_CAP 0x09 |
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#define R852_SMBIT 0x20 /* if set with bit #6 or bit #7, then */ |
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/* hw is smartmedia */ |
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#define R852_DMA1 0x40 /* if set w/bit #7, dma is supported */ |
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#define R852_DMA2 0x80 /* if set w/bit #6, dma is supported */ |
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/* physical DMA address - 32 bit value*/ |
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#define R852_DMA_ADDR 0x0C |
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/* dma settings */ |
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#define R852_DMA_SETTINGS 0x10 |
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#define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */ |
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#define R852_DMA_READ 0x02 /* 0 = write, 1 = read */ |
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#define R852_DMA_INTERNAL 0x04 /* (internal hw buffer <-> card) */ |
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/* dma IRQ status */ |
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#define R852_DMA_IRQ_STA 0x14 |
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/* dma IRQ enable */ |
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#define R852_DMA_IRQ_ENABLE 0x18 |
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#define R852_DMA_IRQ_MEMORY 0x01 /* (memory <-> internal hw buffer) */ |
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#define R852_DMA_IRQ_ERROR 0x02 /* error did happen */ |
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#define R852_DMA_IRQ_INTERNAL 0x04 /* (internal hw buffer <-> card) */ |
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#define R852_DMA_IRQ_MASK 0x07 /* mask of all IRQ bits */ |
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/* ECC syndrome format - read from reg #0 will return two copies of these for |
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each half of the page. |
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first byte is error byte location, and second, bit location + flags */ |
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#define R852_ECC_ERR_BIT_MSK 0x07 /* error bit location */ |
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#define R852_ECC_CORRECT 0x10 /* no errors - (guessed) */ |
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#define R852_ECC_CORRECTABLE 0x20 /* correctable error exist */ |
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#define R852_ECC_FAIL 0x40 /* non correctable error detected */ |
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#define R852_DMA_LEN 512 |
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#define DMA_INTERNAL 0 |
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#define DMA_MEMORY 1 |
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struct r852_device { |
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struct nand_controller controller; |
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void __iomem *mmio; /* mmio */ |
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struct nand_chip *chip; /* nand chip backpointer */ |
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struct pci_dev *pci_dev; /* pci backpointer */ |
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/* dma area */ |
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dma_addr_t phys_dma_addr; /* bus address of buffer*/ |
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struct completion dma_done; /* data transfer done */ |
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dma_addr_t phys_bounce_buffer; /* bus address of bounce buffer */ |
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uint8_t *bounce_buffer; /* virtual address of bounce buffer */ |
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int dma_dir; /* 1 = read, 0 = write */ |
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int dma_stage; /* 0 - idle, 1 - first step, |
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2 - second step */ |
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int dma_state; /* 0 = internal, 1 = memory */ |
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int dma_error; /* dma errors */ |
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int dma_usable; /* is it possible to use dma */ |
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/* card status area */ |
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struct delayed_work card_detect_work; |
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struct workqueue_struct *card_workqueue; |
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int card_registered; /* card registered with mtd */ |
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int card_detected; /* card detected in slot */ |
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int card_unstable; /* whenever the card is inserted, |
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is not known yet */ |
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int readonly; /* card is readonly */ |
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int sm; /* Is card smartmedia */ |
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/* interrupt handling */ |
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spinlock_t irqlock; /* IRQ protecting lock */ |
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int irq; /* irq num */ |
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/* misc */ |
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void *tmp_buffer; /* temporary buffer */ |
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uint8_t ctlreg; /* cached contents of control reg */ |
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}; |
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#define dbg(format, ...) \ |
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if (debug) \ |
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pr_debug(format "\n", ## __VA_ARGS__) |
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#define dbg_verbose(format, ...) \ |
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if (debug > 1) \ |
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pr_debug(format "\n", ## __VA_ARGS__) |
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#define message(format, ...) \ |
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pr_info(format "\n", ## __VA_ARGS__)
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