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588 lines
14 KiB
588 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2019 Macronix International Co., Ltd. |
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* |
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* Author: |
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* Mason Yang <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/nand-ecc-sw-hamming.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/platform_device.h> |
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#include "internals.h" |
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#define HC_CFG 0x0 |
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#define HC_CFG_IF_CFG(x) ((x) << 27) |
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#define HC_CFG_DUAL_SLAVE BIT(31) |
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#define HC_CFG_INDIVIDUAL BIT(30) |
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#define HC_CFG_NIO(x) (((x) / 4) << 27) |
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#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2))) |
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#define HC_CFG_TYPE_SPI_NOR 0 |
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#define HC_CFG_TYPE_SPI_NAND 1 |
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#define HC_CFG_TYPE_SPI_RAM 2 |
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#define HC_CFG_TYPE_RAW_NAND 3 |
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#define HC_CFG_SLV_ACT(x) ((x) << 21) |
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#define HC_CFG_CLK_PH_EN BIT(20) |
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#define HC_CFG_CLK_POL_INV BIT(19) |
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#define HC_CFG_BIG_ENDIAN BIT(18) |
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#define HC_CFG_DATA_PASS BIT(17) |
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#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16) |
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#define HC_CFG_MAN_START_EN BIT(3) |
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#define HC_CFG_MAN_START BIT(2) |
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#define HC_CFG_MAN_CS_EN BIT(1) |
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#define HC_CFG_MAN_CS_ASSERT BIT(0) |
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#define INT_STS 0x4 |
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#define INT_STS_EN 0x8 |
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#define INT_SIG_EN 0xc |
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#define INT_STS_ALL GENMASK(31, 0) |
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#define INT_RDY_PIN BIT(26) |
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#define INT_RDY_SR BIT(25) |
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#define INT_LNR_SUSP BIT(24) |
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#define INT_ECC_ERR BIT(17) |
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#define INT_CRC_ERR BIT(16) |
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#define INT_LWR_DIS BIT(12) |
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#define INT_LRD_DIS BIT(11) |
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#define INT_SDMA_INT BIT(10) |
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#define INT_DMA_FINISH BIT(9) |
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#define INT_RX_NOT_FULL BIT(3) |
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#define INT_RX_NOT_EMPTY BIT(2) |
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#define INT_TX_NOT_FULL BIT(1) |
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#define INT_TX_EMPTY BIT(0) |
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#define HC_EN 0x10 |
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#define HC_EN_BIT BIT(0) |
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#define TXD(x) (0x14 + ((x) * 4)) |
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#define RXD 0x24 |
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#define SS_CTRL(s) (0x30 + ((s) * 4)) |
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#define LRD_CFG 0x44 |
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#define LWR_CFG 0x80 |
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#define RWW_CFG 0x70 |
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#define OP_READ BIT(23) |
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#define OP_DUMMY_CYC(x) ((x) << 17) |
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#define OP_ADDR_BYTES(x) ((x) << 14) |
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#define OP_CMD_BYTES(x) (((x) - 1) << 13) |
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#define OP_OCTA_CRC_EN BIT(12) |
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#define OP_DQS_EN BIT(11) |
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#define OP_ENHC_EN BIT(10) |
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#define OP_PREAMBLE_EN BIT(9) |
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#define OP_DATA_DDR BIT(8) |
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#define OP_DATA_BUSW(x) ((x) << 6) |
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#define OP_ADDR_DDR BIT(5) |
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#define OP_ADDR_BUSW(x) ((x) << 3) |
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#define OP_CMD_DDR BIT(2) |
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#define OP_CMD_BUSW(x) (x) |
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#define OP_BUSW_1 0 |
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#define OP_BUSW_2 1 |
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#define OP_BUSW_4 2 |
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#define OP_BUSW_8 3 |
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#define OCTA_CRC 0x38 |
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#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) |
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#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16))) |
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#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) |
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#define ONFI_DIN_CNT(s) (0x3c + (s)) |
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#define LRD_CTRL 0x48 |
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#define RWW_CTRL 0x74 |
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#define LWR_CTRL 0x84 |
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#define LMODE_EN BIT(31) |
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#define LMODE_SLV_ACT(x) ((x) << 21) |
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#define LMODE_CMD1(x) ((x) << 8) |
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#define LMODE_CMD0(x) (x) |
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#define LRD_ADDR 0x4c |
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#define LWR_ADDR 0x88 |
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#define LRD_RANGE 0x50 |
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#define LWR_RANGE 0x8c |
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#define AXI_SLV_ADDR 0x54 |
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#define DMAC_RD_CFG 0x58 |
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#define DMAC_WR_CFG 0x94 |
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#define DMAC_CFG_PERIPH_EN BIT(31) |
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#define DMAC_CFG_ALLFLUSH_EN BIT(30) |
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#define DMAC_CFG_LASTFLUSH_EN BIT(29) |
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#define DMAC_CFG_QE(x) (((x) + 1) << 16) |
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#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12) |
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#define DMAC_CFG_BURST_SZ(x) ((x) << 8) |
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#define DMAC_CFG_DIR_READ BIT(1) |
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#define DMAC_CFG_START BIT(0) |
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#define DMAC_RD_CNT 0x5c |
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#define DMAC_WR_CNT 0x98 |
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#define SDMA_ADDR 0x60 |
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#define DMAM_CFG 0x64 |
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#define DMAM_CFG_START BIT(31) |
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#define DMAM_CFG_CONT BIT(30) |
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#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2) |
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#define DMAM_CFG_DIR_READ BIT(1) |
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#define DMAM_CFG_EN BIT(0) |
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#define DMAM_CNT 0x68 |
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#define LNR_TIMER_TH 0x6c |
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#define RDM_CFG0 0x78 |
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#define RDM_CFG0_POLY(x) (x) |
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#define RDM_CFG1 0x7c |
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#define RDM_CFG1_RDM_EN BIT(31) |
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#define RDM_CFG1_SEED(x) (x) |
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#define LWR_SUSP_CTRL 0x90 |
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#define LWR_SUSP_CTRL_EN BIT(31) |
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#define DMAS_CTRL 0x9c |
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#define DMAS_CTRL_EN BIT(31) |
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#define DMAS_CTRL_DIR_READ BIT(30) |
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#define DATA_STROB 0xa0 |
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#define DATA_STROB_EDO_EN BIT(2) |
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#define DATA_STROB_INV_POL BIT(1) |
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#define DATA_STROB_DELAY_2CYC BIT(0) |
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#define IDLY_CODE(x) (0xa4 + ((x) * 4)) |
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#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8)) |
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#define GPIO 0xc4 |
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#define GPIO_PT(x) BIT(3 + ((x) * 16)) |
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#define GPIO_RESET(x) BIT(2 + ((x) * 16)) |
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#define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) |
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#define GPIO_WPB(x) BIT((x) * 16) |
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#define HC_VER 0xd0 |
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#define HW_TEST(x) (0xe0 + ((x) * 4)) |
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#define MXIC_NFC_MAX_CLK_HZ 50000000 |
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#define IRQ_TIMEOUT 1000 |
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struct mxic_nand_ctlr { |
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struct clk *ps_clk; |
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struct clk *send_clk; |
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struct clk *send_dly_clk; |
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struct completion complete; |
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void __iomem *regs; |
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struct nand_controller controller; |
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struct device *dev; |
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struct nand_chip chip; |
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}; |
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static int mxic_nfc_clk_enable(struct mxic_nand_ctlr *nfc) |
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{ |
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int ret; |
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ret = clk_prepare_enable(nfc->ps_clk); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(nfc->send_clk); |
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if (ret) |
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goto err_ps_clk; |
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ret = clk_prepare_enable(nfc->send_dly_clk); |
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if (ret) |
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goto err_send_dly_clk; |
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return ret; |
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err_send_dly_clk: |
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clk_disable_unprepare(nfc->send_clk); |
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err_ps_clk: |
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clk_disable_unprepare(nfc->ps_clk); |
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return ret; |
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} |
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static void mxic_nfc_clk_disable(struct mxic_nand_ctlr *nfc) |
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{ |
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clk_disable_unprepare(nfc->send_clk); |
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clk_disable_unprepare(nfc->send_dly_clk); |
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clk_disable_unprepare(nfc->ps_clk); |
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} |
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static void mxic_nfc_set_input_delay(struct mxic_nand_ctlr *nfc, u8 idly_code) |
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{ |
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writel(IDLY_CODE_VAL(0, idly_code) | |
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IDLY_CODE_VAL(1, idly_code) | |
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IDLY_CODE_VAL(2, idly_code) | |
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IDLY_CODE_VAL(3, idly_code), |
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nfc->regs + IDLY_CODE(0)); |
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writel(IDLY_CODE_VAL(4, idly_code) | |
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IDLY_CODE_VAL(5, idly_code) | |
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IDLY_CODE_VAL(6, idly_code) | |
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IDLY_CODE_VAL(7, idly_code), |
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nfc->regs + IDLY_CODE(1)); |
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} |
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static int mxic_nfc_clk_setup(struct mxic_nand_ctlr *nfc, unsigned long freq) |
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{ |
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int ret; |
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ret = clk_set_rate(nfc->send_clk, freq); |
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if (ret) |
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return ret; |
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ret = clk_set_rate(nfc->send_dly_clk, freq); |
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if (ret) |
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return ret; |
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/* |
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* A constant delay range from 0x0 ~ 0x1F for input delay, |
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* the unit is 78 ps, the max input delay is 2.418 ns. |
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*/ |
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mxic_nfc_set_input_delay(nfc, 0xf); |
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/* |
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* Phase degree = 360 * freq * output-delay |
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* where output-delay is a constant value 1 ns in FPGA. |
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* |
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* Get Phase degree = 360 * freq * 1 ns |
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* = 360 * freq * 1 sec / 1000000000 |
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* = 9 * freq / 25000000 |
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*/ |
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ret = clk_set_phase(nfc->send_dly_clk, 9 * freq / 25000000); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int mxic_nfc_set_freq(struct mxic_nand_ctlr *nfc, unsigned long freq) |
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{ |
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int ret; |
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if (freq > MXIC_NFC_MAX_CLK_HZ) |
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freq = MXIC_NFC_MAX_CLK_HZ; |
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mxic_nfc_clk_disable(nfc); |
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ret = mxic_nfc_clk_setup(nfc, freq); |
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if (ret) |
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return ret; |
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ret = mxic_nfc_clk_enable(nfc); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static irqreturn_t mxic_nfc_isr(int irq, void *dev_id) |
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{ |
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struct mxic_nand_ctlr *nfc = dev_id; |
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u32 sts; |
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sts = readl(nfc->regs + INT_STS); |
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if (sts & INT_RDY_PIN) |
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complete(&nfc->complete); |
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else |
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return IRQ_NONE; |
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return IRQ_HANDLED; |
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} |
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static void mxic_nfc_hw_init(struct mxic_nand_ctlr *nfc) |
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{ |
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writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) | |
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HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | |
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HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG); |
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writel(INT_STS_ALL, nfc->regs + INT_STS_EN); |
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writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN); |
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writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); |
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writel(0, nfc->regs + LRD_CFG); |
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writel(0, nfc->regs + LRD_CTRL); |
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writel(0x0, nfc->regs + HC_EN); |
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} |
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static void mxic_nfc_cs_enable(struct mxic_nand_ctlr *nfc) |
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{ |
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writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN, |
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nfc->regs + HC_CFG); |
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writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG), |
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nfc->regs + HC_CFG); |
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} |
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static void mxic_nfc_cs_disable(struct mxic_nand_ctlr *nfc) |
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{ |
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writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG), |
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nfc->regs + HC_CFG); |
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} |
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static int mxic_nfc_wait_ready(struct nand_chip *chip) |
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{ |
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struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip); |
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int ret; |
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ret = wait_for_completion_timeout(&nfc->complete, |
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msecs_to_jiffies(IRQ_TIMEOUT)); |
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if (!ret) { |
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dev_err(nfc->dev, "nand device timeout\n"); |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static int mxic_nfc_data_xfer(struct mxic_nand_ctlr *nfc, const void *txbuf, |
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void *rxbuf, unsigned int len) |
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{ |
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unsigned int pos = 0; |
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while (pos < len) { |
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unsigned int nbytes = len - pos; |
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u32 data = 0xffffffff; |
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u32 sts; |
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int ret; |
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if (nbytes > 4) |
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nbytes = 4; |
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if (txbuf) |
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memcpy(&data, txbuf + pos, nbytes); |
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ret = readl_poll_timeout(nfc->regs + INT_STS, sts, |
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sts & INT_TX_EMPTY, 0, USEC_PER_SEC); |
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if (ret) |
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return ret; |
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writel(data, nfc->regs + TXD(nbytes % 4)); |
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ret = readl_poll_timeout(nfc->regs + INT_STS, sts, |
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sts & INT_TX_EMPTY, 0, USEC_PER_SEC); |
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if (ret) |
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return ret; |
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ret = readl_poll_timeout(nfc->regs + INT_STS, sts, |
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sts & INT_RX_NOT_EMPTY, 0, |
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USEC_PER_SEC); |
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if (ret) |
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return ret; |
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data = readl(nfc->regs + RXD); |
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if (rxbuf) { |
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data >>= (8 * (4 - nbytes)); |
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memcpy(rxbuf + pos, &data, nbytes); |
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} |
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if (readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY) |
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dev_warn(nfc->dev, "RX FIFO not empty\n"); |
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pos += nbytes; |
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} |
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return 0; |
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} |
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static int mxic_nfc_exec_op(struct nand_chip *chip, |
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const struct nand_operation *op, bool check_only) |
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{ |
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struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip); |
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const struct nand_op_instr *instr = NULL; |
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int ret = 0; |
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unsigned int op_id; |
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if (check_only) |
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return 0; |
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mxic_nfc_cs_enable(nfc); |
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init_completion(&nfc->complete); |
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for (op_id = 0; op_id < op->ninstrs; op_id++) { |
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instr = &op->instrs[op_id]; |
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switch (instr->type) { |
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case NAND_OP_CMD_INSTR: |
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writel(0, nfc->regs + HC_EN); |
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writel(HC_EN_BIT, nfc->regs + HC_EN); |
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writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | |
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OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0)); |
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ret = mxic_nfc_data_xfer(nfc, |
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&instr->ctx.cmd.opcode, |
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NULL, 1); |
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break; |
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case NAND_OP_ADDR_INSTR: |
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writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | |
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OP_ADDR_BYTES(instr->ctx.addr.naddrs), |
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nfc->regs + SS_CTRL(0)); |
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ret = mxic_nfc_data_xfer(nfc, |
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instr->ctx.addr.addrs, NULL, |
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instr->ctx.addr.naddrs); |
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break; |
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case NAND_OP_DATA_IN_INSTR: |
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writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); |
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writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | |
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OP_READ, nfc->regs + SS_CTRL(0)); |
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ret = mxic_nfc_data_xfer(nfc, NULL, |
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instr->ctx.data.buf.in, |
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instr->ctx.data.len); |
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break; |
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case NAND_OP_DATA_OUT_INSTR: |
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writel(instr->ctx.data.len, |
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nfc->regs + ONFI_DIN_CNT(0)); |
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writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F), |
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nfc->regs + SS_CTRL(0)); |
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ret = mxic_nfc_data_xfer(nfc, |
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instr->ctx.data.buf.out, NULL, |
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instr->ctx.data.len); |
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break; |
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case NAND_OP_WAITRDY_INSTR: |
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ret = mxic_nfc_wait_ready(chip); |
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break; |
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} |
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} |
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mxic_nfc_cs_disable(nfc); |
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return ret; |
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} |
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static int mxic_nfc_setup_interface(struct nand_chip *chip, int chipnr, |
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const struct nand_interface_config *conf) |
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{ |
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struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip); |
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const struct nand_sdr_timings *sdr; |
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unsigned long freq; |
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int ret; |
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sdr = nand_get_sdr_timings(conf); |
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if (IS_ERR(sdr)) |
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return PTR_ERR(sdr); |
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if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) |
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return 0; |
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freq = NSEC_PER_SEC / (sdr->tRC_min / 1000); |
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ret = mxic_nfc_set_freq(nfc, freq); |
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if (ret) |
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dev_err(nfc->dev, "set freq:%ld failed\n", freq); |
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if (sdr->tRC_min < 30000) |
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writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB); |
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return 0; |
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} |
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static const struct nand_controller_ops mxic_nand_controller_ops = { |
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.exec_op = mxic_nfc_exec_op, |
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.setup_interface = mxic_nfc_setup_interface, |
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}; |
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static int mxic_nfc_probe(struct platform_device *pdev) |
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{ |
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struct device_node *nand_np, *np = pdev->dev.of_node; |
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struct mtd_info *mtd; |
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struct mxic_nand_ctlr *nfc; |
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struct nand_chip *nand_chip; |
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int err; |
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int irq; |
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nfc = devm_kzalloc(&pdev->dev, sizeof(struct mxic_nand_ctlr), |
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GFP_KERNEL); |
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if (!nfc) |
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return -ENOMEM; |
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nfc->ps_clk = devm_clk_get(&pdev->dev, "ps"); |
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if (IS_ERR(nfc->ps_clk)) |
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return PTR_ERR(nfc->ps_clk); |
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nfc->send_clk = devm_clk_get(&pdev->dev, "send"); |
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if (IS_ERR(nfc->send_clk)) |
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return PTR_ERR(nfc->send_clk); |
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nfc->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly"); |
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if (IS_ERR(nfc->send_dly_clk)) |
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return PTR_ERR(nfc->send_dly_clk); |
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nfc->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(nfc->regs)) |
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return PTR_ERR(nfc->regs); |
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|
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nand_chip = &nfc->chip; |
|
mtd = nand_to_mtd(nand_chip); |
|
mtd->dev.parent = &pdev->dev; |
|
|
|
for_each_child_of_node(np, nand_np) |
|
nand_set_flash_node(nand_chip, nand_np); |
|
|
|
nand_chip->priv = nfc; |
|
nfc->dev = &pdev->dev; |
|
nfc->controller.ops = &mxic_nand_controller_ops; |
|
nand_controller_init(&nfc->controller); |
|
nand_chip->controller = &nfc->controller; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
mxic_nfc_hw_init(nfc); |
|
|
|
err = devm_request_irq(&pdev->dev, irq, mxic_nfc_isr, |
|
0, "mxic-nfc", nfc); |
|
if (err) |
|
goto fail; |
|
|
|
err = nand_scan(nand_chip, 1); |
|
if (err) |
|
goto fail; |
|
|
|
err = mtd_device_register(mtd, NULL, 0); |
|
if (err) |
|
goto fail; |
|
|
|
platform_set_drvdata(pdev, nfc); |
|
return 0; |
|
|
|
fail: |
|
mxic_nfc_clk_disable(nfc); |
|
return err; |
|
} |
|
|
|
static int mxic_nfc_remove(struct platform_device *pdev) |
|
{ |
|
struct mxic_nand_ctlr *nfc = platform_get_drvdata(pdev); |
|
struct nand_chip *chip = &nfc->chip; |
|
int ret; |
|
|
|
ret = mtd_device_unregister(nand_to_mtd(chip)); |
|
WARN_ON(ret); |
|
nand_cleanup(chip); |
|
|
|
mxic_nfc_clk_disable(nfc); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id mxic_nfc_of_ids[] = { |
|
{ .compatible = "mxic,multi-itfc-v009-nand-controller", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, mxic_nfc_of_ids); |
|
|
|
static struct platform_driver mxic_nfc_driver = { |
|
.probe = mxic_nfc_probe, |
|
.remove = mxic_nfc_remove, |
|
.driver = { |
|
.name = "mxic-nfc", |
|
.of_match_table = mxic_nfc_of_ids, |
|
}, |
|
}; |
|
module_platform_driver(mxic_nfc_driver); |
|
|
|
MODULE_AUTHOR("Mason Yang <[email protected]>"); |
|
MODULE_DESCRIPTION("Macronix raw NAND controller driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|