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724 lines
18 KiB
724 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* Copyright (c) 2020 Intel Corporation. */ |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-direction.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/nand.h> |
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#include <linux/platform_device.h> |
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#include <linux/sched.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include <asm/unaligned.h> |
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#define EBU_CLC 0x000 |
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#define EBU_CLC_RST 0x00000000u |
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#define EBU_ADDR_SEL(n) (0x020 + (n) * 4) |
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/* 5 bits 26:22 included for comparison in the ADDR_SELx */ |
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#define EBU_ADDR_MASK(x) ((x) << 4) |
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#define EBU_ADDR_SEL_REGEN 0x1 |
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#define EBU_BUSCON(n) (0x060 + (n) * 4) |
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#define EBU_BUSCON_CMULT_V4 0x1 |
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#define EBU_BUSCON_RECOVC(n) ((n) << 2) |
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#define EBU_BUSCON_HOLDC(n) ((n) << 4) |
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#define EBU_BUSCON_WAITRDC(n) ((n) << 6) |
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#define EBU_BUSCON_WAITWRC(n) ((n) << 8) |
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#define EBU_BUSCON_BCGEN_CS 0x0 |
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#define EBU_BUSCON_SETUP_EN BIT(22) |
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#define EBU_BUSCON_ALEC 0xC000 |
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#define EBU_CON 0x0B0 |
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#define EBU_CON_NANDM_EN BIT(0) |
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#define EBU_CON_NANDM_DIS 0x0 |
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#define EBU_CON_CSMUX_E_EN BIT(1) |
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#define EBU_CON_ALE_P_LOW BIT(2) |
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#define EBU_CON_CLE_P_LOW BIT(3) |
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#define EBU_CON_CS_P_LOW BIT(4) |
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#define EBU_CON_SE_P_LOW BIT(5) |
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#define EBU_CON_WP_P_LOW BIT(6) |
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#define EBU_CON_PRE_P_LOW BIT(7) |
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#define EBU_CON_IN_CS_S(n) ((n) << 8) |
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#define EBU_CON_OUT_CS_S(n) ((n) << 10) |
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#define EBU_CON_LAT_EN_CS_P ((0x3D) << 18) |
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#define EBU_WAIT 0x0B4 |
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#define EBU_WAIT_RDBY BIT(0) |
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#define EBU_WAIT_WR_C BIT(3) |
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#define HSNAND_CTL1 0x110 |
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#define HSNAND_CTL1_ADDR_SHIFT 24 |
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#define HSNAND_CTL2 0x114 |
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#define HSNAND_CTL2_ADDR_SHIFT 8 |
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#define HSNAND_CTL2_CYC_N_V5 (0x2 << 16) |
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#define HSNAND_INT_MSK_CTL 0x124 |
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#define HSNAND_INT_MSK_CTL_WR_C BIT(4) |
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#define HSNAND_INT_STA 0x128 |
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#define HSNAND_INT_STA_WR_C BIT(4) |
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#define HSNAND_CTL 0x130 |
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#define HSNAND_CTL_ENABLE_ECC BIT(0) |
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#define HSNAND_CTL_GO BIT(2) |
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#define HSNAND_CTL_CE_SEL_CS(n) BIT(3 + (n)) |
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#define HSNAND_CTL_RW_READ 0x0 |
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#define HSNAND_CTL_RW_WRITE BIT(10) |
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#define HSNAND_CTL_ECC_OFF_V8TH BIT(11) |
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#define HSNAND_CTL_CKFF_EN 0x0 |
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#define HSNAND_CTL_MSG_EN BIT(17) |
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#define HSNAND_PARA0 0x13c |
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#define HSNAND_PARA0_PAGE_V8192 0x3 |
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#define HSNAND_PARA0_PIB_V256 (0x3 << 4) |
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#define HSNAND_PARA0_BYP_EN_NP 0x0 |
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#define HSNAND_PARA0_BYP_DEC_NP 0x0 |
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#define HSNAND_PARA0_TYPE_ONFI BIT(18) |
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#define HSNAND_PARA0_ADEP_EN BIT(21) |
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#define HSNAND_CMSG_0 0x150 |
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#define HSNAND_CMSG_1 0x154 |
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#define HSNAND_ALE_OFFS BIT(2) |
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#define HSNAND_CLE_OFFS BIT(3) |
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#define HSNAND_CS_OFFS BIT(4) |
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#define HSNAND_ECC_OFFSET 0x008 |
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#define NAND_DATA_IFACE_CHECK_ONLY -1 |
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#define MAX_CS 2 |
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#define HZ_PER_MHZ 1000000L |
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#define USEC_PER_SEC 1000000L |
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struct ebu_nand_cs { |
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void __iomem *chipaddr; |
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dma_addr_t nand_pa; |
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u32 addr_sel; |
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}; |
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struct ebu_nand_controller { |
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struct nand_controller controller; |
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struct nand_chip chip; |
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struct device *dev; |
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void __iomem *ebu; |
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void __iomem *hsnand; |
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struct dma_chan *dma_tx; |
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struct dma_chan *dma_rx; |
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struct completion dma_access_complete; |
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unsigned long clk_rate; |
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struct clk *clk; |
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u32 nd_para0; |
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u8 cs_num; |
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struct ebu_nand_cs cs[MAX_CS]; |
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}; |
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static inline struct ebu_nand_controller *nand_to_ebu(struct nand_chip *chip) |
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{ |
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return container_of(chip, struct ebu_nand_controller, chip); |
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} |
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static int ebu_nand_waitrdy(struct nand_chip *chip, int timeout_ms) |
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{ |
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struct ebu_nand_controller *ctrl = nand_to_ebu(chip); |
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u32 status; |
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return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status, |
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(status & EBU_WAIT_RDBY) || |
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(status & EBU_WAIT_WR_C), 20, timeout_ms); |
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} |
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static u8 ebu_nand_readb(struct nand_chip *chip) |
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{ |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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u8 cs_num = ebu_host->cs_num; |
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u8 val; |
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val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS); |
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ebu_nand_waitrdy(chip, 1000); |
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return val; |
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} |
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static void ebu_nand_writeb(struct nand_chip *chip, u32 offset, u8 value) |
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{ |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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u8 cs_num = ebu_host->cs_num; |
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writeb(value, ebu_host->cs[cs_num].chipaddr + offset); |
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ebu_nand_waitrdy(chip, 1000); |
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} |
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static void ebu_read_buf(struct nand_chip *chip, u_char *buf, unsigned int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++) |
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buf[i] = ebu_nand_readb(chip); |
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} |
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static void ebu_write_buf(struct nand_chip *chip, const u_char *buf, int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++) |
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ebu_nand_writeb(chip, HSNAND_CS_OFFS, buf[i]); |
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} |
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static void ebu_nand_disable(struct nand_chip *chip) |
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{ |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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writel(0, ebu_host->ebu + EBU_CON); |
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} |
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static void ebu_select_chip(struct nand_chip *chip) |
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{ |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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void __iomem *nand_con = ebu_host->ebu + EBU_CON; |
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u32 cs = ebu_host->cs_num; |
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writel(EBU_CON_NANDM_EN | EBU_CON_CSMUX_E_EN | EBU_CON_CS_P_LOW | |
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EBU_CON_SE_P_LOW | EBU_CON_WP_P_LOW | EBU_CON_PRE_P_LOW | |
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EBU_CON_IN_CS_S(cs) | EBU_CON_OUT_CS_S(cs) | |
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EBU_CON_LAT_EN_CS_P, nand_con); |
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} |
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static int ebu_nand_set_timings(struct nand_chip *chip, int csline, |
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const struct nand_interface_config *conf) |
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{ |
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struct ebu_nand_controller *ctrl = nand_to_ebu(chip); |
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unsigned int rate = clk_get_rate(ctrl->clk) / HZ_PER_MHZ; |
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unsigned int period = DIV_ROUND_UP(USEC_PER_SEC, rate); |
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const struct nand_sdr_timings *timings; |
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u32 trecov, thold, twrwait, trdwait; |
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u32 reg = 0; |
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timings = nand_get_sdr_timings(conf); |
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if (IS_ERR(timings)) |
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return PTR_ERR(timings); |
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if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
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return 0; |
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trecov = DIV_ROUND_UP(max(timings->tREA_max, timings->tREH_min), |
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period); |
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reg |= EBU_BUSCON_RECOVC(trecov); |
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thold = DIV_ROUND_UP(max(timings->tDH_min, timings->tDS_min), period); |
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reg |= EBU_BUSCON_HOLDC(thold); |
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trdwait = DIV_ROUND_UP(max(timings->tRC_min, timings->tREH_min), |
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period); |
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reg |= EBU_BUSCON_WAITRDC(trdwait); |
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twrwait = DIV_ROUND_UP(max(timings->tWC_min, timings->tWH_min), period); |
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reg |= EBU_BUSCON_WAITWRC(twrwait); |
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reg |= EBU_BUSCON_CMULT_V4 | EBU_BUSCON_BCGEN_CS | EBU_BUSCON_ALEC | |
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EBU_BUSCON_SETUP_EN; |
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writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num)); |
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return 0; |
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} |
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static int ebu_nand_ooblayout_ecc(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *oobregion) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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if (section) |
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return -ERANGE; |
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oobregion->offset = HSNAND_ECC_OFFSET; |
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oobregion->length = chip->ecc.total; |
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return 0; |
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} |
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static int ebu_nand_ooblayout_free(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *oobregion) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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if (section) |
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return -ERANGE; |
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oobregion->offset = chip->ecc.total + HSNAND_ECC_OFFSET; |
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oobregion->length = mtd->oobsize - oobregion->offset; |
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return 0; |
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} |
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static const struct mtd_ooblayout_ops ebu_nand_ooblayout_ops = { |
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.ecc = ebu_nand_ooblayout_ecc, |
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.free = ebu_nand_ooblayout_free, |
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}; |
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static void ebu_dma_rx_callback(void *cookie) |
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{ |
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struct ebu_nand_controller *ebu_host = cookie; |
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dmaengine_terminate_async(ebu_host->dma_rx); |
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complete(&ebu_host->dma_access_complete); |
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} |
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static void ebu_dma_tx_callback(void *cookie) |
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{ |
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struct ebu_nand_controller *ebu_host = cookie; |
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dmaengine_terminate_async(ebu_host->dma_tx); |
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complete(&ebu_host->dma_access_complete); |
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} |
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static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir, |
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const u8 *buf, u32 len) |
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{ |
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struct dma_async_tx_descriptor *tx; |
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struct completion *dma_completion; |
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dma_async_tx_callback callback; |
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struct dma_chan *chan; |
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dma_cookie_t cookie; |
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unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
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dma_addr_t buf_dma; |
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int ret; |
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u32 timeout; |
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if (dir == DMA_DEV_TO_MEM) { |
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chan = ebu_host->dma_rx; |
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dma_completion = &ebu_host->dma_access_complete; |
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callback = ebu_dma_rx_callback; |
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} else { |
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chan = ebu_host->dma_tx; |
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dma_completion = &ebu_host->dma_access_complete; |
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callback = ebu_dma_tx_callback; |
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} |
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buf_dma = dma_map_single(chan->device->dev, (void *)buf, len, dir); |
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if (dma_mapping_error(chan->device->dev, buf_dma)) { |
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dev_err(ebu_host->dev, "Failed to map DMA buffer\n"); |
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ret = -EIO; |
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goto err_unmap; |
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} |
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tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags); |
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if (!tx) { |
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ret = -ENXIO; |
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goto err_unmap; |
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} |
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tx->callback = callback; |
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tx->callback_param = ebu_host; |
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cookie = tx->tx_submit(tx); |
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ret = dma_submit_error(cookie); |
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if (ret) { |
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dev_err(ebu_host->dev, "dma_submit_error %d\n", cookie); |
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ret = -EIO; |
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goto err_unmap; |
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} |
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init_completion(dma_completion); |
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dma_async_issue_pending(chan); |
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/* Wait DMA to finish the data transfer.*/ |
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timeout = wait_for_completion_timeout(dma_completion, msecs_to_jiffies(1000)); |
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if (!timeout) { |
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dev_err(ebu_host->dev, "I/O Error in DMA RX (status %d)\n", |
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dmaengine_tx_status(chan, cookie, NULL)); |
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dmaengine_terminate_sync(chan); |
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ret = -ETIMEDOUT; |
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goto err_unmap; |
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} |
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return 0; |
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err_unmap: |
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dma_unmap_single(ebu_host->dev, buf_dma, len, dir); |
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return ret; |
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} |
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static void ebu_nand_trigger(struct ebu_nand_controller *ebu_host, |
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int page, u32 cmd) |
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{ |
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unsigned int val; |
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val = cmd | (page & 0xFF) << HSNAND_CTL1_ADDR_SHIFT; |
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writel(val, ebu_host->hsnand + HSNAND_CTL1); |
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val = (page & 0xFFFF00) >> 8 | HSNAND_CTL2_CYC_N_V5; |
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writel(val, ebu_host->hsnand + HSNAND_CTL2); |
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writel(ebu_host->nd_para0, ebu_host->hsnand + HSNAND_PARA0); |
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/* clear first, will update later */ |
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writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_0); |
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writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_1); |
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writel(HSNAND_INT_MSK_CTL_WR_C, |
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ebu_host->hsnand + HSNAND_INT_MSK_CTL); |
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if (!cmd) |
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val = HSNAND_CTL_RW_READ; |
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else |
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val = HSNAND_CTL_RW_WRITE; |
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writel(HSNAND_CTL_MSG_EN | HSNAND_CTL_CKFF_EN | |
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HSNAND_CTL_ECC_OFF_V8TH | HSNAND_CTL_CE_SEL_CS(ebu_host->cs_num) | |
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HSNAND_CTL_ENABLE_ECC | HSNAND_CTL_GO | val, |
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ebu_host->hsnand + HSNAND_CTL); |
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} |
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static int ebu_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf, |
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int oob_required, int page) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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int ret, reg_data; |
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ebu_nand_trigger(ebu_host, page, NAND_CMD_READ0); |
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ret = ebu_dma_start(ebu_host, DMA_DEV_TO_MEM, buf, mtd->writesize); |
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if (ret) |
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return ret; |
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if (oob_required) |
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chip->ecc.read_oob(chip, page); |
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reg_data = readl(ebu_host->hsnand + HSNAND_CTL); |
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reg_data &= ~HSNAND_CTL_GO; |
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writel(reg_data, ebu_host->hsnand + HSNAND_CTL); |
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return 0; |
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} |
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static int ebu_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf, |
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int oob_required, int page) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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void __iomem *int_sta = ebu_host->hsnand + HSNAND_INT_STA; |
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int reg_data, ret, val; |
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u32 reg; |
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ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN); |
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ret = ebu_dma_start(ebu_host, DMA_MEM_TO_DEV, buf, mtd->writesize); |
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if (ret) |
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return ret; |
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if (oob_required) { |
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reg = get_unaligned_le32(chip->oob_poi); |
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writel(reg, ebu_host->hsnand + HSNAND_CMSG_0); |
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reg = get_unaligned_le32(chip->oob_poi + 4); |
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writel(reg, ebu_host->hsnand + HSNAND_CMSG_1); |
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} |
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ret = readl_poll_timeout_atomic(int_sta, val, !(val & HSNAND_INT_STA_WR_C), |
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10, 1000); |
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if (ret) |
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return ret; |
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reg_data = readl(ebu_host->hsnand + HSNAND_CTL); |
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reg_data &= ~HSNAND_CTL_GO; |
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writel(reg_data, ebu_host->hsnand + HSNAND_CTL); |
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return 0; |
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} |
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static const u8 ecc_strength[] = { 1, 1, 4, 8, 24, 32, 40, 60, }; |
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static int ebu_nand_attach_chip(struct nand_chip *chip) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip); |
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u32 ecc_steps, ecc_bytes, ecc_total, pagesize, pg_per_blk; |
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u32 ecc_strength_ds = chip->ecc.strength; |
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u32 ecc_size = chip->ecc.size; |
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u32 writesize = mtd->writesize; |
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u32 blocksize = mtd->erasesize; |
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int bch_algo, start, val; |
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/* Default to an ECC size of 512 */ |
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if (!chip->ecc.size) |
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chip->ecc.size = 512; |
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switch (ecc_size) { |
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case 512: |
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start = 1; |
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if (!ecc_strength_ds) |
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ecc_strength_ds = 4; |
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break; |
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case 1024: |
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start = 4; |
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if (!ecc_strength_ds) |
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ecc_strength_ds = 32; |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* BCH ECC algorithm Settings for number of bits per 512B/1024B */ |
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bch_algo = round_up(start + 1, 4); |
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for (val = start; val < bch_algo; val++) { |
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if (ecc_strength_ds == ecc_strength[val]) |
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break; |
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} |
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if (val == bch_algo) |
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return -EINVAL; |
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if (ecc_strength_ds == 8) |
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ecc_bytes = 14; |
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else |
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ecc_bytes = DIV_ROUND_UP(ecc_strength_ds * fls(8 * ecc_size), 8); |
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|
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ecc_steps = writesize / ecc_size; |
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ecc_total = ecc_steps * ecc_bytes; |
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if ((ecc_total + 8) > mtd->oobsize) |
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return -ERANGE; |
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|
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chip->ecc.total = ecc_total; |
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pagesize = fls(writesize >> 11); |
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if (pagesize > HSNAND_PARA0_PAGE_V8192) |
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return -ERANGE; |
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pg_per_blk = fls((blocksize / writesize) >> 6) / 8; |
|
if (pg_per_blk > HSNAND_PARA0_PIB_V256) |
|
return -ERANGE; |
|
|
|
ebu_host->nd_para0 = pagesize | pg_per_blk | HSNAND_PARA0_BYP_EN_NP | |
|
HSNAND_PARA0_BYP_DEC_NP | HSNAND_PARA0_ADEP_EN | |
|
HSNAND_PARA0_TYPE_ONFI | (val << 29); |
|
|
|
mtd_set_ooblayout(mtd, &ebu_nand_ooblayout_ops); |
|
chip->ecc.read_page = ebu_nand_read_page_hwecc; |
|
chip->ecc.write_page = ebu_nand_write_page_hwecc; |
|
|
|
return 0; |
|
} |
|
|
|
static int ebu_nand_exec_op(struct nand_chip *chip, |
|
const struct nand_operation *op, bool check_only) |
|
{ |
|
const struct nand_op_instr *instr = NULL; |
|
unsigned int op_id; |
|
int i, timeout_ms, ret = 0; |
|
|
|
if (check_only) |
|
return 0; |
|
|
|
ebu_select_chip(chip); |
|
for (op_id = 0; op_id < op->ninstrs; op_id++) { |
|
instr = &op->instrs[op_id]; |
|
|
|
switch (instr->type) { |
|
case NAND_OP_CMD_INSTR: |
|
ebu_nand_writeb(chip, HSNAND_CLE_OFFS | HSNAND_CS_OFFS, |
|
instr->ctx.cmd.opcode); |
|
break; |
|
|
|
case NAND_OP_ADDR_INSTR: |
|
for (i = 0; i < instr->ctx.addr.naddrs; i++) |
|
ebu_nand_writeb(chip, |
|
HSNAND_ALE_OFFS | HSNAND_CS_OFFS, |
|
instr->ctx.addr.addrs[i]); |
|
break; |
|
|
|
case NAND_OP_DATA_IN_INSTR: |
|
ebu_read_buf(chip, instr->ctx.data.buf.in, |
|
instr->ctx.data.len); |
|
break; |
|
|
|
case NAND_OP_DATA_OUT_INSTR: |
|
ebu_write_buf(chip, instr->ctx.data.buf.out, |
|
instr->ctx.data.len); |
|
break; |
|
|
|
case NAND_OP_WAITRDY_INSTR: |
|
timeout_ms = instr->ctx.waitrdy.timeout_ms * 1000; |
|
ret = ebu_nand_waitrdy(chip, timeout_ms); |
|
break; |
|
} |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static const struct nand_controller_ops ebu_nand_controller_ops = { |
|
.attach_chip = ebu_nand_attach_chip, |
|
.setup_interface = ebu_nand_set_timings, |
|
.exec_op = ebu_nand_exec_op, |
|
}; |
|
|
|
static void ebu_dma_cleanup(struct ebu_nand_controller *ebu_host) |
|
{ |
|
if (ebu_host->dma_rx) |
|
dma_release_channel(ebu_host->dma_rx); |
|
|
|
if (ebu_host->dma_tx) |
|
dma_release_channel(ebu_host->dma_tx); |
|
} |
|
|
|
static int ebu_nand_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct ebu_nand_controller *ebu_host; |
|
struct nand_chip *nand; |
|
struct mtd_info *mtd; |
|
struct resource *res; |
|
char *resname; |
|
int ret; |
|
u32 cs; |
|
|
|
ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL); |
|
if (!ebu_host) |
|
return -ENOMEM; |
|
|
|
ebu_host->dev = dev; |
|
nand_controller_init(&ebu_host->controller); |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand"); |
|
ebu_host->ebu = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(ebu_host->ebu)) |
|
return PTR_ERR(ebu_host->ebu); |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand"); |
|
ebu_host->hsnand = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(ebu_host->hsnand)) |
|
return PTR_ERR(ebu_host->hsnand); |
|
|
|
ret = device_property_read_u32(dev, "reg", &cs); |
|
if (ret) { |
|
dev_err(dev, "failed to get chip select: %d\n", ret); |
|
return ret; |
|
} |
|
ebu_host->cs_num = cs; |
|
|
|
resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", cs); |
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname); |
|
ebu_host->cs[cs].chipaddr = devm_ioremap_resource(dev, res); |
|
ebu_host->cs[cs].nand_pa = res->start; |
|
if (IS_ERR(ebu_host->cs[cs].chipaddr)) |
|
return PTR_ERR(ebu_host->cs[cs].chipaddr); |
|
|
|
ebu_host->clk = devm_clk_get(dev, NULL); |
|
if (IS_ERR(ebu_host->clk)) |
|
return dev_err_probe(dev, PTR_ERR(ebu_host->clk), |
|
"failed to get clock\n"); |
|
|
|
ret = clk_prepare_enable(ebu_host->clk); |
|
if (ret) { |
|
dev_err(dev, "failed to enable clock: %d\n", ret); |
|
return ret; |
|
} |
|
ebu_host->clk_rate = clk_get_rate(ebu_host->clk); |
|
|
|
ebu_host->dma_tx = dma_request_chan(dev, "tx"); |
|
if (IS_ERR(ebu_host->dma_tx)) |
|
return dev_err_probe(dev, PTR_ERR(ebu_host->dma_tx), |
|
"failed to request DMA tx chan!.\n"); |
|
|
|
ebu_host->dma_rx = dma_request_chan(dev, "rx"); |
|
if (IS_ERR(ebu_host->dma_rx)) |
|
return dev_err_probe(dev, PTR_ERR(ebu_host->dma_rx), |
|
"failed to request DMA rx chan!.\n"); |
|
|
|
resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", cs); |
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname); |
|
if (!res) |
|
return -EINVAL; |
|
ebu_host->cs[cs].addr_sel = res->start; |
|
writel(ebu_host->cs[cs].addr_sel | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN, |
|
ebu_host->ebu + EBU_ADDR_SEL(cs)); |
|
|
|
nand_set_flash_node(&ebu_host->chip, dev->of_node); |
|
|
|
mtd = nand_to_mtd(&ebu_host->chip); |
|
if (!mtd->name) { |
|
dev_err(ebu_host->dev, "NAND label property is mandatory\n"); |
|
return -EINVAL; |
|
} |
|
|
|
mtd->dev.parent = dev; |
|
ebu_host->dev = dev; |
|
|
|
platform_set_drvdata(pdev, ebu_host); |
|
nand_set_controller_data(&ebu_host->chip, ebu_host); |
|
|
|
nand = &ebu_host->chip; |
|
nand->controller = &ebu_host->controller; |
|
nand->controller->ops = &ebu_nand_controller_ops; |
|
|
|
/* Scan to find existence of the device */ |
|
ret = nand_scan(&ebu_host->chip, 1); |
|
if (ret) |
|
goto err_cleanup_dma; |
|
|
|
ret = mtd_device_register(mtd, NULL, 0); |
|
if (ret) |
|
goto err_clean_nand; |
|
|
|
return 0; |
|
|
|
err_clean_nand: |
|
nand_cleanup(&ebu_host->chip); |
|
err_cleanup_dma: |
|
ebu_dma_cleanup(ebu_host); |
|
clk_disable_unprepare(ebu_host->clk); |
|
|
|
return ret; |
|
} |
|
|
|
static int ebu_nand_remove(struct platform_device *pdev) |
|
{ |
|
struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev); |
|
int ret; |
|
|
|
ret = mtd_device_unregister(nand_to_mtd(&ebu_host->chip)); |
|
WARN_ON(ret); |
|
nand_cleanup(&ebu_host->chip); |
|
ebu_nand_disable(&ebu_host->chip); |
|
ebu_dma_cleanup(ebu_host); |
|
clk_disable_unprepare(ebu_host->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id ebu_nand_match[] = { |
|
{ .compatible = "intel,nand-controller" }, |
|
{ .compatible = "intel,lgm-ebunand" }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, ebu_nand_match); |
|
|
|
static struct platform_driver ebu_nand_driver = { |
|
.probe = ebu_nand_probe, |
|
.remove = ebu_nand_remove, |
|
.driver = { |
|
.name = "intel-nand-controller", |
|
.of_match_table = ebu_nand_match, |
|
}, |
|
|
|
}; |
|
module_platform_driver(ebu_nand_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_AUTHOR("Vadivel Murugan R <[email protected]>"); |
|
MODULE_DESCRIPTION("Intel's LGM External Bus NAND Controller driver");
|
|
|