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188 lines
5.6 KiB
188 lines
5.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Clock event driver for the CS5535/CS5536 |
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* |
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* Copyright (C) 2006, Advanced Micro Devices, Inc. |
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* Copyright (C) 2007 Andres Salomon <[email protected]> |
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* Copyright (C) 2009 Andres Salomon <[email protected]> |
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* |
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* The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/irq.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/cs5535.h> |
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#include <linux/clockchips.h> |
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#define DRV_NAME "cs5535-clockevt" |
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static int timer_irq; |
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module_param_hw_named(irq, timer_irq, int, irq, 0644); |
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MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks."); |
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/* |
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* We are using the 32.768kHz input clock - it's the only one that has the |
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* ranges we find desirable. The following table lists the suitable |
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* divisors and the associated Hz, minimum interval and the maximum interval: |
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* |
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* Divisor Hz Min Delta (s) Max Delta (s) |
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* 1 32768 .00048828125 2.000 |
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* 2 16384 .0009765625 4.000 |
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* 4 8192 .001953125 8.000 |
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* 8 4096 .00390625 16.000 |
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* 16 2048 .0078125 32.000 |
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* 32 1024 .015625 64.000 |
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* 64 512 .03125 128.000 |
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* 128 256 .0625 256.000 |
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* 256 128 .125 512.000 |
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*/ |
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static struct cs5535_mfgpt_timer *cs5535_event_clock; |
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/* Selected from the table above */ |
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#define MFGPT_DIVISOR 16 |
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#define MFGPT_SCALE 4 /* divisor = 2^(scale) */ |
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#define MFGPT_HZ (32768 / MFGPT_DIVISOR) |
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#define MFGPT_PERIODIC (MFGPT_HZ / HZ) |
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/* |
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* The MFGPT timers on the CS5536 provide us with suitable timers to use |
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* as clock event sources - not as good as a HPET or APIC, but certainly |
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* better than the PIT. This isn't a general purpose MFGPT driver, but |
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* a simplified one designed specifically to act as a clock event source. |
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* For full details about the MFGPT, please consult the CS5536 data sheet. |
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*/ |
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static void disable_timer(struct cs5535_mfgpt_timer *timer) |
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{ |
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/* avoid races by clearing CMP1 and CMP2 unconditionally */ |
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cs5535_mfgpt_write(timer, MFGPT_REG_SETUP, |
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(uint16_t) ~MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP1 | |
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MFGPT_SETUP_CMP2); |
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} |
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static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta) |
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{ |
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cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta); |
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cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0); |
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cs5535_mfgpt_write(timer, MFGPT_REG_SETUP, |
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MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); |
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} |
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static int mfgpt_shutdown(struct clock_event_device *evt) |
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{ |
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disable_timer(cs5535_event_clock); |
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return 0; |
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} |
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static int mfgpt_set_periodic(struct clock_event_device *evt) |
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{ |
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disable_timer(cs5535_event_clock); |
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start_timer(cs5535_event_clock, MFGPT_PERIODIC); |
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return 0; |
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} |
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static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt) |
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{ |
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start_timer(cs5535_event_clock, delta); |
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return 0; |
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} |
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static struct clock_event_device cs5535_clockevent = { |
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.name = DRV_NAME, |
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
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.set_state_shutdown = mfgpt_shutdown, |
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.set_state_periodic = mfgpt_set_periodic, |
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.set_state_oneshot = mfgpt_shutdown, |
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.tick_resume = mfgpt_shutdown, |
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.set_next_event = mfgpt_next_event, |
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.rating = 250, |
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}; |
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static irqreturn_t mfgpt_tick(int irq, void *dev_id) |
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{ |
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uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP); |
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/* See if the interrupt was for us */ |
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if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1))) |
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return IRQ_NONE; |
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/* Turn off the clock (and clear the event) */ |
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disable_timer(cs5535_event_clock); |
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if (clockevent_state_detached(&cs5535_clockevent) || |
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clockevent_state_shutdown(&cs5535_clockevent)) |
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return IRQ_HANDLED; |
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/* Clear the counter */ |
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cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0); |
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/* Restart the clock in periodic mode */ |
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if (clockevent_state_periodic(&cs5535_clockevent)) |
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cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, |
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MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); |
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cs5535_clockevent.event_handler(&cs5535_clockevent); |
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return IRQ_HANDLED; |
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} |
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static int __init cs5535_mfgpt_init(void) |
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{ |
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unsigned long flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED; |
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struct cs5535_mfgpt_timer *timer; |
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int ret; |
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uint16_t val; |
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timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING); |
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if (!timer) { |
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printk(KERN_ERR DRV_NAME ": Could not allocate MFGPT timer\n"); |
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return -ENODEV; |
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} |
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cs5535_event_clock = timer; |
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/* Set up the IRQ on the MFGPT side */ |
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if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) { |
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printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n", |
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timer_irq); |
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goto err_timer; |
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} |
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/* And register it with the kernel */ |
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ret = request_irq(timer_irq, mfgpt_tick, flags, DRV_NAME, timer); |
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if (ret) { |
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printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n"); |
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goto err_irq; |
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} |
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/* Set the clock scale and enable the event mode for CMP2 */ |
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val = MFGPT_SCALE | (3 << 8); |
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cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val); |
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/* Set up the clock event */ |
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printk(KERN_INFO DRV_NAME |
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": Registering MFGPT timer as a clock event, using IRQ %d\n", |
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timer_irq); |
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clockevents_config_and_register(&cs5535_clockevent, MFGPT_HZ, |
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0xF, 0xFFFE); |
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return 0; |
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err_irq: |
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cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq); |
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err_timer: |
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cs5535_mfgpt_free_timer(cs5535_event_clock); |
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printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n"); |
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return -EIO; |
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} |
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module_init(cs5535_mfgpt_init); |
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MODULE_AUTHOR("Andres Salomon <[email protected]>"); |
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MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver"); |
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MODULE_LICENSE("GPL");
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