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122 lines
3.0 KiB
122 lines
3.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. |
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* |
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* Author: Michael Johnston <[email protected]> |
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* |
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* Description: |
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* TWR-P102x Board Setup |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/errno.h> |
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#include <linux/fsl/guts.h> |
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#include <linux/pci.h> |
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#include <linux/of_platform.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/udbg.h> |
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#include <asm/mpic.h> |
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#include <soc/fsl/qe/qe.h> |
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#include <sysdev/fsl_soc.h> |
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#include <sysdev/fsl_pci.h> |
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#include "smp.h" |
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#include "mpc85xx.h" |
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static void __init twr_p1025_pic_init(void) |
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{ |
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struct mpic *mpic; |
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mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | |
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MPIC_SINGLE_DEST_CPU, |
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0, 256, " OpenPIC "); |
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BUG_ON(mpic == NULL); |
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mpic_init(mpic); |
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} |
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/* ************************************************************************ |
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* |
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* Setup the architecture |
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* |
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*/ |
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static void __init twr_p1025_setup_arch(void) |
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{ |
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if (ppc_md.progress) |
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ppc_md.progress("twr_p1025_setup_arch()", 0); |
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mpc85xx_smp_init(); |
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fsl_pci_assign_primary(); |
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#ifdef CONFIG_QUICC_ENGINE |
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mpc85xx_qe_par_io_init(); |
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#if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE) |
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if (machine_is(twr_p1025)) { |
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struct ccsr_guts __iomem *guts; |
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struct device_node *np; |
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np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts"); |
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if (np) { |
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guts = of_iomap(np, 0); |
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if (!guts) |
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pr_err("twr_p1025: could not map global utilities register\n"); |
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else { |
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/* P1025 has pins muxed for QE and other functions. To |
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* enable QE UEC mode, we need to set bit QE0 for UCC1 |
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* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 |
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* and QE12 for QE MII management signals in PMUXCR |
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* register. |
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* Set QE mux bits in PMUXCR */ |
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setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | |
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MPC85xx_PMUXCR_QE(3) | |
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MPC85xx_PMUXCR_QE(9) | |
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MPC85xx_PMUXCR_QE(12)); |
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iounmap(guts); |
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#if IS_ENABLED(CONFIG_SERIAL_QE) |
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/* On P1025TWR board, the UCC7 acted as UART port. |
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* However, The UCC7's CTS pin is low level in default, |
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* it will impact the transmission in full duplex |
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* communication. So disable the Flow control pin PA18. |
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* The UCC7 UART just can use RXD and TXD pins. |
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*/ |
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par_io_config_pin(0, 18, 0, 0, 0, 0); |
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#endif |
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/* Drive PB29 to CPLD low - CPLD will then change |
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* muxing from LBC to QE */ |
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par_io_config_pin(1, 29, 1, 0, 0, 0); |
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par_io_data_set(1, 29, 0); |
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} |
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of_node_put(np); |
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} |
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} |
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#endif |
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#endif /* CONFIG_QUICC_ENGINE */ |
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pr_info("TWR-P1025 board from Freescale Semiconductor\n"); |
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} |
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machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices); |
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static int __init twr_p1025_probe(void) |
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{ |
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return of_machine_is_compatible("fsl,TWR-P1025"); |
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} |
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define_machine(twr_p1025) { |
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.name = "TWR-P1025", |
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.probe = twr_p1025_probe, |
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.setup_arch = twr_p1025_setup_arch, |
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.init_IRQ = twr_p1025_pic_init, |
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#ifdef CONFIG_PCI |
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
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#endif |
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.get_irq = mpic_get_irq, |
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.calibrate_decr = generic_calibrate_decr, |
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.progress = udbg_progress, |
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};
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