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227 lines
5.8 KiB
227 lines
5.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2014 Mans Rullgard <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/ioport.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/slab.h> |
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#define IRQ0_CTL_BASE 0x0000 |
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#define IRQ1_CTL_BASE 0x0100 |
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#define EDGE_CTL_BASE 0x0200 |
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#define IRQ2_CTL_BASE 0x0300 |
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#define IRQ_CTL_HI 0x18 |
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#define EDGE_CTL_HI 0x20 |
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#define IRQ_STATUS 0x00 |
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#define IRQ_RAWSTAT 0x04 |
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#define IRQ_EN_SET 0x08 |
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#define IRQ_EN_CLR 0x0c |
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#define IRQ_SOFT_SET 0x10 |
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#define IRQ_SOFT_CLR 0x14 |
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#define EDGE_STATUS 0x00 |
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#define EDGE_RAWSTAT 0x04 |
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#define EDGE_CFG_RISE 0x08 |
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#define EDGE_CFG_FALL 0x0c |
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#define EDGE_CFG_RISE_SET 0x10 |
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#define EDGE_CFG_RISE_CLR 0x14 |
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#define EDGE_CFG_FALL_SET 0x18 |
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#define EDGE_CFG_FALL_CLR 0x1c |
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struct tangox_irq_chip { |
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void __iomem *base; |
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unsigned long ctl; |
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}; |
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static inline u32 intc_readl(struct tangox_irq_chip *chip, int reg) |
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{ |
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return readl_relaxed(chip->base + reg); |
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} |
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static inline void intc_writel(struct tangox_irq_chip *chip, int reg, u32 val) |
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{ |
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writel_relaxed(val, chip->base + reg); |
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} |
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static void tangox_dispatch_irqs(struct irq_domain *dom, unsigned int status, |
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int base) |
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{ |
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unsigned int hwirq; |
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unsigned int virq; |
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while (status) { |
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hwirq = __ffs(status); |
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virq = irq_find_mapping(dom, base + hwirq); |
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if (virq) |
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generic_handle_irq(virq); |
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status &= ~BIT(hwirq); |
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} |
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} |
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static void tangox_irq_handler(struct irq_desc *desc) |
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{ |
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struct irq_domain *dom = irq_desc_get_handler_data(desc); |
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struct irq_chip *host_chip = irq_desc_get_chip(desc); |
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struct tangox_irq_chip *chip = dom->host_data; |
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unsigned int status_lo, status_hi; |
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chained_irq_enter(host_chip, desc); |
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status_lo = intc_readl(chip, chip->ctl + IRQ_STATUS); |
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status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS); |
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tangox_dispatch_irqs(dom, status_lo, 0); |
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tangox_dispatch_irqs(dom, status_hi, 32); |
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chained_irq_exit(host_chip, desc); |
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} |
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static int tangox_irq_set_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct tangox_irq_chip *chip = gc->domain->host_data; |
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struct irq_chip_regs *regs = &gc->chip_types[0].regs; |
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switch (flow_type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_EDGE_RISING: |
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intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask); |
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intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask); |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask); |
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intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask); |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask); |
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intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask); |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask); |
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intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask); |
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break; |
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default: |
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pr_err("Invalid trigger mode %x for IRQ %d\n", |
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flow_type, d->irq); |
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return -EINVAL; |
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} |
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return irq_setup_alt_chip(d, flow_type); |
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} |
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static void __init tangox_irq_init_chip(struct irq_chip_generic *gc, |
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unsigned long ctl_offs, |
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unsigned long edge_offs) |
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{ |
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struct tangox_irq_chip *chip = gc->domain->host_data; |
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struct irq_chip_type *ct = gc->chip_types; |
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unsigned long ctl_base = chip->ctl + ctl_offs; |
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unsigned long edge_base = EDGE_CTL_BASE + edge_offs; |
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int i; |
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gc->reg_base = chip->base; |
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gc->unused = 0; |
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for (i = 0; i < 2; i++) { |
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ct[i].chip.irq_ack = irq_gc_ack_set_bit; |
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ct[i].chip.irq_mask = irq_gc_mask_disable_reg; |
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ct[i].chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set; |
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ct[i].chip.irq_unmask = irq_gc_unmask_enable_reg; |
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ct[i].chip.irq_set_type = tangox_irq_set_type; |
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ct[i].chip.name = gc->domain->name; |
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ct[i].regs.enable = ctl_base + IRQ_EN_SET; |
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ct[i].regs.disable = ctl_base + IRQ_EN_CLR; |
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ct[i].regs.ack = edge_base + EDGE_RAWSTAT; |
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ct[i].regs.type = edge_base; |
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} |
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ct[0].type = IRQ_TYPE_LEVEL_MASK; |
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ct[0].handler = handle_level_irq; |
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ct[1].type = IRQ_TYPE_EDGE_BOTH; |
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ct[1].handler = handle_edge_irq; |
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intc_writel(chip, ct->regs.disable, 0xffffffff); |
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intc_writel(chip, ct->regs.ack, 0xffffffff); |
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} |
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static void __init tangox_irq_domain_init(struct irq_domain *dom) |
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{ |
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struct irq_chip_generic *gc; |
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int i; |
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for (i = 0; i < 2; i++) { |
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gc = irq_get_domain_generic_chip(dom, i * 32); |
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tangox_irq_init_chip(gc, i * IRQ_CTL_HI, i * EDGE_CTL_HI); |
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} |
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} |
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static int __init tangox_irq_init(void __iomem *base, struct resource *baseres, |
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struct device_node *node) |
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{ |
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struct tangox_irq_chip *chip; |
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struct irq_domain *dom; |
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struct resource res; |
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int irq; |
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int err; |
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irq = irq_of_parse_and_map(node, 0); |
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if (!irq) |
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panic("%pOFn: failed to get IRQ", node); |
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err = of_address_to_resource(node, 0, &res); |
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if (err) |
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panic("%pOFn: failed to get address", node); |
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chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
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chip->ctl = res.start - baseres->start; |
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chip->base = base; |
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dom = irq_domain_add_linear(node, 64, &irq_generic_chip_ops, chip); |
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if (!dom) |
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panic("%pOFn: failed to create irqdomain", node); |
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err = irq_alloc_domain_generic_chips(dom, 32, 2, node->name, |
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handle_level_irq, 0, 0, 0); |
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if (err) |
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panic("%pOFn: failed to allocate irqchip", node); |
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tangox_irq_domain_init(dom); |
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irq_set_chained_handler_and_data(irq, tangox_irq_handler, dom); |
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return 0; |
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} |
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static int __init tangox_of_irq_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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struct device_node *c; |
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struct resource res; |
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void __iomem *base; |
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base = of_iomap(node, 0); |
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if (!base) |
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panic("%pOFn: of_iomap failed", node); |
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of_address_to_resource(node, 0, &res); |
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for_each_child_of_node(node, c) |
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tangox_irq_init(base, &res, c); |
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return 0; |
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} |
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IRQCHIP_DECLARE(tangox_intc, "sigma,smp8642-intc", tangox_of_irq_init);
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