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104 lines
2.7 KiB
104 lines
2.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2017, HiSilicon. All rights reserved. |
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*/ |
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#ifndef UFS_HISI_H_ |
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#define UFS_HISI_H_ |
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#define HBRN8_POLL_TOUT_MS 1000 |
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/* |
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* ufs sysctrl specific define |
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*/ |
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#define PSW_POWER_CTRL (0x04) |
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#define PHY_ISO_EN (0x08) |
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#define HC_LP_CTRL (0x0C) |
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#define PHY_CLK_CTRL (0x10) |
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#define PSW_CLK_CTRL (0x14) |
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#define CLOCK_GATE_BYPASS (0x18) |
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#define RESET_CTRL_EN (0x1C) |
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#define UFS_SYSCTRL (0x5C) |
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#define UFS_DEVICE_RESET_CTRL (0x60) |
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#define BIT_UFS_PSW_ISO_CTRL (1 << 16) |
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#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) |
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#define BIT_UFS_REFCLK_ISO_EN (1 << 16) |
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#define BIT_UFS_PHY_ISO_CTRL (1 << 0) |
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#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) |
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#define BIT_SYSCTRL_PWR_READY (1 << 8) |
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#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) |
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#define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) |
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#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) |
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#define UFS_FREQ_CFG_CLK (0x39) |
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#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) |
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#define MASK_UFS_CLK_GATE_BYPASS (0x3F) |
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#define BIT_SYSCTRL_LP_RESET_N (1 << 0) |
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#define BIT_UFS_REFCLK_SRC_SEl (1 << 0) |
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#define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) |
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#define MASK_UFS_DEVICE_RESET (0x1 << 16) |
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#define BIT_UFS_DEVICE_RESET (0x1) |
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/* |
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* M-TX Configuration Attributes for Hixxxx |
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*/ |
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#define MPHY_TX_FSM_STATE 0x41 |
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#define TX_FSM_HIBERN8 0x1 |
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/* |
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* Hixxxx UFS HC specific Registers |
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*/ |
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enum { |
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UFS_REG_OCPTHRTL = 0xc0, |
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UFS_REG_OOCPR = 0xc4, |
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UFS_REG_CDACFG = 0xd0, |
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UFS_REG_CDATX1 = 0xd4, |
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UFS_REG_CDATX2 = 0xd8, |
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UFS_REG_CDARX1 = 0xdc, |
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UFS_REG_CDARX2 = 0xe0, |
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UFS_REG_CDASTA = 0xe4, |
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UFS_REG_LBMCFG = 0xf0, |
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UFS_REG_LBMSTA = 0xf4, |
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UFS_REG_UFSMODE = 0xf8, |
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UFS_REG_HCLKDIV = 0xfc, |
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}; |
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/* AHIT - Auto-Hibernate Idle Timer */ |
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#define UFS_AHIT_AH8ITV_MASK 0x3FF |
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/* REG UFS_REG_OCPTHRTL definition */ |
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#define UFS_HCLKDIV_NORMAL_VALUE 0xE4 |
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/* vendor specific pre-defined parameters */ |
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#define SLOW 1 |
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#define FAST 2 |
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#define UFS_HISI_CAP_RESERVED BIT(0) |
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#define UFS_HISI_CAP_PHY10nm BIT(1) |
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struct ufs_hisi_host { |
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struct ufs_hba *hba; |
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void __iomem *ufs_sys_ctrl; |
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struct reset_control *rst; |
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uint64_t caps; |
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bool in_suspend; |
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}; |
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#define ufs_sys_ctrl_writel(host, val, reg) \ |
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writel((val), (host)->ufs_sys_ctrl + (reg)) |
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#define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) |
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#define ufs_sys_ctrl_set_bits(host, mask, reg) \ |
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ufs_sys_ctrl_writel( \ |
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(host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) |
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#define ufs_sys_ctrl_clr_bits(host, mask, reg) \ |
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ufs_sys_ctrl_writel((host), \ |
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((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ |
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(reg)) |
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#endif /* UFS_HISI_H_ */
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