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639 lines
18 KiB
639 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/**************************************************************************** |
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* Driver for Solarflare network controllers and boards |
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* Copyright 2005-2006 Fen Systems Ltd. |
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* Copyright 2005-2013 Solarflare Communications Inc. |
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*/ |
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|
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#include <linux/pci.h> |
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#include <linux/tcp.h> |
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#include <linux/ip.h> |
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#include <linux/in.h> |
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#include <linux/ipv6.h> |
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#include <linux/slab.h> |
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#include <net/ipv6.h> |
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#include <linux/if_ether.h> |
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#include <linux/highmem.h> |
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#include <linux/cache.h> |
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#include "net_driver.h" |
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#include "efx.h" |
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#include "io.h" |
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#include "nic.h" |
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#include "tx.h" |
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#include "tx_common.h" |
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#include "workarounds.h" |
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#include "ef10_regs.h" |
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#ifdef EFX_USE_PIO |
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#define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES) |
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unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF; |
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#endif /* EFX_USE_PIO */ |
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static inline u8 *efx_tx_get_copy_buffer(struct efx_tx_queue *tx_queue, |
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struct efx_tx_buffer *buffer) |
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{ |
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unsigned int index = efx_tx_queue_get_insert_index(tx_queue); |
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struct efx_buffer *page_buf = |
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&tx_queue->cb_page[index >> (PAGE_SHIFT - EFX_TX_CB_ORDER)]; |
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unsigned int offset = |
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((index << EFX_TX_CB_ORDER) + NET_IP_ALIGN) & (PAGE_SIZE - 1); |
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|
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if (unlikely(!page_buf->addr) && |
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efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE, |
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GFP_ATOMIC)) |
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return NULL; |
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buffer->dma_addr = page_buf->dma_addr + offset; |
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buffer->unmap_len = 0; |
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return (u8 *)page_buf->addr + offset; |
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} |
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u8 *efx_tx_get_copy_buffer_limited(struct efx_tx_queue *tx_queue, |
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struct efx_tx_buffer *buffer, size_t len) |
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{ |
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if (len > EFX_TX_CB_SIZE) |
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return NULL; |
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return efx_tx_get_copy_buffer(tx_queue, buffer); |
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} |
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static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1) |
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{ |
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/* We need to consider all queues that the net core sees as one */ |
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struct efx_nic *efx = txq1->efx; |
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struct efx_tx_queue *txq2; |
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unsigned int fill_level; |
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fill_level = efx_channel_tx_old_fill_level(txq1->channel); |
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if (likely(fill_level < efx->txq_stop_thresh)) |
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return; |
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/* We used the stale old_read_count above, which gives us a |
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* pessimistic estimate of the fill level (which may even |
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* validly be >= efx->txq_entries). Now try again using |
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* read_count (more likely to be a cache miss). |
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* |
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* If we read read_count and then conditionally stop the |
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* queue, it is possible for the completion path to race with |
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* us and complete all outstanding descriptors in the middle, |
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* after which there will be no more completions to wake it. |
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* Therefore we stop the queue first, then read read_count |
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* (with a memory barrier to ensure the ordering), then |
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* restart the queue if the fill level turns out to be low |
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* enough. |
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*/ |
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netif_tx_stop_queue(txq1->core_txq); |
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smp_mb(); |
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efx_for_each_channel_tx_queue(txq2, txq1->channel) |
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txq2->old_read_count = READ_ONCE(txq2->read_count); |
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fill_level = efx_channel_tx_old_fill_level(txq1->channel); |
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EFX_WARN_ON_ONCE_PARANOID(fill_level >= efx->txq_entries); |
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if (likely(fill_level < efx->txq_stop_thresh)) { |
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smp_mb(); |
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if (likely(!efx->loopback_selftest)) |
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netif_tx_start_queue(txq1->core_txq); |
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} |
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} |
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static int efx_enqueue_skb_copy(struct efx_tx_queue *tx_queue, |
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struct sk_buff *skb) |
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{ |
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unsigned int copy_len = skb->len; |
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struct efx_tx_buffer *buffer; |
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u8 *copy_buffer; |
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int rc; |
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EFX_WARN_ON_ONCE_PARANOID(copy_len > EFX_TX_CB_SIZE); |
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buffer = efx_tx_queue_get_insert_buffer(tx_queue); |
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copy_buffer = efx_tx_get_copy_buffer(tx_queue, buffer); |
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if (unlikely(!copy_buffer)) |
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return -ENOMEM; |
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rc = skb_copy_bits(skb, 0, copy_buffer, copy_len); |
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EFX_WARN_ON_PARANOID(rc); |
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buffer->len = copy_len; |
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buffer->skb = skb; |
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buffer->flags = EFX_TX_BUF_SKB; |
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++tx_queue->insert_count; |
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return rc; |
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} |
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#ifdef EFX_USE_PIO |
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struct efx_short_copy_buffer { |
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int used; |
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u8 buf[L1_CACHE_BYTES]; |
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}; |
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/* Copy to PIO, respecting that writes to PIO buffers must be dword aligned. |
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* Advances piobuf pointer. Leaves additional data in the copy buffer. |
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*/ |
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static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf, |
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u8 *data, int len, |
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struct efx_short_copy_buffer *copy_buf) |
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{ |
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int block_len = len & ~(sizeof(copy_buf->buf) - 1); |
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__iowrite64_copy(*piobuf, data, block_len >> 3); |
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*piobuf += block_len; |
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len -= block_len; |
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if (len) { |
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data += block_len; |
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BUG_ON(copy_buf->used); |
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BUG_ON(len > sizeof(copy_buf->buf)); |
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memcpy(copy_buf->buf, data, len); |
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copy_buf->used = len; |
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} |
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} |
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/* Copy to PIO, respecting dword alignment, popping data from copy buffer first. |
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* Advances piobuf pointer. Leaves additional data in the copy buffer. |
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*/ |
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static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf, |
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u8 *data, int len, |
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struct efx_short_copy_buffer *copy_buf) |
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{ |
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if (copy_buf->used) { |
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/* if the copy buffer is partially full, fill it up and write */ |
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int copy_to_buf = |
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min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len); |
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memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf); |
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copy_buf->used += copy_to_buf; |
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/* if we didn't fill it up then we're done for now */ |
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if (copy_buf->used < sizeof(copy_buf->buf)) |
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return; |
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__iowrite64_copy(*piobuf, copy_buf->buf, |
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sizeof(copy_buf->buf) >> 3); |
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*piobuf += sizeof(copy_buf->buf); |
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data += copy_to_buf; |
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len -= copy_to_buf; |
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copy_buf->used = 0; |
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} |
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efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf); |
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} |
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static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf, |
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struct efx_short_copy_buffer *copy_buf) |
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{ |
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/* if there's anything in it, write the whole buffer, including junk */ |
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if (copy_buf->used) |
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__iowrite64_copy(piobuf, copy_buf->buf, |
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sizeof(copy_buf->buf) >> 3); |
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} |
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/* Traverse skb structure and copy fragments in to PIO buffer. |
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* Advances piobuf pointer. |
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*/ |
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static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb, |
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u8 __iomem **piobuf, |
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struct efx_short_copy_buffer *copy_buf) |
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{ |
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int i; |
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efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb), |
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copy_buf); |
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for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) { |
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skb_frag_t *f = &skb_shinfo(skb)->frags[i]; |
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u8 *vaddr; |
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vaddr = kmap_atomic(skb_frag_page(f)); |
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efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + skb_frag_off(f), |
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skb_frag_size(f), copy_buf); |
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kunmap_atomic(vaddr); |
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} |
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EFX_WARN_ON_ONCE_PARANOID(skb_shinfo(skb)->frag_list); |
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} |
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static int efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, |
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struct sk_buff *skb) |
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{ |
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struct efx_tx_buffer *buffer = |
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efx_tx_queue_get_insert_buffer(tx_queue); |
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u8 __iomem *piobuf = tx_queue->piobuf; |
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/* Copy to PIO buffer. Ensure the writes are padded to the end |
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* of a cache line, as this is required for write-combining to be |
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* effective on at least x86. |
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*/ |
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if (skb_shinfo(skb)->nr_frags) { |
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/* The size of the copy buffer will ensure all writes |
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* are the size of a cache line. |
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*/ |
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struct efx_short_copy_buffer copy_buf; |
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copy_buf.used = 0; |
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efx_skb_copy_bits_to_pio(tx_queue->efx, skb, |
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&piobuf, ©_buf); |
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efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf); |
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} else { |
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/* Pad the write to the size of a cache line. |
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* We can do this because we know the skb_shared_info struct is |
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* after the source, and the destination buffer is big enough. |
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*/ |
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BUILD_BUG_ON(L1_CACHE_BYTES > |
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); |
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__iowrite64_copy(tx_queue->piobuf, skb->data, |
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ALIGN(skb->len, L1_CACHE_BYTES) >> 3); |
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} |
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buffer->skb = skb; |
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buffer->flags = EFX_TX_BUF_SKB | EFX_TX_BUF_OPTION; |
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EFX_POPULATE_QWORD_5(buffer->option, |
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ESF_DZ_TX_DESC_IS_OPT, 1, |
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ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO, |
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ESF_DZ_TX_PIO_CONT, 0, |
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ESF_DZ_TX_PIO_BYTE_CNT, skb->len, |
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ESF_DZ_TX_PIO_BUF_ADDR, |
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tx_queue->piobuf_offset); |
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++tx_queue->insert_count; |
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return 0; |
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} |
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/* Decide whether we can use TX PIO, ie. write packet data directly into |
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* a buffer on the device. This can reduce latency at the expense of |
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* throughput, so we only do this if both hardware and software TX rings |
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* are empty, including all queues for the channel. This also ensures that |
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* only one packet at a time can be using the PIO buffer. If the xmit_more |
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* flag is set then we don't use this - there'll be another packet along |
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* shortly and we want to hold off the doorbell. |
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*/ |
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static bool efx_tx_may_pio(struct efx_tx_queue *tx_queue) |
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{ |
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struct efx_channel *channel = tx_queue->channel; |
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if (!tx_queue->piobuf) |
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return false; |
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EFX_WARN_ON_ONCE_PARANOID(!channel->efx->type->option_descriptors); |
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efx_for_each_channel_tx_queue(tx_queue, channel) |
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if (!efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count)) |
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return false; |
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return true; |
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} |
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#endif /* EFX_USE_PIO */ |
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/* Send any pending traffic for a channel. xmit_more is shared across all |
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* queues for a channel, so we must check all of them. |
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*/ |
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static void efx_tx_send_pending(struct efx_channel *channel) |
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{ |
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struct efx_tx_queue *q; |
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efx_for_each_channel_tx_queue(q, channel) { |
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if (q->xmit_pending) |
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efx_nic_push_buffers(q); |
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} |
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} |
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/* |
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* Add a socket buffer to a TX queue |
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* |
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* This maps all fragments of a socket buffer for DMA and adds them to |
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* the TX queue. The queue's insert pointer will be incremented by |
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* the number of fragments in the socket buffer. |
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* |
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* If any DMA mapping fails, any mapped fragments will be unmapped, |
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* the queue's insert pointer will be restored to its original value. |
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* |
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* This function is split out from efx_hard_start_xmit to allow the |
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* loopback test to direct packets via specific TX queues. |
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* |
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* Returns NETDEV_TX_OK. |
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* You must hold netif_tx_lock() to call this function. |
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*/ |
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netdev_tx_t __efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) |
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{ |
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unsigned int old_insert_count = tx_queue->insert_count; |
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bool xmit_more = netdev_xmit_more(); |
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bool data_mapped = false; |
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unsigned int segments; |
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unsigned int skb_len; |
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int rc; |
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skb_len = skb->len; |
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segments = skb_is_gso(skb) ? skb_shinfo(skb)->gso_segs : 0; |
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if (segments == 1) |
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segments = 0; /* Don't use TSO for a single segment. */ |
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/* Handle TSO first - it's *possible* (although unlikely) that we might |
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* be passed a packet to segment that's smaller than the copybreak/PIO |
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* size limit. |
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*/ |
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if (segments) { |
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switch (tx_queue->tso_version) { |
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case 1: |
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rc = efx_enqueue_skb_tso(tx_queue, skb, &data_mapped); |
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break; |
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case 2: |
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rc = efx_ef10_tx_tso_desc(tx_queue, skb, &data_mapped); |
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break; |
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case 0: /* No TSO on this queue, SW fallback needed */ |
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default: |
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rc = -EINVAL; |
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break; |
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} |
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if (rc == -EINVAL) { |
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rc = efx_tx_tso_fallback(tx_queue, skb); |
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tx_queue->tso_fallbacks++; |
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if (rc == 0) |
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return 0; |
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} |
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if (rc) |
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goto err; |
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#ifdef EFX_USE_PIO |
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} else if (skb_len <= efx_piobuf_size && !xmit_more && |
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efx_tx_may_pio(tx_queue)) { |
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/* Use PIO for short packets with an empty queue. */ |
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if (efx_enqueue_skb_pio(tx_queue, skb)) |
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goto err; |
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tx_queue->pio_packets++; |
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data_mapped = true; |
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#endif |
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} else if (skb->data_len && skb_len <= EFX_TX_CB_SIZE) { |
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/* Pad short packets or coalesce short fragmented packets. */ |
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if (efx_enqueue_skb_copy(tx_queue, skb)) |
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goto err; |
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tx_queue->cb_packets++; |
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data_mapped = true; |
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} |
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/* Map for DMA and create descriptors if we haven't done so already. */ |
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if (!data_mapped && (efx_tx_map_data(tx_queue, skb, segments))) |
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goto err; |
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efx_tx_maybe_stop_queue(tx_queue); |
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tx_queue->xmit_pending = true; |
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/* Pass off to hardware */ |
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if (__netdev_tx_sent_queue(tx_queue->core_txq, skb_len, xmit_more)) |
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efx_tx_send_pending(tx_queue->channel); |
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if (segments) { |
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tx_queue->tso_bursts++; |
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tx_queue->tso_packets += segments; |
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tx_queue->tx_packets += segments; |
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} else { |
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tx_queue->tx_packets++; |
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} |
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return NETDEV_TX_OK; |
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err: |
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efx_enqueue_unwind(tx_queue, old_insert_count); |
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dev_kfree_skb_any(skb); |
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/* If we're not expecting another transmit and we had something to push |
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* on this queue or a partner queue then we need to push here to get the |
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* previous packets out. |
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*/ |
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if (!xmit_more) |
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efx_tx_send_pending(tx_queue->channel); |
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return NETDEV_TX_OK; |
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} |
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/* Transmit a packet from an XDP buffer |
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* |
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* Returns number of packets sent on success, error code otherwise. |
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* Runs in NAPI context, either in our poll (for XDP TX) or a different NIC |
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* (for XDP redirect). |
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*/ |
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int efx_xdp_tx_buffers(struct efx_nic *efx, int n, struct xdp_frame **xdpfs, |
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bool flush) |
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{ |
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struct efx_tx_buffer *tx_buffer; |
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struct efx_tx_queue *tx_queue; |
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struct xdp_frame *xdpf; |
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dma_addr_t dma_addr; |
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unsigned int len; |
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int space; |
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int cpu; |
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int i = 0; |
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if (unlikely(n && !xdpfs)) |
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return -EINVAL; |
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if (unlikely(!n)) |
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return 0; |
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cpu = raw_smp_processor_id(); |
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if (unlikely(cpu >= efx->xdp_tx_queue_count)) |
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return -EINVAL; |
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tx_queue = efx->xdp_tx_queues[cpu]; |
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if (unlikely(!tx_queue)) |
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return -EINVAL; |
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|
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if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED) |
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HARD_TX_LOCK(efx->net_dev, tx_queue->core_txq, cpu); |
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|
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/* If we're borrowing net stack queues we have to handle stop-restart |
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* or we might block the queue and it will be considered as frozen |
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*/ |
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if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) { |
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if (netif_tx_queue_stopped(tx_queue->core_txq)) |
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goto unlock; |
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efx_tx_maybe_stop_queue(tx_queue); |
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} |
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|
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/* Check for available space. We should never need multiple |
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* descriptors per frame. |
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*/ |
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space = efx->txq_entries + |
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tx_queue->read_count - tx_queue->insert_count; |
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for (i = 0; i < n; i++) { |
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xdpf = xdpfs[i]; |
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|
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if (i >= space) |
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break; |
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|
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/* We'll want a descriptor for this tx. */ |
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prefetchw(__efx_tx_queue_get_insert_buffer(tx_queue)); |
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|
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len = xdpf->len; |
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|
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/* Map for DMA. */ |
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dma_addr = dma_map_single(&efx->pci_dev->dev, |
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xdpf->data, len, |
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DMA_TO_DEVICE); |
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if (dma_mapping_error(&efx->pci_dev->dev, dma_addr)) |
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break; |
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|
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/* Create descriptor and set up for unmapping DMA. */ |
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tx_buffer = efx_tx_map_chunk(tx_queue, dma_addr, len); |
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tx_buffer->xdpf = xdpf; |
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tx_buffer->flags = EFX_TX_BUF_XDP | |
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EFX_TX_BUF_MAP_SINGLE; |
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tx_buffer->dma_offset = 0; |
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tx_buffer->unmap_len = len; |
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tx_queue->tx_packets++; |
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} |
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|
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/* Pass mapped frames to hardware. */ |
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if (flush && i > 0) |
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efx_nic_push_buffers(tx_queue); |
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|
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unlock: |
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if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED) |
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HARD_TX_UNLOCK(efx->net_dev, tx_queue->core_txq); |
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|
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return i == 0 ? -EIO : i; |
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} |
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|
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/* Initiate a packet transmission. We use one channel per CPU |
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* (sharing when we have more CPUs than channels). |
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* |
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* Context: non-blocking. |
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* Should always return NETDEV_TX_OK and consume the skb. |
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*/ |
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netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
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struct net_device *net_dev) |
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{ |
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struct efx_nic *efx = netdev_priv(net_dev); |
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struct efx_tx_queue *tx_queue; |
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unsigned index, type; |
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|
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EFX_WARN_ON_PARANOID(!netif_device_present(net_dev)); |
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|
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index = skb_get_queue_mapping(skb); |
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type = efx_tx_csum_type_skb(skb); |
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if (index >= efx->n_tx_channels) { |
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index -= efx->n_tx_channels; |
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type |= EFX_TXQ_TYPE_HIGHPRI; |
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} |
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|
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/* PTP "event" packet */ |
|
if (unlikely(efx_xmit_with_hwtstamp(skb)) && |
|
unlikely(efx_ptp_is_ptp_tx(efx, skb))) { |
|
/* There may be existing transmits on the channel that are |
|
* waiting for this packet to trigger the doorbell write. |
|
* We need to send the packets at this point. |
|
*/ |
|
efx_tx_send_pending(efx_get_tx_channel(efx, index)); |
|
return efx_ptp_tx(efx, skb); |
|
} |
|
|
|
tx_queue = efx_get_tx_queue(efx, index, type); |
|
if (WARN_ON_ONCE(!tx_queue)) { |
|
/* We don't have a TXQ of the right type. |
|
* This should never happen, as we don't advertise offload |
|
* features unless we can support them. |
|
*/ |
|
dev_kfree_skb_any(skb); |
|
/* If we're not expecting another transmit and we had something to push |
|
* on this queue or a partner queue then we need to push here to get the |
|
* previous packets out. |
|
*/ |
|
if (!netdev_xmit_more()) |
|
efx_tx_send_pending(tx_queue->channel); |
|
return NETDEV_TX_OK; |
|
} |
|
|
|
return __efx_enqueue_skb(tx_queue, skb); |
|
} |
|
|
|
void efx_xmit_done_single(struct efx_tx_queue *tx_queue) |
|
{ |
|
unsigned int pkts_compl = 0, bytes_compl = 0; |
|
unsigned int read_ptr; |
|
bool finished = false; |
|
|
|
read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
|
|
|
while (!finished) { |
|
struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; |
|
|
|
if (!efx_tx_buffer_in_use(buffer)) { |
|
struct efx_nic *efx = tx_queue->efx; |
|
|
|
netif_err(efx, hw, efx->net_dev, |
|
"TX queue %d spurious single TX completion\n", |
|
tx_queue->queue); |
|
efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); |
|
return; |
|
} |
|
|
|
/* Need to check the flag before dequeueing. */ |
|
if (buffer->flags & EFX_TX_BUF_SKB) |
|
finished = true; |
|
efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
|
|
|
++tx_queue->read_count; |
|
read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
|
} |
|
|
|
tx_queue->pkts_compl += pkts_compl; |
|
tx_queue->bytes_compl += bytes_compl; |
|
|
|
EFX_WARN_ON_PARANOID(pkts_compl != 1); |
|
|
|
efx_xmit_done_check_empty(tx_queue); |
|
} |
|
|
|
void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) |
|
{ |
|
struct efx_nic *efx = tx_queue->efx; |
|
|
|
/* Must be inverse of queue lookup in efx_hard_start_xmit() */ |
|
tx_queue->core_txq = |
|
netdev_get_tx_queue(efx->net_dev, |
|
tx_queue->channel->channel + |
|
((tx_queue->type & EFX_TXQ_TYPE_HIGHPRI) ? |
|
efx->n_tx_channels : 0)); |
|
} |
|
|
|
int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type, |
|
void *type_data) |
|
{ |
|
struct efx_nic *efx = netdev_priv(net_dev); |
|
struct tc_mqprio_qopt *mqprio = type_data; |
|
unsigned tc, num_tc; |
|
|
|
if (type != TC_SETUP_QDISC_MQPRIO) |
|
return -EOPNOTSUPP; |
|
|
|
/* Only Siena supported highpri queues */ |
|
if (efx_nic_rev(efx) > EFX_REV_SIENA_A0) |
|
return -EOPNOTSUPP; |
|
|
|
num_tc = mqprio->num_tc; |
|
|
|
if (num_tc > EFX_MAX_TX_TC) |
|
return -EINVAL; |
|
|
|
mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
|
|
|
if (num_tc == net_dev->num_tc) |
|
return 0; |
|
|
|
for (tc = 0; tc < num_tc; tc++) { |
|
net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels; |
|
net_dev->tc_to_txq[tc].count = efx->n_tx_channels; |
|
} |
|
|
|
net_dev->num_tc = num_tc; |
|
|
|
return netif_set_real_num_tx_queues(net_dev, |
|
max_t(int, num_tc, 1) * |
|
efx->n_tx_channels); |
|
}
|
|
|