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583 lines
15 KiB
583 lines
15 KiB
/* |
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* FCC driver for Motorola MPC82xx (PQ2). |
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* |
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* Copyright (c) 2003 Intracom S.A. |
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* by Pantelis Antoniou <[email protected]> |
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* |
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* 2005 (c) MontaVista Software, Inc. |
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* Vitaly Bordug <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/string.h> |
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#include <linux/ptrace.h> |
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#include <linux/errno.h> |
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#include <linux/ioport.h> |
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#include <linux/interrupt.h> |
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#include <linux/delay.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/skbuff.h> |
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#include <linux/spinlock.h> |
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#include <linux/mii.h> |
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#include <linux/ethtool.h> |
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#include <linux/bitops.h> |
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#include <linux/fs.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_irq.h> |
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#include <linux/gfp.h> |
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#include <linux/pgtable.h> |
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|
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#include <asm/immap_cpm2.h> |
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#include <asm/mpc8260.h> |
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#include <asm/cpm2.h> |
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|
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#include <asm/irq.h> |
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#include <linux/uaccess.h> |
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|
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#include "fs_enet.h" |
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|
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/*************************************************/ |
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|
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/* FCC access macros */ |
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|
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/* write, read, set bits, clear bits */ |
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#define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v)) |
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#define R32(_p, _m) in_be32(&(_p)->_m) |
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#define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) |
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#define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) |
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|
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#define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v)) |
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#define R16(_p, _m) in_be16(&(_p)->_m) |
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#define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) |
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#define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) |
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|
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#define W8(_p, _m, _v) out_8(&(_p)->_m, (_v)) |
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#define R8(_p, _m) in_8(&(_p)->_m) |
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#define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) |
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#define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) |
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|
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/*************************************************/ |
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|
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#define FCC_MAX_MULTICAST_ADDRS 64 |
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|
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#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) |
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#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) |
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#define mk_mii_end 0 |
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|
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#define MAX_CR_CMD_LOOPS 10000 |
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|
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static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op) |
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{ |
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const struct fs_platform_info *fpi = fep->fpi; |
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|
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return cpm_command(fpi->cp_command, op); |
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} |
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|
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static int do_pd_setup(struct fs_enet_private *fep) |
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{ |
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struct platform_device *ofdev = to_platform_device(fep->dev); |
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struct fs_platform_info *fpi = fep->fpi; |
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int ret = -EINVAL; |
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|
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fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); |
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if (!fep->interrupt) |
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goto out; |
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|
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fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0); |
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if (!fep->fcc.fccp) |
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goto out; |
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|
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fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1); |
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if (!fep->fcc.ep) |
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goto out_fccp; |
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|
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fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2); |
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if (!fep->fcc.fcccp) |
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goto out_ep; |
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|
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fep->fcc.mem = (void __iomem *)cpm2_immr; |
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fpi->dpram_offset = cpm_dpalloc(128, 32); |
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if (IS_ERR_VALUE(fpi->dpram_offset)) { |
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ret = fpi->dpram_offset; |
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goto out_fcccp; |
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} |
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return 0; |
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|
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out_fcccp: |
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iounmap(fep->fcc.fcccp); |
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out_ep: |
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iounmap(fep->fcc.ep); |
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out_fccp: |
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iounmap(fep->fcc.fccp); |
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out: |
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return ret; |
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} |
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|
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#define FCC_NAPI_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB | FCC_ENET_TXB) |
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#define FCC_EVENT (FCC_ENET_RXF | FCC_ENET_TXB) |
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#define FCC_ERR_EVENT_MSK (FCC_ENET_TXE) |
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|
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static int setup_data(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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if (do_pd_setup(fep) != 0) |
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return -EINVAL; |
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fep->ev_napi = FCC_NAPI_EVENT_MSK; |
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fep->ev = FCC_EVENT; |
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fep->ev_err = FCC_ERR_EVENT_MSK; |
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return 0; |
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} |
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|
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static int allocate_bd(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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const struct fs_platform_info *fpi = fep->fpi; |
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|
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fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev, |
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(fpi->tx_ring + fpi->rx_ring) * |
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sizeof(cbd_t), &fep->ring_mem_addr, |
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GFP_KERNEL); |
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if (fep->ring_base == NULL) |
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return -ENOMEM; |
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|
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return 0; |
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} |
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static void free_bd(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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const struct fs_platform_info *fpi = fep->fpi; |
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|
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if (fep->ring_base) |
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dma_free_coherent(fep->dev, |
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(fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t), |
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(void __force *)fep->ring_base, fep->ring_mem_addr); |
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} |
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static void cleanup_data(struct net_device *dev) |
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{ |
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/* nothing */ |
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} |
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static void set_promiscuous_mode(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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fcc_t __iomem *fccp = fep->fcc.fccp; |
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|
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S32(fccp, fcc_fpsmr, FCC_PSMR_PRO); |
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} |
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|
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static void set_multicast_start(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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fcc_enet_t __iomem *ep = fep->fcc.ep; |
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|
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W32(ep, fen_gaddrh, 0); |
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W32(ep, fen_gaddrl, 0); |
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} |
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static void set_multicast_one(struct net_device *dev, const u8 *mac) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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fcc_enet_t __iomem *ep = fep->fcc.ep; |
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u16 taddrh, taddrm, taddrl; |
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taddrh = ((u16)mac[5] << 8) | mac[4]; |
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taddrm = ((u16)mac[3] << 8) | mac[2]; |
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taddrl = ((u16)mac[1] << 8) | mac[0]; |
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W16(ep, fen_taddrh, taddrh); |
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W16(ep, fen_taddrm, taddrm); |
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W16(ep, fen_taddrl, taddrl); |
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fcc_cr_cmd(fep, CPM_CR_SET_GADDR); |
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} |
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static void set_multicast_finish(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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fcc_t __iomem *fccp = fep->fcc.fccp; |
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fcc_enet_t __iomem *ep = fep->fcc.ep; |
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|
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/* clear promiscuous always */ |
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C32(fccp, fcc_fpsmr, FCC_PSMR_PRO); |
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|
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/* if all multi or too many multicasts; just enable all */ |
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if ((dev->flags & IFF_ALLMULTI) != 0 || |
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netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) { |
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|
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W32(ep, fen_gaddrh, 0xffffffff); |
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W32(ep, fen_gaddrl, 0xffffffff); |
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} |
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/* read back */ |
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fep->fcc.gaddrh = R32(ep, fen_gaddrh); |
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fep->fcc.gaddrl = R32(ep, fen_gaddrl); |
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} |
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static void set_multicast_list(struct net_device *dev) |
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{ |
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struct netdev_hw_addr *ha; |
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if ((dev->flags & IFF_PROMISC) == 0) { |
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set_multicast_start(dev); |
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netdev_for_each_mc_addr(ha, dev) |
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set_multicast_one(dev, ha->addr); |
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set_multicast_finish(dev); |
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} else |
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set_promiscuous_mode(dev); |
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} |
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static void restart(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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const struct fs_platform_info *fpi = fep->fpi; |
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fcc_t __iomem *fccp = fep->fcc.fccp; |
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fcc_c_t __iomem *fcccp = fep->fcc.fcccp; |
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fcc_enet_t __iomem *ep = fep->fcc.ep; |
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dma_addr_t rx_bd_base_phys, tx_bd_base_phys; |
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u16 paddrh, paddrm, paddrl; |
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const unsigned char *mac; |
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int i; |
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C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); |
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/* clear everything (slow & steady does it) */ |
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for (i = 0; i < sizeof(*ep); i++) |
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out_8((u8 __iomem *)ep + i, 0); |
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/* get physical address */ |
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rx_bd_base_phys = fep->ring_mem_addr; |
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tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; |
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/* point to bds */ |
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W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); |
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W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); |
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/* Set maximum bytes per receive buffer. |
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* It must be a multiple of 32. |
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*/ |
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W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); |
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W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); |
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W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); |
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|
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/* Allocate space in the reserved FCC area of DPRAM for the |
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* internal buffers. No one uses this space (yet), so we |
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* can do this. Later, we will add resource management for |
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* this area. |
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*/ |
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W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset); |
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W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32); |
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W16(ep, fen_padptr, fpi->dpram_offset + 64); |
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/* fill with special symbol... */ |
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memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); |
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W32(ep, fen_genfcc.fcc_rbptr, 0); |
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W32(ep, fen_genfcc.fcc_tbptr, 0); |
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W32(ep, fen_genfcc.fcc_rcrc, 0); |
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W32(ep, fen_genfcc.fcc_tcrc, 0); |
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W16(ep, fen_genfcc.fcc_res1, 0); |
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W32(ep, fen_genfcc.fcc_res2, 0); |
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|
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/* no CAM */ |
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W32(ep, fen_camptr, 0); |
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|
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/* Set CRC preset and mask */ |
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W32(ep, fen_cmask, 0xdebb20e3); |
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W32(ep, fen_cpres, 0xffffffff); |
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|
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W32(ep, fen_crcec, 0); /* CRC Error counter */ |
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W32(ep, fen_alec, 0); /* alignment error counter */ |
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W32(ep, fen_disfc, 0); /* discard frame counter */ |
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W16(ep, fen_retlim, 15); /* Retry limit threshold */ |
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W16(ep, fen_pper, 0); /* Normal persistence */ |
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|
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/* set group address */ |
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W32(ep, fen_gaddrh, fep->fcc.gaddrh); |
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W32(ep, fen_gaddrl, fep->fcc.gaddrh); |
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|
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/* Clear hash filter tables */ |
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W32(ep, fen_iaddrh, 0); |
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W32(ep, fen_iaddrl, 0); |
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|
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/* Clear the Out-of-sequence TxBD */ |
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W16(ep, fen_tfcstat, 0); |
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W16(ep, fen_tfclen, 0); |
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W32(ep, fen_tfcptr, 0); |
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|
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W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ |
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W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ |
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|
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/* set address */ |
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mac = dev->dev_addr; |
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paddrh = ((u16)mac[5] << 8) | mac[4]; |
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paddrm = ((u16)mac[3] << 8) | mac[2]; |
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paddrl = ((u16)mac[1] << 8) | mac[0]; |
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W16(ep, fen_paddrh, paddrh); |
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W16(ep, fen_paddrm, paddrm); |
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W16(ep, fen_paddrl, paddrl); |
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|
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W16(ep, fen_taddrh, 0); |
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W16(ep, fen_taddrm, 0); |
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W16(ep, fen_taddrl, 0); |
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|
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W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ |
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W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ |
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|
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/* Clear stat counters, in case we ever enable RMON */ |
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W32(ep, fen_octc, 0); |
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W32(ep, fen_colc, 0); |
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W32(ep, fen_broc, 0); |
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W32(ep, fen_mulc, 0); |
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W32(ep, fen_uspc, 0); |
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W32(ep, fen_frgc, 0); |
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W32(ep, fen_ospc, 0); |
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W32(ep, fen_jbrc, 0); |
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W32(ep, fen_p64c, 0); |
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W32(ep, fen_p65c, 0); |
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W32(ep, fen_p128c, 0); |
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W32(ep, fen_p256c, 0); |
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W32(ep, fen_p512c, 0); |
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W32(ep, fen_p1024c, 0); |
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|
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W16(ep, fen_rfthr, 0); /* Suggested by manual */ |
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W16(ep, fen_rfcnt, 0); |
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W16(ep, fen_cftype, 0); |
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|
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fs_init_bds(dev); |
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|
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/* adjust to speed (for RMII mode) */ |
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if (fpi->use_rmii) { |
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if (dev->phydev->speed == 100) |
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C8(fcccp, fcc_gfemr, 0x20); |
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else |
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S8(fcccp, fcc_gfemr, 0x20); |
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} |
|
|
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fcc_cr_cmd(fep, CPM_CR_INIT_TRX); |
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|
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/* clear events */ |
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W16(fccp, fcc_fcce, 0xffff); |
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|
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/* Enable interrupts we wish to service */ |
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W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); |
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|
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/* Set GFMR to enable Ethernet operating mode */ |
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W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); |
|
|
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/* set sync/delimiters */ |
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W16(fccp, fcc_fdsr, 0xd555); |
|
|
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W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); |
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|
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if (fpi->use_rmii) |
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S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); |
|
|
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/* adjust to duplex mode */ |
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if (dev->phydev->duplex) |
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S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); |
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else |
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C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); |
|
|
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/* Restore multicast and promiscuous settings */ |
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set_multicast_list(dev); |
|
|
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S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); |
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} |
|
|
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static void stop(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
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/* stop ethernet */ |
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C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); |
|
|
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/* clear events */ |
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W16(fccp, fcc_fcce, 0xffff); |
|
|
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/* clear interrupt mask */ |
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W16(fccp, fcc_fccm, 0); |
|
|
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fs_cleanup_bds(dev); |
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} |
|
|
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static void napi_clear_event_fs(struct net_device *dev) |
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{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
|
fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
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W16(fccp, fcc_fcce, FCC_NAPI_EVENT_MSK); |
|
} |
|
|
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static void napi_enable_fs(struct net_device *dev) |
|
{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
|
fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
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S16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK); |
|
} |
|
|
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static void napi_disable_fs(struct net_device *dev) |
|
{ |
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struct fs_enet_private *fep = netdev_priv(dev); |
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fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
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C16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK); |
|
} |
|
|
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static void rx_bd_done(struct net_device *dev) |
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{ |
|
/* nothing */ |
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} |
|
|
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static void tx_kickstart(struct net_device *dev) |
|
{ |
|
struct fs_enet_private *fep = netdev_priv(dev); |
|
fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
|
S16(fccp, fcc_ftodr, 0x8000); |
|
} |
|
|
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static u32 get_int_events(struct net_device *dev) |
|
{ |
|
struct fs_enet_private *fep = netdev_priv(dev); |
|
fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
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return (u32)R16(fccp, fcc_fcce); |
|
} |
|
|
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static void clear_int_events(struct net_device *dev, u32 int_events) |
|
{ |
|
struct fs_enet_private *fep = netdev_priv(dev); |
|
fcc_t __iomem *fccp = fep->fcc.fccp; |
|
|
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W16(fccp, fcc_fcce, int_events & 0xffff); |
|
} |
|
|
|
static void ev_error(struct net_device *dev, u32 int_events) |
|
{ |
|
struct fs_enet_private *fep = netdev_priv(dev); |
|
|
|
dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events); |
|
} |
|
|
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static int get_regs(struct net_device *dev, void *p, int *sizep) |
|
{ |
|
struct fs_enet_private *fep = netdev_priv(dev); |
|
|
|
if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1) |
|
return -EINVAL; |
|
|
|
memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t)); |
|
p = (char *)p + sizeof(fcc_t); |
|
|
|
memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t)); |
|
p = (char *)p + sizeof(fcc_enet_t); |
|
|
|
memcpy_fromio(p, fep->fcc.fcccp, 1); |
|
return 0; |
|
} |
|
|
|
static int get_regs_len(struct net_device *dev) |
|
{ |
|
return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1; |
|
} |
|
|
|
/* Some transmit errors cause the transmitter to shut |
|
* down. We now issue a restart transmit. |
|
* Also, to workaround 8260 device erratum CPM37, we must |
|
* disable and then re-enable the transmitterfollowing a |
|
* Late Collision, Underrun, or Retry Limit error. |
|
* In addition, tbptr may point beyond BDs beyond still marked |
|
* as ready due to internal pipelining, so we need to look back |
|
* through the BDs and adjust tbptr to point to the last BD |
|
* marked as ready. This may result in some buffers being |
|
* retransmitted. |
|
*/ |
|
static void tx_restart(struct net_device *dev) |
|
{ |
|
struct fs_enet_private *fep = netdev_priv(dev); |
|
fcc_t __iomem *fccp = fep->fcc.fccp; |
|
const struct fs_platform_info *fpi = fep->fpi; |
|
fcc_enet_t __iomem *ep = fep->fcc.ep; |
|
cbd_t __iomem *curr_tbptr; |
|
cbd_t __iomem *recheck_bd; |
|
cbd_t __iomem *prev_bd; |
|
cbd_t __iomem *last_tx_bd; |
|
|
|
last_tx_bd = fep->tx_bd_base + (fpi->tx_ring - 1); |
|
|
|
/* get the current bd held in TBPTR and scan back from this point */ |
|
recheck_bd = curr_tbptr = (cbd_t __iomem *) |
|
((R32(ep, fen_genfcc.fcc_tbptr) - fep->ring_mem_addr) + |
|
fep->ring_base); |
|
|
|
prev_bd = (recheck_bd == fep->tx_bd_base) ? last_tx_bd : recheck_bd - 1; |
|
|
|
/* Move through the bds in reverse, look for the earliest buffer |
|
* that is not ready. Adjust TBPTR to the following buffer */ |
|
while ((CBDR_SC(prev_bd) & BD_ENET_TX_READY) != 0) { |
|
/* Go back one buffer */ |
|
recheck_bd = prev_bd; |
|
|
|
/* update the previous buffer */ |
|
prev_bd = (prev_bd == fep->tx_bd_base) ? last_tx_bd : prev_bd - 1; |
|
|
|
/* We should never see all bds marked as ready, check anyway */ |
|
if (recheck_bd == curr_tbptr) |
|
break; |
|
} |
|
/* Now update the TBPTR and dirty flag to the current buffer */ |
|
W32(ep, fen_genfcc.fcc_tbptr, |
|
(uint) (((void *)recheck_bd - fep->ring_base) + |
|
fep->ring_mem_addr)); |
|
fep->dirty_tx = recheck_bd; |
|
|
|
C32(fccp, fcc_gfmr, FCC_GFMR_ENT); |
|
udelay(10); |
|
S32(fccp, fcc_gfmr, FCC_GFMR_ENT); |
|
|
|
fcc_cr_cmd(fep, CPM_CR_RESTART_TX); |
|
} |
|
|
|
/*************************************************************************/ |
|
|
|
const struct fs_ops fs_fcc_ops = { |
|
.setup_data = setup_data, |
|
.cleanup_data = cleanup_data, |
|
.set_multicast_list = set_multicast_list, |
|
.restart = restart, |
|
.stop = stop, |
|
.napi_clear_event = napi_clear_event_fs, |
|
.napi_enable = napi_enable_fs, |
|
.napi_disable = napi_disable_fs, |
|
.rx_bd_done = rx_bd_done, |
|
.tx_kickstart = tx_kickstart, |
|
.get_int_events = get_int_events, |
|
.clear_int_events = clear_int_events, |
|
.ev_error = ev_error, |
|
.get_regs = get_regs, |
|
.get_regs_len = get_regs_len, |
|
.tx_restart = tx_restart, |
|
.allocate_bd = allocate_bd, |
|
.free_bd = free_bd, |
|
};
|
|
|