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648 lines
18 KiB
648 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Fast Ethernet Controller (ENET) PTP driver for MX6x. |
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* |
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* Copyright (C) 2012 Freescale Semiconductor, Inc. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/ptrace.h> |
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#include <linux/errno.h> |
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#include <linux/ioport.h> |
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#include <linux/slab.h> |
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#include <linux/interrupt.h> |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/skbuff.h> |
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#include <linux/spinlock.h> |
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#include <linux/workqueue.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/clk.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy.h> |
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#include <linux/fec.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/of_gpio.h> |
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#include <linux/of_net.h> |
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#include "fec.h" |
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/* FEC 1588 register bits */ |
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#define FEC_T_CTRL_SLAVE 0x00002000 |
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#define FEC_T_CTRL_CAPTURE 0x00000800 |
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#define FEC_T_CTRL_RESTART 0x00000200 |
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#define FEC_T_CTRL_PERIOD_RST 0x00000030 |
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#define FEC_T_CTRL_PERIOD_EN 0x00000010 |
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#define FEC_T_CTRL_ENABLE 0x00000001 |
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#define FEC_T_INC_MASK 0x0000007f |
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#define FEC_T_INC_OFFSET 0 |
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#define FEC_T_INC_CORR_MASK 0x00007f00 |
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#define FEC_T_INC_CORR_OFFSET 8 |
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#define FEC_T_CTRL_PINPER 0x00000080 |
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#define FEC_T_TF0_MASK 0x00000001 |
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#define FEC_T_TF0_OFFSET 0 |
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#define FEC_T_TF1_MASK 0x00000002 |
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#define FEC_T_TF1_OFFSET 1 |
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#define FEC_T_TF2_MASK 0x00000004 |
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#define FEC_T_TF2_OFFSET 2 |
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#define FEC_T_TF3_MASK 0x00000008 |
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#define FEC_T_TF3_OFFSET 3 |
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#define FEC_T_TDRE_MASK 0x00000001 |
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#define FEC_T_TDRE_OFFSET 0 |
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#define FEC_T_TMODE_MASK 0x0000003C |
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#define FEC_T_TMODE_OFFSET 2 |
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#define FEC_T_TIE_MASK 0x00000040 |
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#define FEC_T_TIE_OFFSET 6 |
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#define FEC_T_TF_MASK 0x00000080 |
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#define FEC_T_TF_OFFSET 7 |
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#define FEC_ATIME_CTRL 0x400 |
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#define FEC_ATIME 0x404 |
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#define FEC_ATIME_EVT_OFFSET 0x408 |
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#define FEC_ATIME_EVT_PERIOD 0x40c |
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#define FEC_ATIME_CORR 0x410 |
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#define FEC_ATIME_INC 0x414 |
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#define FEC_TS_TIMESTAMP 0x418 |
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#define FEC_TGSR 0x604 |
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#define FEC_TCSR(n) (0x608 + n * 0x08) |
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#define FEC_TCCR(n) (0x60C + n * 0x08) |
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#define MAX_TIMER_CHANNEL 3 |
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#define FEC_TMODE_TOGGLE 0x05 |
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#define FEC_HIGH_PULSE 0x0F |
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#define FEC_CC_MULT (1 << 31) |
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#define FEC_COUNTER_PERIOD (1 << 31) |
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#define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC |
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#define FEC_CHANNLE_0 0 |
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#define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0 |
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/** |
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* fec_ptp_enable_pps |
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* @fep: the fec_enet_private structure handle |
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* @enable: enable the channel pps output |
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* |
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* This function enble the PPS ouput on the timer channel. |
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*/ |
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static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable) |
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{ |
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unsigned long flags; |
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u32 val, tempval; |
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struct timespec64 ts; |
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u64 ns; |
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val = 0; |
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if (fep->pps_enable == enable) |
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return 0; |
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fep->pps_channel = DEFAULT_PPS_CHANNEL; |
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fep->reload_period = PPS_OUPUT_RELOAD_PERIOD; |
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spin_lock_irqsave(&fep->tmreg_lock, flags); |
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if (enable) { |
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/* clear capture or output compare interrupt status if have. |
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*/ |
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writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); |
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/* It is recommended to double check the TMODE field in the |
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* TCSR register to be cleared before the first compare counter |
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* is written into TCCR register. Just add a double check. |
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*/ |
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val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); |
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do { |
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val &= ~(FEC_T_TMODE_MASK); |
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writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); |
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val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); |
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} while (val & FEC_T_TMODE_MASK); |
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/* Dummy read counter to update the counter */ |
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timecounter_read(&fep->tc); |
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/* We want to find the first compare event in the next |
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* second point. So we need to know what the ptp time |
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* is now and how many nanoseconds is ahead to get next second. |
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* The remaining nanosecond ahead before the next second would be |
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* NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds |
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* to current timer would be next second. |
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*/ |
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tempval = readl(fep->hwp + FEC_ATIME_CTRL); |
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tempval |= FEC_T_CTRL_CAPTURE; |
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writel(tempval, fep->hwp + FEC_ATIME_CTRL); |
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tempval = readl(fep->hwp + FEC_ATIME); |
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/* Convert the ptp local counter to 1588 timestamp */ |
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ns = timecounter_cyc2time(&fep->tc, tempval); |
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ts = ns_to_timespec64(ns); |
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/* The tempval is less than 3 seconds, and so val is less than |
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* 4 seconds. No overflow for 32bit calculation. |
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*/ |
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val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval; |
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/* Need to consider the situation that the current time is |
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* very close to the second point, which means NSEC_PER_SEC |
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* - ts.tv_nsec is close to be zero(For example 20ns); Since the timer |
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* is still running when we calculate the first compare event, it is |
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* possible that the remaining nanoseonds run out before the compare |
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* counter is calculated and written into TCCR register. To avoid |
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* this possibility, we will set the compare event to be the next |
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* of next second. The current setting is 31-bit timer and wrap |
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* around over 2 seconds. So it is okay to set the next of next |
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* seond for the timer. |
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*/ |
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val += NSEC_PER_SEC; |
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/* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current |
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* ptp counter, which maybe cause 32-bit wrap. Since the |
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* (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second. |
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* We can ensure the wrap will not cause issue. If the offset |
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* is bigger than fep->cc.mask would be a error. |
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*/ |
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val &= fep->cc.mask; |
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writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); |
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/* Calculate the second the compare event timestamp */ |
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fep->next_counter = (val + fep->reload_period) & fep->cc.mask; |
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/* * Enable compare event when overflow */ |
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val = readl(fep->hwp + FEC_ATIME_CTRL); |
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val |= FEC_T_CTRL_PINPER; |
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writel(val, fep->hwp + FEC_ATIME_CTRL); |
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/* Compare channel setting. */ |
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val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); |
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val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); |
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val &= ~(1 << FEC_T_TDRE_OFFSET); |
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val &= ~(FEC_T_TMODE_MASK); |
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val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET); |
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writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); |
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/* Write the second compare event timestamp and calculate |
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* the third timestamp. Refer the TCCR register detail in the spec. |
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*/ |
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writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); |
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fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; |
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} else { |
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writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); |
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} |
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fep->pps_enable = enable; |
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spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
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return 0; |
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} |
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/** |
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* fec_ptp_read - read raw cycle counter (to be used by time counter) |
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* @cc: the cyclecounter structure |
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* |
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* this function reads the cyclecounter registers and is called by the |
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* cyclecounter structure used to construct a ns counter from the |
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* arbitrary fixed point registers |
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*/ |
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static u64 fec_ptp_read(const struct cyclecounter *cc) |
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{ |
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struct fec_enet_private *fep = |
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container_of(cc, struct fec_enet_private, cc); |
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u32 tempval; |
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tempval = readl(fep->hwp + FEC_ATIME_CTRL); |
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tempval |= FEC_T_CTRL_CAPTURE; |
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writel(tempval, fep->hwp + FEC_ATIME_CTRL); |
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if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) |
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udelay(1); |
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return readl(fep->hwp + FEC_ATIME); |
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} |
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/** |
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* fec_ptp_start_cyclecounter - create the cycle counter from hw |
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* @ndev: network device |
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* |
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* this function initializes the timecounter and cyclecounter |
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* structures for use in generated a ns counter from the arbitrary |
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* fixed point cycles registers in the hardware. |
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*/ |
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void fec_ptp_start_cyclecounter(struct net_device *ndev) |
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{ |
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struct fec_enet_private *fep = netdev_priv(ndev); |
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unsigned long flags; |
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int inc; |
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inc = 1000000000 / fep->cycle_speed; |
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/* grab the ptp lock */ |
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spin_lock_irqsave(&fep->tmreg_lock, flags); |
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/* 1ns counter */ |
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writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); |
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/* use 31-bit timer counter */ |
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writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD); |
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writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST, |
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fep->hwp + FEC_ATIME_CTRL); |
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memset(&fep->cc, 0, sizeof(fep->cc)); |
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fep->cc.read = fec_ptp_read; |
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fep->cc.mask = CLOCKSOURCE_MASK(31); |
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fep->cc.shift = 31; |
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fep->cc.mult = FEC_CC_MULT; |
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/* reset the ns time counter */ |
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timecounter_init(&fep->tc, &fep->cc, 0); |
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spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
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} |
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/** |
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* fec_ptp_adjfreq - adjust ptp cycle frequency |
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* @ptp: the ptp clock structure |
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* @ppb: parts per billion adjustment from base |
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* |
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* Adjust the frequency of the ptp cycle counter by the |
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* indicated ppb from the base frequency. |
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* |
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* Because ENET hardware frequency adjust is complex, |
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* using software method to do that. |
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*/ |
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static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) |
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{ |
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unsigned long flags; |
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int neg_adj = 0; |
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u32 i, tmp; |
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u32 corr_inc, corr_period; |
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u32 corr_ns; |
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u64 lhs, rhs; |
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struct fec_enet_private *fep = |
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container_of(ptp, struct fec_enet_private, ptp_caps); |
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if (ppb == 0) |
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return 0; |
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if (ppb < 0) { |
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ppb = -ppb; |
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neg_adj = 1; |
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} |
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/* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC; |
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* Try to find the corr_inc between 1 to fep->ptp_inc to |
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* meet adjustment requirement. |
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*/ |
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lhs = NSEC_PER_SEC; |
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rhs = (u64)ppb * (u64)fep->ptp_inc; |
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for (i = 1; i <= fep->ptp_inc; i++) { |
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if (lhs >= rhs) { |
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corr_inc = i; |
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corr_period = div_u64(lhs, rhs); |
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break; |
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} |
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lhs += NSEC_PER_SEC; |
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} |
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/* Not found? Set it to high value - double speed |
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* correct in every clock step. |
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*/ |
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if (i > fep->ptp_inc) { |
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corr_inc = fep->ptp_inc; |
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corr_period = 1; |
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} |
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if (neg_adj) |
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corr_ns = fep->ptp_inc - corr_inc; |
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else |
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corr_ns = fep->ptp_inc + corr_inc; |
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spin_lock_irqsave(&fep->tmreg_lock, flags); |
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tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; |
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tmp |= corr_ns << FEC_T_INC_CORR_OFFSET; |
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writel(tmp, fep->hwp + FEC_ATIME_INC); |
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corr_period = corr_period > 1 ? corr_period - 1 : corr_period; |
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writel(corr_period, fep->hwp + FEC_ATIME_CORR); |
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/* dummy read to update the timer. */ |
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timecounter_read(&fep->tc); |
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spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
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return 0; |
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} |
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/** |
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* fec_ptp_adjtime |
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* @ptp: the ptp clock structure |
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* @delta: offset to adjust the cycle counter by |
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* |
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* adjust the timer by resetting the timecounter structure. |
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*/ |
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static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) |
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{ |
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struct fec_enet_private *fep = |
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container_of(ptp, struct fec_enet_private, ptp_caps); |
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unsigned long flags; |
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spin_lock_irqsave(&fep->tmreg_lock, flags); |
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timecounter_adjtime(&fep->tc, delta); |
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spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
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return 0; |
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} |
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/** |
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* fec_ptp_gettime |
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* @ptp: the ptp clock structure |
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* @ts: timespec structure to hold the current time value |
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* |
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* read the timecounter and return the correct value on ns, |
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* after converting it into a struct timespec. |
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*/ |
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static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
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{ |
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struct fec_enet_private *adapter = |
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container_of(ptp, struct fec_enet_private, ptp_caps); |
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u64 ns; |
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unsigned long flags; |
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mutex_lock(&adapter->ptp_clk_mutex); |
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/* Check the ptp clock */ |
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if (!adapter->ptp_clk_on) { |
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mutex_unlock(&adapter->ptp_clk_mutex); |
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return -EINVAL; |
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} |
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spin_lock_irqsave(&adapter->tmreg_lock, flags); |
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ns = timecounter_read(&adapter->tc); |
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spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
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mutex_unlock(&adapter->ptp_clk_mutex); |
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*ts = ns_to_timespec64(ns); |
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return 0; |
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} |
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/** |
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* fec_ptp_settime |
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* @ptp: the ptp clock structure |
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* @ts: the timespec containing the new time for the cycle counter |
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* |
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* reset the timecounter to use a new base value instead of the kernel |
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* wall timer value. |
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*/ |
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static int fec_ptp_settime(struct ptp_clock_info *ptp, |
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const struct timespec64 *ts) |
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{ |
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struct fec_enet_private *fep = |
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container_of(ptp, struct fec_enet_private, ptp_caps); |
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u64 ns; |
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unsigned long flags; |
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u32 counter; |
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mutex_lock(&fep->ptp_clk_mutex); |
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/* Check the ptp clock */ |
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if (!fep->ptp_clk_on) { |
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mutex_unlock(&fep->ptp_clk_mutex); |
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return -EINVAL; |
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} |
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ns = timespec64_to_ns(ts); |
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/* Get the timer value based on timestamp. |
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* Update the counter with the masked value. |
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*/ |
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counter = ns & fep->cc.mask; |
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spin_lock_irqsave(&fep->tmreg_lock, flags); |
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writel(counter, fep->hwp + FEC_ATIME); |
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timecounter_init(&fep->tc, &fep->cc, ns); |
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spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
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mutex_unlock(&fep->ptp_clk_mutex); |
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return 0; |
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} |
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/** |
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* fec_ptp_enable |
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* @ptp: the ptp clock structure |
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* @rq: the requested feature to change |
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* @on: whether to enable or disable the feature |
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* |
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*/ |
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static int fec_ptp_enable(struct ptp_clock_info *ptp, |
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struct ptp_clock_request *rq, int on) |
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{ |
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struct fec_enet_private *fep = |
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container_of(ptp, struct fec_enet_private, ptp_caps); |
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int ret = 0; |
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if (rq->type == PTP_CLK_REQ_PPS) { |
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ret = fec_ptp_enable_pps(fep, on); |
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return ret; |
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} |
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return -EOPNOTSUPP; |
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} |
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/** |
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* fec_ptp_disable_hwts - disable hardware time stamping |
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* @ndev: pointer to net_device |
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*/ |
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void fec_ptp_disable_hwts(struct net_device *ndev) |
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{ |
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struct fec_enet_private *fep = netdev_priv(ndev); |
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fep->hwts_tx_en = 0; |
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fep->hwts_rx_en = 0; |
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} |
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int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr) |
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{ |
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struct fec_enet_private *fep = netdev_priv(ndev); |
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struct hwtstamp_config config; |
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if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) |
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return -EFAULT; |
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/* reserved for future extensions */ |
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if (config.flags) |
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return -EINVAL; |
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switch (config.tx_type) { |
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case HWTSTAMP_TX_OFF: |
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fep->hwts_tx_en = 0; |
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break; |
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case HWTSTAMP_TX_ON: |
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fep->hwts_tx_en = 1; |
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break; |
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default: |
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return -ERANGE; |
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} |
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switch (config.rx_filter) { |
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case HWTSTAMP_FILTER_NONE: |
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fep->hwts_rx_en = 0; |
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break; |
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default: |
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fep->hwts_rx_en = 1; |
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config.rx_filter = HWTSTAMP_FILTER_ALL; |
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break; |
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} |
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return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
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-EFAULT : 0; |
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} |
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int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr) |
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{ |
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struct fec_enet_private *fep = netdev_priv(ndev); |
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struct hwtstamp_config config; |
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config.flags = 0; |
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config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; |
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config.rx_filter = (fep->hwts_rx_en ? |
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HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); |
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return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
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-EFAULT : 0; |
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} |
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/* |
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* fec_time_keep - call timecounter_read every second to avoid timer overrun |
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* because ENET just support 32bit counter, will timeout in 4s |
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*/ |
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static void fec_time_keep(struct work_struct *work) |
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{ |
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struct delayed_work *dwork = to_delayed_work(work); |
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struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep); |
|
unsigned long flags; |
|
|
|
mutex_lock(&fep->ptp_clk_mutex); |
|
if (fep->ptp_clk_on) { |
|
spin_lock_irqsave(&fep->tmreg_lock, flags); |
|
timecounter_read(&fep->tc); |
|
spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
|
} |
|
mutex_unlock(&fep->ptp_clk_mutex); |
|
|
|
schedule_delayed_work(&fep->time_keep, HZ); |
|
} |
|
|
|
/* This function checks the pps event and reloads the timer compare counter. */ |
|
static irqreturn_t fec_pps_interrupt(int irq, void *dev_id) |
|
{ |
|
struct net_device *ndev = dev_id; |
|
struct fec_enet_private *fep = netdev_priv(ndev); |
|
u32 val; |
|
u8 channel = fep->pps_channel; |
|
struct ptp_clock_event event; |
|
|
|
val = readl(fep->hwp + FEC_TCSR(channel)); |
|
if (val & FEC_T_TF_MASK) { |
|
/* Write the next next compare(not the next according the spec) |
|
* value to the register |
|
*/ |
|
writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); |
|
do { |
|
writel(val, fep->hwp + FEC_TCSR(channel)); |
|
} while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); |
|
|
|
/* Update the counter; */ |
|
fep->next_counter = (fep->next_counter + fep->reload_period) & |
|
fep->cc.mask; |
|
|
|
event.type = PTP_CLOCK_PPS; |
|
ptp_clock_event(fep->ptp_clock, &event); |
|
return IRQ_HANDLED; |
|
} |
|
|
|
return IRQ_NONE; |
|
} |
|
|
|
/** |
|
* fec_ptp_init |
|
* @pdev: The FEC network adapter |
|
* @irq_idx: the interrupt index |
|
* |
|
* This function performs the required steps for enabling ptp |
|
* support. If ptp support has already been loaded it simply calls the |
|
* cyclecounter init routine and exits. |
|
*/ |
|
|
|
void fec_ptp_init(struct platform_device *pdev, int irq_idx) |
|
{ |
|
struct net_device *ndev = platform_get_drvdata(pdev); |
|
struct fec_enet_private *fep = netdev_priv(ndev); |
|
int irq; |
|
int ret; |
|
|
|
fep->ptp_caps.owner = THIS_MODULE; |
|
strlcpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name)); |
|
|
|
fep->ptp_caps.max_adj = 250000000; |
|
fep->ptp_caps.n_alarm = 0; |
|
fep->ptp_caps.n_ext_ts = 0; |
|
fep->ptp_caps.n_per_out = 0; |
|
fep->ptp_caps.n_pins = 0; |
|
fep->ptp_caps.pps = 1; |
|
fep->ptp_caps.adjfreq = fec_ptp_adjfreq; |
|
fep->ptp_caps.adjtime = fec_ptp_adjtime; |
|
fep->ptp_caps.gettime64 = fec_ptp_gettime; |
|
fep->ptp_caps.settime64 = fec_ptp_settime; |
|
fep->ptp_caps.enable = fec_ptp_enable; |
|
|
|
fep->cycle_speed = clk_get_rate(fep->clk_ptp); |
|
if (!fep->cycle_speed) { |
|
fep->cycle_speed = NSEC_PER_SEC; |
|
dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n"); |
|
} |
|
fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed; |
|
|
|
spin_lock_init(&fep->tmreg_lock); |
|
|
|
fec_ptp_start_cyclecounter(ndev); |
|
|
|
INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep); |
|
|
|
irq = platform_get_irq_byname_optional(pdev, "pps"); |
|
if (irq < 0) |
|
irq = platform_get_irq_optional(pdev, irq_idx); |
|
/* Failure to get an irq is not fatal, |
|
* only the PTP_CLOCK_PPS clock events should stop |
|
*/ |
|
if (irq >= 0) { |
|
ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt, |
|
0, pdev->name, ndev); |
|
if (ret < 0) |
|
dev_warn(&pdev->dev, "request for pps irq failed(%d)\n", |
|
ret); |
|
} |
|
|
|
fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev); |
|
if (IS_ERR(fep->ptp_clock)) { |
|
fep->ptp_clock = NULL; |
|
dev_err(&pdev->dev, "ptp_clock_register failed\n"); |
|
} |
|
|
|
schedule_delayed_work(&fep->time_keep, HZ); |
|
} |
|
|
|
void fec_ptp_stop(struct platform_device *pdev) |
|
{ |
|
struct net_device *ndev = platform_get_drvdata(pdev); |
|
struct fec_enet_private *fep = netdev_priv(ndev); |
|
|
|
cancel_delayed_work_sync(&fep->time_keep); |
|
if (fep->ptp_clock) |
|
ptp_clock_unregister(fep->ptp_clock); |
|
}
|
|
|