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1053 lines
31 KiB
1053 lines
31 KiB
/* |
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* TI HECC (CAN) device driver |
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* |
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* This driver supports TI's HECC (High End CAN Controller module) and the |
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* specs for the same is available at <http://www.ti.com> |
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* |
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ |
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* Copyright (C) 2019 Jeroen Hofstee <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed as is WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/interrupt.h> |
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#include <linux/errno.h> |
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#include <linux/netdevice.h> |
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#include <linux/skbuff.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/regulator/consumer.h> |
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|
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#include <linux/can/dev.h> |
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#include <linux/can/error.h> |
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#include <linux/can/led.h> |
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#include <linux/can/rx-offload.h> |
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|
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#define DRV_NAME "ti_hecc" |
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#define HECC_MODULE_VERSION "0.7" |
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MODULE_VERSION(HECC_MODULE_VERSION); |
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#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION |
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|
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/* TX / RX Mailbox Configuration */ |
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#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ |
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#define MAX_TX_PRIO 0x3F /* hardware value - do not change */ |
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|
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/* Important Note: TX mailbox configuration |
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* TX mailboxes should be restricted to the number of SKB buffers to avoid |
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* maintaining SKB buffers separately. TX mailboxes should be a power of 2 |
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* for the mailbox logic to work. Top mailbox numbers are reserved for RX |
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* and lower mailboxes for TX. |
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* |
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* HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT |
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* 4 (default) 2 |
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* 8 3 |
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* 16 4 |
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*/ |
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#define HECC_MB_TX_SHIFT 2 /* as per table above */ |
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#define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) |
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|
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#define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) |
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#define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) |
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#define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) |
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#define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) |
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|
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/* RX mailbox configuration |
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* |
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* The remaining mailboxes are used for reception and are delivered |
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* based on their timestamp, to avoid a hardware race when CANME is |
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* changed while CAN-bus traffic is being received. |
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*/ |
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#define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) |
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#define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) |
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#define HECC_RX_LAST_MBOX (HECC_MAX_TX_MBOX) |
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|
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/* TI HECC module registers */ |
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#define HECC_CANME 0x0 /* Mailbox enable */ |
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#define HECC_CANMD 0x4 /* Mailbox direction */ |
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#define HECC_CANTRS 0x8 /* Transmit request set */ |
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#define HECC_CANTRR 0xC /* Transmit request */ |
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#define HECC_CANTA 0x10 /* Transmission acknowledge */ |
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#define HECC_CANAA 0x14 /* Abort acknowledge */ |
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#define HECC_CANRMP 0x18 /* Receive message pending */ |
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#define HECC_CANRML 0x1C /* Receive message lost */ |
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#define HECC_CANRFP 0x20 /* Remote frame pending */ |
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#define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ |
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#define HECC_CANMC 0x28 /* Master control */ |
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#define HECC_CANBTC 0x2C /* Bit timing configuration */ |
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#define HECC_CANES 0x30 /* Error and status */ |
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#define HECC_CANTEC 0x34 /* Transmit error counter */ |
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#define HECC_CANREC 0x38 /* Receive error counter */ |
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#define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ |
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#define HECC_CANGIM 0x40 /* Global interrupt mask */ |
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#define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ |
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#define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ |
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#define HECC_CANMIL 0x4C /* Mailbox interrupt level */ |
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#define HECC_CANOPC 0x50 /* Overwrite protection control */ |
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#define HECC_CANTIOC 0x54 /* Transmit I/O control */ |
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#define HECC_CANRIOC 0x58 /* Receive I/O control */ |
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#define HECC_CANLNT 0x5C /* HECC only: Local network time */ |
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#define HECC_CANTOC 0x60 /* HECC only: Time-out control */ |
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#define HECC_CANTOS 0x64 /* HECC only: Time-out status */ |
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#define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ |
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#define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ |
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|
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/* TI HECC RAM registers */ |
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#define HECC_CANMOTS 0x80 /* Message object time stamp */ |
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|
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/* Mailbox registers */ |
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#define HECC_CANMID 0x0 |
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#define HECC_CANMCF 0x4 |
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#define HECC_CANMDL 0x8 |
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#define HECC_CANMDH 0xC |
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#define HECC_SET_REG 0xFFFFFFFF |
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#define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ |
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#define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ |
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|
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#define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ |
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#define HECC_CANMC_CCR BIT(12) /* Change config request */ |
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#define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ |
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#define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ |
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#define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ |
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#define HECC_CANMC_SRES BIT(5) /* Software reset */ |
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|
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#define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ |
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#define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ |
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|
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#define HECC_CANMID_IDE BIT(31) /* Extended frame format */ |
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#define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ |
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#define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ |
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|
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#define HECC_CANES_FE BIT(24) /* form error */ |
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#define HECC_CANES_BE BIT(23) /* bit error */ |
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#define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ |
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#define HECC_CANES_CRCE BIT(21) /* CRC error */ |
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#define HECC_CANES_SE BIT(20) /* stuff bit error */ |
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#define HECC_CANES_ACKE BIT(19) /* ack error */ |
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#define HECC_CANES_BO BIT(18) /* Bus off status */ |
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#define HECC_CANES_EP BIT(17) /* Error passive status */ |
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#define HECC_CANES_EW BIT(16) /* Error warning status */ |
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#define HECC_CANES_SMA BIT(5) /* suspend mode ack */ |
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#define HECC_CANES_CCE BIT(4) /* Change config enabled */ |
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#define HECC_CANES_PDA BIT(3) /* Power down mode ack */ |
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|
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#define HECC_CANBTC_SAM BIT(7) /* sample points */ |
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|
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#define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ |
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HECC_CANES_CRCE | HECC_CANES_SE |\ |
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HECC_CANES_ACKE) |
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#define HECC_CANES_FLAGS (HECC_BUS_ERROR | HECC_CANES_BO |\ |
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HECC_CANES_EP | HECC_CANES_EW) |
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|
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#define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ |
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|
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#define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ |
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#define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ |
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#define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ |
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#define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ |
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#define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ |
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#define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ |
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#define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ |
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#define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ |
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#define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ |
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#define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ |
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#define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ |
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#define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ |
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#define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ |
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#define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ |
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#define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ |
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|
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/* CAN Bittiming constants as per HECC specs */ |
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static const struct can_bittiming_const ti_hecc_bittiming_const = { |
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.name = DRV_NAME, |
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.tseg1_min = 1, |
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.tseg1_max = 16, |
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.tseg2_min = 1, |
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.tseg2_max = 8, |
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.sjw_max = 4, |
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.brp_min = 1, |
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.brp_max = 256, |
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.brp_inc = 1, |
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}; |
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struct ti_hecc_priv { |
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struct can_priv can; /* MUST be first member/field */ |
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struct can_rx_offload offload; |
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struct net_device *ndev; |
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struct clk *clk; |
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void __iomem *base; |
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void __iomem *hecc_ram; |
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void __iomem *mbx; |
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bool use_hecc1int; |
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spinlock_t mbx_lock; /* CANME register needs protection */ |
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u32 tx_head; |
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u32 tx_tail; |
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struct regulator *reg_xceiver; |
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}; |
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static inline int get_tx_head_mb(struct ti_hecc_priv *priv) |
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{ |
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return priv->tx_head & HECC_TX_MB_MASK; |
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} |
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static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) |
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{ |
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return priv->tx_tail & HECC_TX_MB_MASK; |
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} |
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static inline int get_tx_head_prio(struct ti_hecc_priv *priv) |
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{ |
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return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; |
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} |
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static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) |
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{ |
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__raw_writel(val, priv->hecc_ram + mbxno * 4); |
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} |
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static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno) |
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{ |
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return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); |
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} |
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static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, |
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u32 reg, u32 val) |
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{ |
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__raw_writel(val, priv->mbx + mbxno * 0x10 + reg); |
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} |
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static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) |
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{ |
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return __raw_readl(priv->mbx + mbxno * 0x10 + reg); |
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} |
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static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) |
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{ |
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__raw_writel(val, priv->base + reg); |
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} |
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static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) |
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{ |
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return __raw_readl(priv->base + reg); |
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} |
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static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, |
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u32 bit_mask) |
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{ |
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hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); |
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} |
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static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, |
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u32 bit_mask) |
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{ |
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hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); |
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} |
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static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) |
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{ |
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return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; |
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} |
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static int ti_hecc_set_btc(struct ti_hecc_priv *priv) |
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{ |
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struct can_bittiming *bit_timing = &priv->can.bittiming; |
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u32 can_btc; |
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can_btc = (bit_timing->phase_seg2 - 1) & 0x7; |
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can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) |
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& 0xF) << 3; |
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if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { |
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if (bit_timing->brp > 4) |
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can_btc |= HECC_CANBTC_SAM; |
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else |
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netdev_warn(priv->ndev, |
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"WARN: Triple sampling not set due to h/w limitations"); |
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} |
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can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; |
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can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; |
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/* ERM being set to 0 by default meaning resync at falling edge */ |
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hecc_write(priv, HECC_CANBTC, can_btc); |
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netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); |
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return 0; |
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} |
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static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv, |
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int on) |
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{ |
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if (!priv->reg_xceiver) |
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return 0; |
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|
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if (on) |
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return regulator_enable(priv->reg_xceiver); |
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else |
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return regulator_disable(priv->reg_xceiver); |
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} |
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static void ti_hecc_reset(struct net_device *ndev) |
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{ |
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u32 cnt; |
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struct ti_hecc_priv *priv = netdev_priv(ndev); |
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|
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netdev_dbg(ndev, "resetting hecc ...\n"); |
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hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); |
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|
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/* Set change control request and wait till enabled */ |
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hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); |
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|
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/* INFO: It has been observed that at times CCE bit may not be |
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* set and hw seems to be ok even if this bit is not set so |
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* timing out with a timing of 1ms to respect the specs |
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*/ |
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cnt = HECC_CCE_WAIT_COUNT; |
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while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { |
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--cnt; |
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udelay(10); |
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} |
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|
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/* Note: On HECC, BTC can be programmed only in initialization mode, so |
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* it is expected that the can bittiming parameters are set via ip |
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* utility before the device is opened |
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*/ |
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ti_hecc_set_btc(priv); |
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|
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/* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ |
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hecc_write(priv, HECC_CANMC, 0); |
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|
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/* INFO: CAN net stack handles bus off and hence disabling auto-bus-on |
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* hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); |
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*/ |
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|
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/* INFO: It has been observed that at times CCE bit may not be |
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* set and hw seems to be ok even if this bit is not set so |
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*/ |
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cnt = HECC_CCE_WAIT_COUNT; |
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while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { |
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--cnt; |
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udelay(10); |
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} |
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|
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/* Enable TX and RX I/O Control pins */ |
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hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); |
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hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); |
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|
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/* Clear registers for clean operation */ |
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hecc_write(priv, HECC_CANTA, HECC_SET_REG); |
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hecc_write(priv, HECC_CANRMP, HECC_SET_REG); |
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hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); |
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hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); |
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hecc_write(priv, HECC_CANME, 0); |
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hecc_write(priv, HECC_CANMD, 0); |
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|
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/* SCC compat mode NOT supported (and not needed too) */ |
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hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); |
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} |
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static void ti_hecc_start(struct net_device *ndev) |
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{ |
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struct ti_hecc_priv *priv = netdev_priv(ndev); |
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u32 cnt, mbxno, mbx_mask; |
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|
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/* put HECC in initialization mode and set btc */ |
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ti_hecc_reset(ndev); |
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|
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priv->tx_head = HECC_TX_MASK; |
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priv->tx_tail = HECC_TX_MASK; |
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|
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/* Enable local and global acceptance mask registers */ |
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hecc_write(priv, HECC_CANGAM, HECC_SET_REG); |
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|
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/* Prepare configured mailboxes to receive messages */ |
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for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { |
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mbxno = HECC_MAX_MAILBOXES - 1 - cnt; |
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mbx_mask = BIT(mbxno); |
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hecc_clear_bit(priv, HECC_CANME, mbx_mask); |
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hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); |
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hecc_write_lam(priv, mbxno, HECC_SET_REG); |
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hecc_set_bit(priv, HECC_CANMD, mbx_mask); |
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hecc_set_bit(priv, HECC_CANME, mbx_mask); |
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hecc_set_bit(priv, HECC_CANMIM, mbx_mask); |
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} |
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|
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/* Enable tx interrupts */ |
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hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1); |
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|
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/* Prevent message over-write to create a rx fifo, but not for |
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* the lowest priority mailbox, since that allows detecting |
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* overflows instead of the hardware silently dropping the |
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* messages. |
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*/ |
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mbx_mask = ~BIT(HECC_RX_LAST_MBOX); |
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hecc_write(priv, HECC_CANOPC, mbx_mask); |
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|
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/* Enable interrupts */ |
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if (priv->use_hecc1int) { |
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hecc_write(priv, HECC_CANMIL, HECC_SET_REG); |
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hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | |
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HECC_CANGIM_I1EN | HECC_CANGIM_SIL); |
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} else { |
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hecc_write(priv, HECC_CANMIL, 0); |
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hecc_write(priv, HECC_CANGIM, |
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HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); |
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} |
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priv->can.state = CAN_STATE_ERROR_ACTIVE; |
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} |
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|
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static void ti_hecc_stop(struct net_device *ndev) |
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{ |
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struct ti_hecc_priv *priv = netdev_priv(ndev); |
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|
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/* Disable the CPK; stop sending, erroring and acking */ |
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hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); |
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|
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/* Disable interrupts and disable mailboxes */ |
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hecc_write(priv, HECC_CANGIM, 0); |
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hecc_write(priv, HECC_CANMIM, 0); |
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hecc_write(priv, HECC_CANME, 0); |
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priv->can.state = CAN_STATE_STOPPED; |
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} |
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|
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static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) |
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{ |
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int ret = 0; |
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|
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switch (mode) { |
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case CAN_MODE_START: |
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ti_hecc_start(ndev); |
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netif_wake_queue(ndev); |
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break; |
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default: |
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ret = -EOPNOTSUPP; |
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break; |
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} |
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|
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return ret; |
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} |
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|
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static int ti_hecc_get_berr_counter(const struct net_device *ndev, |
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struct can_berr_counter *bec) |
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{ |
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struct ti_hecc_priv *priv = netdev_priv(ndev); |
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|
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bec->txerr = hecc_read(priv, HECC_CANTEC); |
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bec->rxerr = hecc_read(priv, HECC_CANREC); |
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|
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return 0; |
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} |
|
|
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/* ti_hecc_xmit: HECC Transmit |
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* |
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* The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the |
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* priority of the mailbox for transmission is dependent upon priority setting |
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* field in mailbox registers. The mailbox with highest value in priority field |
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* is transmitted first. Only when two mailboxes have the same value in |
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* priority field the highest numbered mailbox is transmitted first. |
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* |
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* To utilize the HECC priority feature as described above we start with the |
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* highest numbered mailbox with highest priority level and move on to the next |
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* mailbox with the same priority level and so on. Once we loop through all the |
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* transmit mailboxes we choose the next priority level (lower) and so on |
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* until we reach the lowest priority level on the lowest numbered mailbox |
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* when we stop transmission until all mailboxes are transmitted and then |
|
* restart at highest numbered mailbox with highest priority. |
|
* |
|
* Two counters (head and tail) are used to track the next mailbox to transmit |
|
* and to track the echo buffer for already transmitted mailbox. The queue |
|
* is stopped when all the mailboxes are busy or when there is a priority |
|
* value roll-over happens. |
|
*/ |
|
static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) |
|
{ |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
struct can_frame *cf = (struct can_frame *)skb->data; |
|
u32 mbxno, mbx_mask, data; |
|
unsigned long flags; |
|
|
|
if (can_dropped_invalid_skb(ndev, skb)) |
|
return NETDEV_TX_OK; |
|
|
|
mbxno = get_tx_head_mb(priv); |
|
mbx_mask = BIT(mbxno); |
|
spin_lock_irqsave(&priv->mbx_lock, flags); |
|
if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { |
|
spin_unlock_irqrestore(&priv->mbx_lock, flags); |
|
netif_stop_queue(ndev); |
|
netdev_err(priv->ndev, |
|
"BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", |
|
priv->tx_head, priv->tx_tail); |
|
return NETDEV_TX_BUSY; |
|
} |
|
spin_unlock_irqrestore(&priv->mbx_lock, flags); |
|
|
|
/* Prepare mailbox for transmission */ |
|
data = cf->len | (get_tx_head_prio(priv) << 8); |
|
if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ |
|
data |= HECC_CANMCF_RTR; |
|
hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); |
|
|
|
if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ |
|
data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; |
|
else /* Standard frame format */ |
|
data = (cf->can_id & CAN_SFF_MASK) << 18; |
|
hecc_write_mbx(priv, mbxno, HECC_CANMID, data); |
|
hecc_write_mbx(priv, mbxno, HECC_CANMDL, |
|
be32_to_cpu(*(__be32 *)(cf->data))); |
|
if (cf->len > 4) |
|
hecc_write_mbx(priv, mbxno, HECC_CANMDH, |
|
be32_to_cpu(*(__be32 *)(cf->data + 4))); |
|
else |
|
*(u32 *)(cf->data + 4) = 0; |
|
can_put_echo_skb(skb, ndev, mbxno, 0); |
|
|
|
spin_lock_irqsave(&priv->mbx_lock, flags); |
|
--priv->tx_head; |
|
if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || |
|
(priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { |
|
netif_stop_queue(ndev); |
|
} |
|
hecc_set_bit(priv, HECC_CANME, mbx_mask); |
|
spin_unlock_irqrestore(&priv->mbx_lock, flags); |
|
|
|
hecc_write(priv, HECC_CANTRS, mbx_mask); |
|
|
|
return NETDEV_TX_OK; |
|
} |
|
|
|
static inline |
|
struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload) |
|
{ |
|
return container_of(offload, struct ti_hecc_priv, offload); |
|
} |
|
|
|
static struct sk_buff *ti_hecc_mailbox_read(struct can_rx_offload *offload, |
|
unsigned int mbxno, u32 *timestamp, |
|
bool drop) |
|
{ |
|
struct ti_hecc_priv *priv = rx_offload_to_priv(offload); |
|
struct sk_buff *skb; |
|
struct can_frame *cf; |
|
u32 data, mbx_mask; |
|
|
|
mbx_mask = BIT(mbxno); |
|
|
|
if (unlikely(drop)) { |
|
skb = ERR_PTR(-ENOBUFS); |
|
goto mark_as_read; |
|
} |
|
|
|
skb = alloc_can_skb(offload->dev, &cf); |
|
if (unlikely(!skb)) { |
|
skb = ERR_PTR(-ENOMEM); |
|
goto mark_as_read; |
|
} |
|
|
|
data = hecc_read_mbx(priv, mbxno, HECC_CANMID); |
|
if (data & HECC_CANMID_IDE) |
|
cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; |
|
else |
|
cf->can_id = (data >> 18) & CAN_SFF_MASK; |
|
|
|
data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); |
|
if (data & HECC_CANMCF_RTR) |
|
cf->can_id |= CAN_RTR_FLAG; |
|
cf->len = can_cc_dlc2len(data & 0xF); |
|
|
|
data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); |
|
*(__be32 *)(cf->data) = cpu_to_be32(data); |
|
if (cf->len > 4) { |
|
data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); |
|
*(__be32 *)(cf->data + 4) = cpu_to_be32(data); |
|
} |
|
|
|
*timestamp = hecc_read_stamp(priv, mbxno); |
|
|
|
/* Check for FIFO overrun. |
|
* |
|
* All but the last RX mailbox have activated overwrite |
|
* protection. So skip check for overrun, if we're not |
|
* handling the last RX mailbox. |
|
* |
|
* As the overwrite protection for the last RX mailbox is |
|
* disabled, the CAN core might update while we're reading |
|
* it. This means the skb might be inconsistent. |
|
* |
|
* Return an error to let rx-offload discard this CAN frame. |
|
*/ |
|
if (unlikely(mbxno == HECC_RX_LAST_MBOX && |
|
hecc_read(priv, HECC_CANRML) & mbx_mask)) |
|
skb = ERR_PTR(-ENOBUFS); |
|
|
|
mark_as_read: |
|
hecc_write(priv, HECC_CANRMP, mbx_mask); |
|
|
|
return skb; |
|
} |
|
|
|
static int ti_hecc_error(struct net_device *ndev, int int_status, |
|
int err_status) |
|
{ |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
struct can_frame *cf; |
|
struct sk_buff *skb; |
|
u32 timestamp; |
|
int err; |
|
|
|
if (err_status & HECC_BUS_ERROR) { |
|
/* propagate the error condition to the can stack */ |
|
skb = alloc_can_err_skb(ndev, &cf); |
|
if (!skb) { |
|
if (net_ratelimit()) |
|
netdev_err(priv->ndev, |
|
"%s: alloc_can_err_skb() failed\n", |
|
__func__); |
|
return -ENOMEM; |
|
} |
|
|
|
++priv->can.can_stats.bus_error; |
|
cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; |
|
if (err_status & HECC_CANES_FE) |
|
cf->data[2] |= CAN_ERR_PROT_FORM; |
|
if (err_status & HECC_CANES_BE) |
|
cf->data[2] |= CAN_ERR_PROT_BIT; |
|
if (err_status & HECC_CANES_SE) |
|
cf->data[2] |= CAN_ERR_PROT_STUFF; |
|
if (err_status & HECC_CANES_CRCE) |
|
cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; |
|
if (err_status & HECC_CANES_ACKE) |
|
cf->data[3] = CAN_ERR_PROT_LOC_ACK; |
|
|
|
timestamp = hecc_read(priv, HECC_CANLNT); |
|
err = can_rx_offload_queue_sorted(&priv->offload, skb, |
|
timestamp); |
|
if (err) |
|
ndev->stats.rx_fifo_errors++; |
|
} |
|
|
|
hecc_write(priv, HECC_CANES, HECC_CANES_FLAGS); |
|
|
|
return 0; |
|
} |
|
|
|
static void ti_hecc_change_state(struct net_device *ndev, |
|
enum can_state rx_state, |
|
enum can_state tx_state) |
|
{ |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
struct can_frame *cf; |
|
struct sk_buff *skb; |
|
u32 timestamp; |
|
int err; |
|
|
|
skb = alloc_can_err_skb(priv->ndev, &cf); |
|
if (unlikely(!skb)) { |
|
priv->can.state = max(tx_state, rx_state); |
|
return; |
|
} |
|
|
|
can_change_state(priv->ndev, cf, tx_state, rx_state); |
|
|
|
if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) { |
|
cf->data[6] = hecc_read(priv, HECC_CANTEC); |
|
cf->data[7] = hecc_read(priv, HECC_CANREC); |
|
} |
|
|
|
timestamp = hecc_read(priv, HECC_CANLNT); |
|
err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); |
|
if (err) |
|
ndev->stats.rx_fifo_errors++; |
|
} |
|
|
|
static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) |
|
{ |
|
struct net_device *ndev = (struct net_device *)dev_id; |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
struct net_device_stats *stats = &ndev->stats; |
|
u32 mbxno, mbx_mask, int_status, err_status, stamp; |
|
unsigned long flags, rx_pending; |
|
u32 handled = 0; |
|
|
|
int_status = hecc_read(priv, |
|
priv->use_hecc1int ? |
|
HECC_CANGIF1 : HECC_CANGIF0); |
|
|
|
if (!int_status) |
|
return IRQ_NONE; |
|
|
|
err_status = hecc_read(priv, HECC_CANES); |
|
if (unlikely(err_status & HECC_CANES_FLAGS)) |
|
ti_hecc_error(ndev, int_status, err_status); |
|
|
|
if (unlikely(int_status & HECC_CANGIM_DEF_MASK)) { |
|
enum can_state rx_state, tx_state; |
|
u32 rec = hecc_read(priv, HECC_CANREC); |
|
u32 tec = hecc_read(priv, HECC_CANTEC); |
|
|
|
if (int_status & HECC_CANGIF_WLIF) { |
|
handled |= HECC_CANGIF_WLIF; |
|
rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0; |
|
tx_state = rec <= tec ? CAN_STATE_ERROR_WARNING : 0; |
|
netdev_dbg(priv->ndev, "Error Warning interrupt\n"); |
|
ti_hecc_change_state(ndev, rx_state, tx_state); |
|
} |
|
|
|
if (int_status & HECC_CANGIF_EPIF) { |
|
handled |= HECC_CANGIF_EPIF; |
|
rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0; |
|
tx_state = rec <= tec ? CAN_STATE_ERROR_PASSIVE : 0; |
|
netdev_dbg(priv->ndev, "Error passive interrupt\n"); |
|
ti_hecc_change_state(ndev, rx_state, tx_state); |
|
} |
|
|
|
if (int_status & HECC_CANGIF_BOIF) { |
|
handled |= HECC_CANGIF_BOIF; |
|
rx_state = CAN_STATE_BUS_OFF; |
|
tx_state = CAN_STATE_BUS_OFF; |
|
netdev_dbg(priv->ndev, "Bus off interrupt\n"); |
|
|
|
/* Disable all interrupts */ |
|
hecc_write(priv, HECC_CANGIM, 0); |
|
can_bus_off(ndev); |
|
ti_hecc_change_state(ndev, rx_state, tx_state); |
|
} |
|
} else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) { |
|
enum can_state new_state, tx_state, rx_state; |
|
u32 rec = hecc_read(priv, HECC_CANREC); |
|
u32 tec = hecc_read(priv, HECC_CANTEC); |
|
|
|
if (rec >= 128 || tec >= 128) |
|
new_state = CAN_STATE_ERROR_PASSIVE; |
|
else if (rec >= 96 || tec >= 96) |
|
new_state = CAN_STATE_ERROR_WARNING; |
|
else |
|
new_state = CAN_STATE_ERROR_ACTIVE; |
|
|
|
if (new_state < priv->can.state) { |
|
rx_state = rec >= tec ? new_state : 0; |
|
tx_state = rec <= tec ? new_state : 0; |
|
ti_hecc_change_state(ndev, rx_state, tx_state); |
|
} |
|
} |
|
|
|
if (int_status & HECC_CANGIF_GMIF) { |
|
while (priv->tx_tail - priv->tx_head > 0) { |
|
mbxno = get_tx_tail_mb(priv); |
|
mbx_mask = BIT(mbxno); |
|
if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) |
|
break; |
|
hecc_write(priv, HECC_CANTA, mbx_mask); |
|
spin_lock_irqsave(&priv->mbx_lock, flags); |
|
hecc_clear_bit(priv, HECC_CANME, mbx_mask); |
|
spin_unlock_irqrestore(&priv->mbx_lock, flags); |
|
stamp = hecc_read_stamp(priv, mbxno); |
|
stats->tx_bytes += |
|
can_rx_offload_get_echo_skb(&priv->offload, |
|
mbxno, stamp, NULL); |
|
stats->tx_packets++; |
|
can_led_event(ndev, CAN_LED_EVENT_TX); |
|
--priv->tx_tail; |
|
} |
|
|
|
/* restart queue if wrap-up or if queue stalled on last pkt */ |
|
if ((priv->tx_head == priv->tx_tail && |
|
((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || |
|
(((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && |
|
((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) |
|
netif_wake_queue(ndev); |
|
|
|
/* offload RX mailboxes and let NAPI deliver them */ |
|
while ((rx_pending = hecc_read(priv, HECC_CANRMP))) { |
|
can_rx_offload_irq_offload_timestamp(&priv->offload, |
|
rx_pending); |
|
} |
|
} |
|
|
|
/* clear all interrupt conditions - read back to avoid spurious ints */ |
|
if (priv->use_hecc1int) { |
|
hecc_write(priv, HECC_CANGIF1, handled); |
|
int_status = hecc_read(priv, HECC_CANGIF1); |
|
} else { |
|
hecc_write(priv, HECC_CANGIF0, handled); |
|
int_status = hecc_read(priv, HECC_CANGIF0); |
|
} |
|
|
|
can_rx_offload_irq_finish(&priv->offload); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int ti_hecc_open(struct net_device *ndev) |
|
{ |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
int err; |
|
|
|
err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, |
|
ndev->name, ndev); |
|
if (err) { |
|
netdev_err(ndev, "error requesting interrupt\n"); |
|
return err; |
|
} |
|
|
|
ti_hecc_transceiver_switch(priv, 1); |
|
|
|
/* Open common can device */ |
|
err = open_candev(ndev); |
|
if (err) { |
|
netdev_err(ndev, "open_candev() failed %d\n", err); |
|
ti_hecc_transceiver_switch(priv, 0); |
|
free_irq(ndev->irq, ndev); |
|
return err; |
|
} |
|
|
|
can_led_event(ndev, CAN_LED_EVENT_OPEN); |
|
|
|
ti_hecc_start(ndev); |
|
can_rx_offload_enable(&priv->offload); |
|
netif_start_queue(ndev); |
|
|
|
return 0; |
|
} |
|
|
|
static int ti_hecc_close(struct net_device *ndev) |
|
{ |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
|
|
netif_stop_queue(ndev); |
|
can_rx_offload_disable(&priv->offload); |
|
ti_hecc_stop(ndev); |
|
free_irq(ndev->irq, ndev); |
|
close_candev(ndev); |
|
ti_hecc_transceiver_switch(priv, 0); |
|
|
|
can_led_event(ndev, CAN_LED_EVENT_STOP); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct net_device_ops ti_hecc_netdev_ops = { |
|
.ndo_open = ti_hecc_open, |
|
.ndo_stop = ti_hecc_close, |
|
.ndo_start_xmit = ti_hecc_xmit, |
|
.ndo_change_mtu = can_change_mtu, |
|
}; |
|
|
|
static const struct of_device_id ti_hecc_dt_ids[] = { |
|
{ |
|
.compatible = "ti,am3517-hecc", |
|
}, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids); |
|
|
|
static int ti_hecc_probe(struct platform_device *pdev) |
|
{ |
|
struct net_device *ndev = (struct net_device *)0; |
|
struct ti_hecc_priv *priv; |
|
struct device_node *np = pdev->dev.of_node; |
|
struct resource *irq; |
|
struct regulator *reg_xceiver; |
|
int err = -ENODEV; |
|
|
|
if (!IS_ENABLED(CONFIG_OF) || !np) |
|
return -EINVAL; |
|
|
|
reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); |
|
if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) |
|
return -EPROBE_DEFER; |
|
else if (IS_ERR(reg_xceiver)) |
|
reg_xceiver = NULL; |
|
|
|
ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); |
|
if (!ndev) { |
|
dev_err(&pdev->dev, "alloc_candev failed\n"); |
|
return -ENOMEM; |
|
} |
|
priv = netdev_priv(ndev); |
|
|
|
/* handle hecc memory */ |
|
priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc"); |
|
if (IS_ERR(priv->base)) { |
|
dev_err(&pdev->dev, "hecc ioremap failed\n"); |
|
err = PTR_ERR(priv->base); |
|
goto probe_exit_candev; |
|
} |
|
|
|
/* handle hecc-ram memory */ |
|
priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev, |
|
"hecc-ram"); |
|
if (IS_ERR(priv->hecc_ram)) { |
|
dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); |
|
err = PTR_ERR(priv->hecc_ram); |
|
goto probe_exit_candev; |
|
} |
|
|
|
/* handle mbx memory */ |
|
priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx"); |
|
if (IS_ERR(priv->mbx)) { |
|
dev_err(&pdev->dev, "mbx ioremap failed\n"); |
|
err = PTR_ERR(priv->mbx); |
|
goto probe_exit_candev; |
|
} |
|
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
|
if (!irq) { |
|
dev_err(&pdev->dev, "No irq resource\n"); |
|
goto probe_exit_candev; |
|
} |
|
|
|
priv->ndev = ndev; |
|
priv->reg_xceiver = reg_xceiver; |
|
priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); |
|
|
|
priv->can.bittiming_const = &ti_hecc_bittiming_const; |
|
priv->can.do_set_mode = ti_hecc_do_set_mode; |
|
priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; |
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; |
|
|
|
spin_lock_init(&priv->mbx_lock); |
|
ndev->irq = irq->start; |
|
ndev->flags |= IFF_ECHO; |
|
platform_set_drvdata(pdev, ndev); |
|
SET_NETDEV_DEV(ndev, &pdev->dev); |
|
ndev->netdev_ops = &ti_hecc_netdev_ops; |
|
|
|
priv->clk = clk_get(&pdev->dev, "hecc_ck"); |
|
if (IS_ERR(priv->clk)) { |
|
dev_err(&pdev->dev, "No clock available\n"); |
|
err = PTR_ERR(priv->clk); |
|
priv->clk = NULL; |
|
goto probe_exit_candev; |
|
} |
|
priv->can.clock.freq = clk_get_rate(priv->clk); |
|
|
|
err = clk_prepare_enable(priv->clk); |
|
if (err) { |
|
dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); |
|
goto probe_exit_release_clk; |
|
} |
|
|
|
priv->offload.mailbox_read = ti_hecc_mailbox_read; |
|
priv->offload.mb_first = HECC_RX_FIRST_MBOX; |
|
priv->offload.mb_last = HECC_RX_LAST_MBOX; |
|
err = can_rx_offload_add_timestamp(ndev, &priv->offload); |
|
if (err) { |
|
dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n"); |
|
goto probe_exit_disable_clk; |
|
} |
|
|
|
err = register_candev(ndev); |
|
if (err) { |
|
dev_err(&pdev->dev, "register_candev() failed\n"); |
|
goto probe_exit_offload; |
|
} |
|
|
|
devm_can_led_init(ndev); |
|
|
|
dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", |
|
priv->base, (u32)ndev->irq); |
|
|
|
return 0; |
|
|
|
probe_exit_offload: |
|
can_rx_offload_del(&priv->offload); |
|
probe_exit_disable_clk: |
|
clk_disable_unprepare(priv->clk); |
|
probe_exit_release_clk: |
|
clk_put(priv->clk); |
|
probe_exit_candev: |
|
free_candev(ndev); |
|
|
|
return err; |
|
} |
|
|
|
static int ti_hecc_remove(struct platform_device *pdev) |
|
{ |
|
struct net_device *ndev = platform_get_drvdata(pdev); |
|
struct ti_hecc_priv *priv = netdev_priv(ndev); |
|
|
|
unregister_candev(ndev); |
|
clk_disable_unprepare(priv->clk); |
|
clk_put(priv->clk); |
|
can_rx_offload_del(&priv->offload); |
|
free_candev(ndev); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state) |
|
{ |
|
struct net_device *dev = platform_get_drvdata(pdev); |
|
struct ti_hecc_priv *priv = netdev_priv(dev); |
|
|
|
if (netif_running(dev)) { |
|
netif_stop_queue(dev); |
|
netif_device_detach(dev); |
|
} |
|
|
|
hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR); |
|
priv->can.state = CAN_STATE_SLEEPING; |
|
|
|
clk_disable_unprepare(priv->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int ti_hecc_resume(struct platform_device *pdev) |
|
{ |
|
struct net_device *dev = platform_get_drvdata(pdev); |
|
struct ti_hecc_priv *priv = netdev_priv(dev); |
|
int err; |
|
|
|
err = clk_prepare_enable(priv->clk); |
|
if (err) |
|
return err; |
|
|
|
hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR); |
|
priv->can.state = CAN_STATE_ERROR_ACTIVE; |
|
|
|
if (netif_running(dev)) { |
|
netif_device_attach(dev); |
|
netif_start_queue(dev); |
|
} |
|
|
|
return 0; |
|
} |
|
#else |
|
#define ti_hecc_suspend NULL |
|
#define ti_hecc_resume NULL |
|
#endif |
|
|
|
/* TI HECC netdevice driver: platform driver structure */ |
|
static struct platform_driver ti_hecc_driver = { |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = ti_hecc_dt_ids, |
|
}, |
|
.probe = ti_hecc_probe, |
|
.remove = ti_hecc_remove, |
|
.suspend = ti_hecc_suspend, |
|
.resume = ti_hecc_resume, |
|
}; |
|
|
|
module_platform_driver(ti_hecc_driver); |
|
|
|
MODULE_AUTHOR("Anant Gole <[email protected]>"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION(DRV_DESC); |
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
|