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239 lines
7.2 KiB
239 lines
7.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* MTD map driver for BIOS Flash on Intel SCB2 boards |
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* Copyright (C) 2002 Sun Microsystems, Inc. |
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* Tim Hockin <[email protected]> |
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* |
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* A few notes on this MTD map: |
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* |
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* This was developed with a small number of SCB2 boards to test on. |
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* Hopefully, Intel has not introducted too many unaccounted variables in the |
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* making of this board. |
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* |
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* The BIOS marks its own memory region as 'reserved' in the e820 map. We |
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* try to request it here, but if it fails, we carry on anyway. |
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* |
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* This is how the chip is attached, so said the schematic: |
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* * a 4 MiB (32 Mib) 16 bit chip |
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* * a 1 MiB memory region |
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* * A20 and A21 pulled up |
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* * D8-D15 ignored |
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* What this means is that, while we are addressing bytes linearly, we are |
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* really addressing words, and discarding the other byte. This means that |
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* the chip MUST BE at least 2 MiB. This also means that every block is |
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* actually half as big as the chip reports. It also means that accesses of |
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* logical address 0 hit higher-address sections of the chip, not physical 0. |
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* One can only hope that these 4MiB x16 chips were a lot cheaper than 1MiB x8 |
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* chips. |
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* |
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* This driver assumes the chip is not write-protected by an external signal. |
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* As of the this writing, that is true, but may change, just to spite me. |
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* |
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* The actual BIOS layout has been mostly reverse engineered. Intel BIOS |
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* updates for this board include 10 related (*.bio - &.bi9) binary files and |
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* another separate (*.bbo) binary file. The 10 files are 64k of data + a |
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* small header. If the headers are stripped off, the 10 64k files can be |
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* concatenated into a 640k image. This is your BIOS image, proper. The |
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* separate .bbo file also has a small header. It is the 'Boot Block' |
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* recovery BIOS. Once the header is stripped, no further prep is needed. |
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* As best I can tell, the BIOS is arranged as such: |
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* offset 0x00000 to 0x4ffff (320k): unknown - SCSI BIOS, etc? |
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* offset 0x50000 to 0xeffff (640k): BIOS proper |
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* offset 0xf0000 ty 0xfffff (64k): Boot Block region |
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* |
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* Intel's BIOS update program flashes the BIOS and Boot Block in separate |
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* steps. Probably a wise thing to do. |
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*/ |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <asm/io.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/map.h> |
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#include <linux/mtd/cfi.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#define MODNAME "scb2_flash" |
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#define SCB2_ADDR 0xfff00000 |
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#define SCB2_WINDOW 0x00100000 |
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static void __iomem *scb2_ioaddr; |
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static struct mtd_info *scb2_mtd; |
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static struct map_info scb2_map = { |
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.name = "SCB2 BIOS Flash", |
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.size = 0, |
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.bankwidth = 1, |
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}; |
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static int region_fail; |
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static int scb2_fixup_mtd(struct mtd_info *mtd) |
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{ |
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int i; |
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int done = 0; |
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struct map_info *map = mtd->priv; |
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struct cfi_private *cfi = map->fldrv_priv; |
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/* barf if this doesn't look right */ |
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if (cfi->cfiq->InterfaceDesc != CFI_INTERFACE_X16_ASYNC) { |
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printk(KERN_ERR MODNAME ": unsupported InterfaceDesc: %#x\n", |
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cfi->cfiq->InterfaceDesc); |
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return -1; |
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} |
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/* I wasn't here. I didn't see. dwmw2. */ |
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/* the chip is sometimes bigger than the map - what a waste */ |
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mtd->size = map->size; |
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/* |
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* We only REALLY get half the chip, due to the way it is |
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* wired up - D8-D15 are tossed away. We read linear bytes, |
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* but in reality we are getting 1/2 of each 16-bit read, |
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* which LOOKS linear to us. Because CFI code accounts for |
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* things like lock/unlock/erase by eraseregions, we need to |
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* fudge them to reflect this. Erases go like this: |
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* * send an erase to an address |
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* * the chip samples the address and erases the block |
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* * add the block erasesize to the address and repeat |
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* -- the problem is that addresses are 16-bit addressable |
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* -- we end up erasing every-other block |
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*/ |
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mtd->erasesize /= 2; |
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for (i = 0; i < mtd->numeraseregions; i++) { |
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struct mtd_erase_region_info *region = &mtd->eraseregions[i]; |
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region->erasesize /= 2; |
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} |
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/* |
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* If the chip is bigger than the map, it is wired with the high |
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* address lines pulled up. This makes us access the top portion of |
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* the chip, so all our erase-region info is wrong. Start cutting from |
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* the bottom. |
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*/ |
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for (i = 0; !done && i < mtd->numeraseregions; i++) { |
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struct mtd_erase_region_info *region = &mtd->eraseregions[i]; |
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if (region->numblocks * region->erasesize > mtd->size) { |
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region->numblocks = ((unsigned long)mtd->size / |
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region->erasesize); |
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done = 1; |
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} else { |
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region->numblocks = 0; |
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} |
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region->offset = 0; |
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} |
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return 0; |
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} |
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/* CSB5's 'Function Control Register' has bits for decoding @ >= 0xffc00000 */ |
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#define CSB5_FCR 0x41 |
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#define CSB5_FCR_DECODE_ALL 0x0e |
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static int scb2_flash_probe(struct pci_dev *dev, |
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const struct pci_device_id *ent) |
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{ |
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u8 reg; |
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/* enable decoding of the flash region in the south bridge */ |
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pci_read_config_byte(dev, CSB5_FCR, ®); |
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pci_write_config_byte(dev, CSB5_FCR, reg | CSB5_FCR_DECODE_ALL); |
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if (!request_mem_region(SCB2_ADDR, SCB2_WINDOW, scb2_map.name)) { |
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/* |
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* The BIOS seems to mark the flash region as 'reserved' |
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* in the e820 map. Warn and go about our business. |
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*/ |
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printk(KERN_WARNING MODNAME |
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": warning - can't reserve rom window, continuing\n"); |
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region_fail = 1; |
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} |
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/* remap the IO window (w/o caching) */ |
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scb2_ioaddr = ioremap(SCB2_ADDR, SCB2_WINDOW); |
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if (!scb2_ioaddr) { |
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printk(KERN_ERR MODNAME ": Failed to ioremap window!\n"); |
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if (!region_fail) |
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release_mem_region(SCB2_ADDR, SCB2_WINDOW); |
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return -ENOMEM; |
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} |
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scb2_map.phys = SCB2_ADDR; |
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scb2_map.virt = scb2_ioaddr; |
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scb2_map.size = SCB2_WINDOW; |
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simple_map_init(&scb2_map); |
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/* try to find a chip */ |
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scb2_mtd = do_map_probe("cfi_probe", &scb2_map); |
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if (!scb2_mtd) { |
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printk(KERN_ERR MODNAME ": flash probe failed!\n"); |
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iounmap(scb2_ioaddr); |
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if (!region_fail) |
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release_mem_region(SCB2_ADDR, SCB2_WINDOW); |
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return -ENODEV; |
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} |
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scb2_mtd->owner = THIS_MODULE; |
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if (scb2_fixup_mtd(scb2_mtd) < 0) { |
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mtd_device_unregister(scb2_mtd); |
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map_destroy(scb2_mtd); |
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iounmap(scb2_ioaddr); |
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if (!region_fail) |
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release_mem_region(SCB2_ADDR, SCB2_WINDOW); |
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return -ENODEV; |
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} |
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printk(KERN_NOTICE MODNAME ": chip size 0x%llx at offset 0x%llx\n", |
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(unsigned long long)scb2_mtd->size, |
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(unsigned long long)(SCB2_WINDOW - scb2_mtd->size)); |
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mtd_device_register(scb2_mtd, NULL, 0); |
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return 0; |
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} |
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static void scb2_flash_remove(struct pci_dev *dev) |
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{ |
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if (!scb2_mtd) |
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return; |
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/* disable flash writes */ |
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mtd_lock(scb2_mtd, 0, scb2_mtd->size); |
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mtd_device_unregister(scb2_mtd); |
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map_destroy(scb2_mtd); |
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iounmap(scb2_ioaddr); |
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scb2_ioaddr = NULL; |
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if (!region_fail) |
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release_mem_region(SCB2_ADDR, SCB2_WINDOW); |
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} |
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static struct pci_device_id scb2_flash_pci_ids[] = { |
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{ |
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.vendor = PCI_VENDOR_ID_SERVERWORKS, |
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.device = PCI_DEVICE_ID_SERVERWORKS_CSB5, |
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.subvendor = PCI_ANY_ID, |
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.subdevice = PCI_ANY_ID |
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}, |
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{ 0, } |
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}; |
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static struct pci_driver scb2_flash_driver = { |
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.name = "Intel SCB2 BIOS Flash", |
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.id_table = scb2_flash_pci_ids, |
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.probe = scb2_flash_probe, |
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.remove = scb2_flash_remove, |
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}; |
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module_pci_driver(scb2_flash_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Tim Hockin <[email protected]>"); |
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MODULE_DESCRIPTION("MTD map driver for Intel SCB2 BIOS Flash"); |
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MODULE_DEVICE_TABLE(pci, scb2_flash_pci_ids);
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