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614 lines
13 KiB
614 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* sun_esp.c: ESP front-end for Sparc SBUS systems. |
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* |
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* Copyright (C) 2007, 2008 David S. Miller ([email protected]) |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/delay.h> |
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#include <linux/module.h> |
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#include <linux/mm.h> |
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#include <linux/init.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/gfp.h> |
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#include <asm/irq.h> |
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#include <asm/io.h> |
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#include <asm/dma.h> |
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#include <scsi/scsi_host.h> |
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#include "esp_scsi.h" |
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#define DRV_MODULE_NAME "sun_esp" |
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#define PFX DRV_MODULE_NAME ": " |
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#define DRV_VERSION "1.100" |
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#define DRV_MODULE_RELDATE "August 27, 2008" |
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#define dma_read32(REG) \ |
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sbus_readl(esp->dma_regs + (REG)) |
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#define dma_write32(VAL, REG) \ |
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sbus_writel((VAL), esp->dma_regs + (REG)) |
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/* DVMA chip revisions */ |
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enum dvma_rev { |
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dvmarev0, |
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dvmaesc1, |
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dvmarev1, |
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dvmarev2, |
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dvmarev3, |
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dvmarevplus, |
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dvmahme |
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}; |
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static int esp_sbus_setup_dma(struct esp *esp, struct platform_device *dma_of) |
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{ |
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esp->dma = dma_of; |
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esp->dma_regs = of_ioremap(&dma_of->resource[0], 0, |
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resource_size(&dma_of->resource[0]), |
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"espdma"); |
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if (!esp->dma_regs) |
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return -ENOMEM; |
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switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) { |
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case DMA_VERS0: |
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esp->dmarev = dvmarev0; |
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break; |
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case DMA_ESCV1: |
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esp->dmarev = dvmaesc1; |
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break; |
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case DMA_VERS1: |
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esp->dmarev = dvmarev1; |
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break; |
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case DMA_VERS2: |
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esp->dmarev = dvmarev2; |
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break; |
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case DMA_VERHME: |
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esp->dmarev = dvmahme; |
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break; |
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case DMA_VERSPLUS: |
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esp->dmarev = dvmarevplus; |
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break; |
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} |
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return 0; |
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} |
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static int esp_sbus_map_regs(struct esp *esp, int hme) |
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{ |
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struct platform_device *op = to_platform_device(esp->dev); |
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struct resource *res; |
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/* On HME, two reg sets exist, first is DVMA, |
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* second is ESP registers. |
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*/ |
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if (hme) |
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res = &op->resource[1]; |
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else |
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res = &op->resource[0]; |
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esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP"); |
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if (!esp->regs) |
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return -ENOMEM; |
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return 0; |
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} |
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static int esp_sbus_map_command_block(struct esp *esp) |
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{ |
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esp->command_block = dma_alloc_coherent(esp->dev, 16, |
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&esp->command_block_dma, |
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GFP_KERNEL); |
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if (!esp->command_block) |
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return -ENOMEM; |
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return 0; |
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} |
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static int esp_sbus_register_irq(struct esp *esp) |
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{ |
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struct Scsi_Host *host = esp->host; |
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struct platform_device *op = to_platform_device(esp->dev); |
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host->irq = op->archdata.irqs[0]; |
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return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp); |
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} |
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static void esp_get_scsi_id(struct esp *esp, struct platform_device *espdma) |
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{ |
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struct platform_device *op = to_platform_device(esp->dev); |
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struct device_node *dp; |
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dp = op->dev.of_node; |
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esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff); |
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if (esp->scsi_id != 0xff) |
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goto done; |
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esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff); |
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if (esp->scsi_id != 0xff) |
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goto done; |
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esp->scsi_id = of_getintprop_default(espdma->dev.of_node, |
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"scsi-initiator-id", 7); |
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done: |
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esp->host->this_id = esp->scsi_id; |
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esp->scsi_id_mask = (1 << esp->scsi_id); |
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} |
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static void esp_get_differential(struct esp *esp) |
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{ |
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struct platform_device *op = to_platform_device(esp->dev); |
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struct device_node *dp; |
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dp = op->dev.of_node; |
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if (of_find_property(dp, "differential", NULL)) |
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esp->flags |= ESP_FLAG_DIFFERENTIAL; |
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else |
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esp->flags &= ~ESP_FLAG_DIFFERENTIAL; |
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} |
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static void esp_get_clock_params(struct esp *esp) |
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{ |
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struct platform_device *op = to_platform_device(esp->dev); |
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struct device_node *bus_dp, *dp; |
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int fmhz; |
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dp = op->dev.of_node; |
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bus_dp = dp->parent; |
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fmhz = of_getintprop_default(dp, "clock-frequency", 0); |
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if (fmhz == 0) |
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fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0); |
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esp->cfreq = fmhz; |
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} |
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static void esp_get_bursts(struct esp *esp, struct platform_device *dma_of) |
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{ |
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struct device_node *dma_dp = dma_of->dev.of_node; |
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struct platform_device *op = to_platform_device(esp->dev); |
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struct device_node *dp; |
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u8 bursts, val; |
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dp = op->dev.of_node; |
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bursts = of_getintprop_default(dp, "burst-sizes", 0xff); |
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val = of_getintprop_default(dma_dp, "burst-sizes", 0xff); |
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if (val != 0xff) |
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bursts &= val; |
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val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff); |
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if (val != 0xff) |
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bursts &= val; |
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if (bursts == 0xff || |
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(bursts & DMA_BURST16) == 0 || |
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(bursts & DMA_BURST32) == 0) |
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bursts = (DMA_BURST32 - 1); |
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esp->bursts = bursts; |
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} |
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static void esp_sbus_get_props(struct esp *esp, struct platform_device *espdma) |
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{ |
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esp_get_scsi_id(esp, espdma); |
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esp_get_differential(esp); |
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esp_get_clock_params(esp); |
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esp_get_bursts(esp, espdma); |
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} |
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static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg) |
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{ |
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sbus_writeb(val, esp->regs + (reg * 4UL)); |
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} |
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static u8 sbus_esp_read8(struct esp *esp, unsigned long reg) |
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{ |
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return sbus_readb(esp->regs + (reg * 4UL)); |
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} |
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static int sbus_esp_irq_pending(struct esp *esp) |
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{ |
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if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)) |
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return 1; |
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return 0; |
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} |
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static void sbus_esp_reset_dma(struct esp *esp) |
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{ |
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int can_do_burst16, can_do_burst32, can_do_burst64; |
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int can_do_sbus64, lim; |
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struct platform_device *op = to_platform_device(esp->dev); |
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u32 val; |
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can_do_burst16 = (esp->bursts & DMA_BURST16) != 0; |
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can_do_burst32 = (esp->bursts & DMA_BURST32) != 0; |
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can_do_burst64 = 0; |
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can_do_sbus64 = 0; |
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if (sbus_can_dma_64bit()) |
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can_do_sbus64 = 1; |
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if (sbus_can_burst64()) |
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can_do_burst64 = (esp->bursts & DMA_BURST64) != 0; |
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/* Put the DVMA into a known state. */ |
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if (esp->dmarev != dvmahme) { |
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val = dma_read32(DMA_CSR); |
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dma_write32(val | DMA_RST_SCSI, DMA_CSR); |
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dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); |
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} |
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switch (esp->dmarev) { |
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case dvmahme: |
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dma_write32(DMA_RESET_FAS366, DMA_CSR); |
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dma_write32(DMA_RST_SCSI, DMA_CSR); |
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esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS | |
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DMA_SCSI_DISAB | DMA_INT_ENAB); |
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esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE | |
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DMA_BRST_SZ); |
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if (can_do_burst64) |
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esp->prev_hme_dmacsr |= DMA_BRST64; |
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else if (can_do_burst32) |
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esp->prev_hme_dmacsr |= DMA_BRST32; |
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if (can_do_sbus64) { |
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esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64; |
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sbus_set_sbus64(&op->dev, esp->bursts); |
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} |
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lim = 1000; |
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while (dma_read32(DMA_CSR) & DMA_PEND_READ) { |
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if (--lim == 0) { |
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printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ " |
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"will not clear!\n", |
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esp->host->unique_id); |
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break; |
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} |
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udelay(1); |
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} |
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dma_write32(0, DMA_CSR); |
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dma_write32(esp->prev_hme_dmacsr, DMA_CSR); |
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dma_write32(0, DMA_ADDR); |
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break; |
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case dvmarev2: |
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if (esp->rev != ESP100) { |
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val = dma_read32(DMA_CSR); |
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dma_write32(val | DMA_3CLKS, DMA_CSR); |
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} |
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break; |
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case dvmarev3: |
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val = dma_read32(DMA_CSR); |
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val &= ~DMA_3CLKS; |
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val |= DMA_2CLKS; |
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if (can_do_burst32) { |
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val &= ~DMA_BRST_SZ; |
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val |= DMA_BRST32; |
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} |
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dma_write32(val, DMA_CSR); |
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break; |
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case dvmaesc1: |
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val = dma_read32(DMA_CSR); |
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val |= DMA_ADD_ENABLE; |
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val &= ~DMA_BCNT_ENAB; |
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if (!can_do_burst32 && can_do_burst16) { |
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val |= DMA_ESC_BURST; |
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} else { |
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val &= ~(DMA_ESC_BURST); |
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} |
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dma_write32(val, DMA_CSR); |
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break; |
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default: |
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break; |
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} |
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/* Enable interrupts. */ |
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val = dma_read32(DMA_CSR); |
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dma_write32(val | DMA_INT_ENAB, DMA_CSR); |
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} |
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static void sbus_esp_dma_drain(struct esp *esp) |
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{ |
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u32 csr; |
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int lim; |
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if (esp->dmarev == dvmahme) |
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return; |
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csr = dma_read32(DMA_CSR); |
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if (!(csr & DMA_FIFO_ISDRAIN)) |
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return; |
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if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1) |
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dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); |
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lim = 1000; |
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while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) { |
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if (--lim == 0) { |
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printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n", |
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esp->host->unique_id); |
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break; |
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} |
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udelay(1); |
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} |
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} |
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static void sbus_esp_dma_invalidate(struct esp *esp) |
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{ |
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if (esp->dmarev == dvmahme) { |
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dma_write32(DMA_RST_SCSI, DMA_CSR); |
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esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr | |
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(DMA_PARITY_OFF | DMA_2CLKS | |
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DMA_SCSI_DISAB | DMA_INT_ENAB)) & |
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~(DMA_ST_WRITE | DMA_ENABLE)); |
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dma_write32(0, DMA_CSR); |
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dma_write32(esp->prev_hme_dmacsr, DMA_CSR); |
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/* This is necessary to avoid having the SCSI channel |
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* engine lock up on us. |
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*/ |
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dma_write32(0, DMA_ADDR); |
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} else { |
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u32 val; |
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int lim; |
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lim = 1000; |
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while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) { |
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if (--lim == 0) { |
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printk(KERN_ALERT PFX "esp%d: DMA will not " |
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"invalidate!\n", esp->host->unique_id); |
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break; |
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} |
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udelay(1); |
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} |
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val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB); |
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val |= DMA_FIFO_INV; |
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dma_write32(val, DMA_CSR); |
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val &= ~DMA_FIFO_INV; |
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dma_write32(val, DMA_CSR); |
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} |
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} |
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static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count, |
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u32 dma_count, int write, u8 cmd) |
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{ |
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u32 csr; |
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BUG_ON(!(cmd & ESP_CMD_DMA)); |
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sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); |
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sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); |
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if (esp->rev == FASHME) { |
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sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO); |
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sbus_esp_write8(esp, 0, FAS_RHI); |
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scsi_esp_cmd(esp, cmd); |
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csr = esp->prev_hme_dmacsr; |
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csr |= DMA_SCSI_DISAB | DMA_ENABLE; |
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if (write) |
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csr |= DMA_ST_WRITE; |
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else |
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csr &= ~DMA_ST_WRITE; |
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esp->prev_hme_dmacsr = csr; |
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dma_write32(dma_count, DMA_COUNT); |
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dma_write32(addr, DMA_ADDR); |
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dma_write32(csr, DMA_CSR); |
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} else { |
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csr = dma_read32(DMA_CSR); |
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csr |= DMA_ENABLE; |
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if (write) |
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csr |= DMA_ST_WRITE; |
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else |
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csr &= ~DMA_ST_WRITE; |
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dma_write32(csr, DMA_CSR); |
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if (esp->dmarev == dvmaesc1) { |
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u32 end = PAGE_ALIGN(addr + dma_count + 16U); |
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dma_write32(end - addr, DMA_COUNT); |
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} |
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dma_write32(addr, DMA_ADDR); |
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scsi_esp_cmd(esp, cmd); |
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} |
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} |
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static int sbus_esp_dma_error(struct esp *esp) |
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{ |
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u32 csr = dma_read32(DMA_CSR); |
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if (csr & DMA_HNDL_ERROR) |
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return 1; |
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return 0; |
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} |
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static const struct esp_driver_ops sbus_esp_ops = { |
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.esp_write8 = sbus_esp_write8, |
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.esp_read8 = sbus_esp_read8, |
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.irq_pending = sbus_esp_irq_pending, |
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.reset_dma = sbus_esp_reset_dma, |
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.dma_drain = sbus_esp_dma_drain, |
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.dma_invalidate = sbus_esp_dma_invalidate, |
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.send_dma_cmd = sbus_esp_send_dma_cmd, |
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.dma_error = sbus_esp_dma_error, |
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}; |
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static int esp_sbus_probe_one(struct platform_device *op, |
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struct platform_device *espdma, int hme) |
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{ |
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struct scsi_host_template *tpnt = &scsi_esp_template; |
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struct Scsi_Host *host; |
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struct esp *esp; |
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int err; |
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host = scsi_host_alloc(tpnt, sizeof(struct esp)); |
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err = -ENOMEM; |
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if (!host) |
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goto fail; |
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host->max_id = (hme ? 16 : 8); |
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esp = shost_priv(host); |
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esp->host = host; |
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esp->dev = &op->dev; |
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esp->ops = &sbus_esp_ops; |
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if (hme) |
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esp->flags |= ESP_FLAG_WIDE_CAPABLE; |
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err = esp_sbus_setup_dma(esp, espdma); |
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if (err < 0) |
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goto fail_unlink; |
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err = esp_sbus_map_regs(esp, hme); |
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if (err < 0) |
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goto fail_unlink; |
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err = esp_sbus_map_command_block(esp); |
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if (err < 0) |
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goto fail_unmap_regs; |
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err = esp_sbus_register_irq(esp); |
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if (err < 0) |
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goto fail_unmap_command_block; |
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esp_sbus_get_props(esp, espdma); |
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|
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/* Before we try to touch the ESP chip, ESC1 dma can |
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* come up with the reset bit set, so make sure that |
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* is clear first. |
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*/ |
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if (esp->dmarev == dvmaesc1) { |
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u32 val = dma_read32(DMA_CSR); |
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dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); |
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} |
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dev_set_drvdata(&op->dev, esp); |
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err = scsi_esp_register(esp); |
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if (err) |
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goto fail_free_irq; |
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return 0; |
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|
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fail_free_irq: |
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free_irq(host->irq, esp); |
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fail_unmap_command_block: |
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dma_free_coherent(&op->dev, 16, |
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esp->command_block, |
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esp->command_block_dma); |
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fail_unmap_regs: |
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of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE); |
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fail_unlink: |
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scsi_host_put(host); |
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fail: |
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return err; |
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} |
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static int esp_sbus_probe(struct platform_device *op) |
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{ |
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struct device_node *dma_node = NULL; |
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struct device_node *dp = op->dev.of_node; |
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struct platform_device *dma_of = NULL; |
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int hme = 0; |
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int ret; |
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if (of_node_name_eq(dp->parent, "espdma") || |
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of_node_name_eq(dp->parent, "dma")) |
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dma_node = dp->parent; |
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else if (of_node_name_eq(dp, "SUNW,fas")) { |
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dma_node = op->dev.of_node; |
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hme = 1; |
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} |
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if (dma_node) |
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dma_of = of_find_device_by_node(dma_node); |
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if (!dma_of) |
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return -ENODEV; |
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ret = esp_sbus_probe_one(op, dma_of, hme); |
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if (ret) |
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put_device(&dma_of->dev); |
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return ret; |
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} |
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static int esp_sbus_remove(struct platform_device *op) |
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{ |
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struct esp *esp = dev_get_drvdata(&op->dev); |
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struct platform_device *dma_of = esp->dma; |
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unsigned int irq = esp->host->irq; |
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bool is_hme; |
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u32 val; |
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|
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scsi_esp_unregister(esp); |
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|
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/* Disable interrupts. */ |
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val = dma_read32(DMA_CSR); |
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dma_write32(val & ~DMA_INT_ENAB, DMA_CSR); |
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|
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free_irq(irq, esp); |
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is_hme = (esp->dmarev == dvmahme); |
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|
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dma_free_coherent(&op->dev, 16, |
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esp->command_block, |
|
esp->command_block_dma); |
|
of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs, |
|
SBUS_ESP_REG_SIZE); |
|
of_iounmap(&dma_of->resource[0], esp->dma_regs, |
|
resource_size(&dma_of->resource[0])); |
|
|
|
scsi_host_put(esp->host); |
|
|
|
dev_set_drvdata(&op->dev, NULL); |
|
|
|
put_device(&dma_of->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id esp_match[] = { |
|
{ |
|
.name = "SUNW,esp", |
|
}, |
|
{ |
|
.name = "SUNW,fas", |
|
}, |
|
{ |
|
.name = "esp", |
|
}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, esp_match); |
|
|
|
static struct platform_driver esp_sbus_driver = { |
|
.driver = { |
|
.name = "esp", |
|
.of_match_table = esp_match, |
|
}, |
|
.probe = esp_sbus_probe, |
|
.remove = esp_sbus_remove, |
|
}; |
|
module_platform_driver(esp_sbus_driver); |
|
|
|
MODULE_DESCRIPTION("Sun ESP SCSI driver"); |
|
MODULE_AUTHOR("David S. Miller ([email protected])"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_VERSION(DRV_VERSION);
|
|
|