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764 lines
19 KiB
764 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2021 Broadcom. All Rights Reserved. The term |
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* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. |
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*/ |
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|
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#ifndef _EFCT_HW_H |
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#define _EFCT_HW_H |
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|
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#include "../libefc_sli/sli4.h" |
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|
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/* |
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* EFCT PCI IDs |
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*/ |
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#define EFCT_VENDOR_ID 0x10df |
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/* LightPulse 16Gb x 4 FC (lancer-g6) */ |
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#define EFCT_DEVICE_LANCER_G6 0xe307 |
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/* LightPulse 32Gb x 4 FC (lancer-g7) */ |
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#define EFCT_DEVICE_LANCER_G7 0xf407 |
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/*Default RQ entries len used by driver*/ |
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#define EFCT_HW_RQ_ENTRIES_MIN 512 |
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#define EFCT_HW_RQ_ENTRIES_DEF 1024 |
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#define EFCT_HW_RQ_ENTRIES_MAX 4096 |
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|
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/*Defines the size of the RQ buffers used for each RQ*/ |
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#define EFCT_HW_RQ_SIZE_HDR 128 |
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#define EFCT_HW_RQ_SIZE_PAYLOAD 1024 |
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|
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/*Define the maximum number of multi-receive queues*/ |
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#define EFCT_HW_MAX_MRQS 8 |
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|
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/* |
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* Define count of when to set the WQEC bit in a submitted |
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* WQE, causing a consummed/released completion to be posted. |
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*/ |
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#define EFCT_HW_WQEC_SET_COUNT 32 |
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|
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/*Send frame timeout in seconds*/ |
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#define EFCT_HW_SEND_FRAME_TIMEOUT 10 |
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/* |
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* FDT Transfer Hint value, reads greater than this value |
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* will be segmented to implement fairness. A value of zero disables |
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* the feature. |
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*/ |
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#define EFCT_HW_FDT_XFER_HINT 8192 |
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#define EFCT_HW_TIMECHECK_ITERATIONS 100 |
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#define EFCT_HW_MAX_NUM_MQ 1 |
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#define EFCT_HW_MAX_NUM_RQ 32 |
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#define EFCT_HW_MAX_NUM_EQ 16 |
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#define EFCT_HW_MAX_NUM_WQ 32 |
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#define EFCT_HW_DEF_NUM_EQ 1 |
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#define OCE_HW_MAX_NUM_MRQ_PAIRS 16 |
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#define EFCT_HW_MQ_DEPTH 128 |
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#define EFCT_HW_EQ_DEPTH 1024 |
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/* |
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* A CQ will be assinged to each WQ |
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* (CQ must have 2X entries of the WQ for abort |
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* processing), plus a separate one for each RQ PAIR and one for MQ |
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*/ |
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#define EFCT_HW_MAX_NUM_CQ \ |
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((EFCT_HW_MAX_NUM_WQ * 2) + 1 + (OCE_HW_MAX_NUM_MRQ_PAIRS * 2)) |
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#define EFCT_HW_Q_HASH_SIZE 128 |
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#define EFCT_HW_RQ_HEADER_SIZE 128 |
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#define EFCT_HW_RQ_HEADER_INDEX 0 |
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#define EFCT_HW_REQUE_XRI_REGTAG 65534 |
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/* Options for efct_hw_command() */ |
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enum efct_cmd_opts { |
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/* command executes synchronously and busy-waits for completion */ |
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EFCT_CMD_POLL, |
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/* command executes asynchronously. Uses callback */ |
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EFCT_CMD_NOWAIT, |
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}; |
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enum efct_hw_reset { |
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EFCT_HW_RESET_FUNCTION, |
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EFCT_HW_RESET_FIRMWARE, |
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EFCT_HW_RESET_MAX |
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}; |
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enum efct_hw_topo { |
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EFCT_HW_TOPOLOGY_AUTO, |
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EFCT_HW_TOPOLOGY_NPORT, |
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EFCT_HW_TOPOLOGY_LOOP, |
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EFCT_HW_TOPOLOGY_NONE, |
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EFCT_HW_TOPOLOGY_MAX |
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}; |
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/* pack fw revision values into a single uint64_t */ |
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#define HW_FWREV(a, b, c, d) (((uint64_t)(a) << 48) | ((uint64_t)(b) << 32) \ |
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| ((uint64_t)(c) << 16) | ((uint64_t)(d))) |
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#define EFCT_FW_VER_STR(a, b, c, d) (#a "." #b "." #c "." #d) |
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enum efct_hw_io_type { |
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EFCT_HW_ELS_REQ, |
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EFCT_HW_ELS_RSP, |
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EFCT_HW_FC_CT, |
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EFCT_HW_FC_CT_RSP, |
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EFCT_HW_BLS_ACC, |
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EFCT_HW_BLS_RJT, |
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EFCT_HW_IO_TARGET_READ, |
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EFCT_HW_IO_TARGET_WRITE, |
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EFCT_HW_IO_TARGET_RSP, |
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EFCT_HW_IO_DNRX_REQUEUE, |
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EFCT_HW_IO_MAX, |
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}; |
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enum efct_hw_io_state { |
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EFCT_HW_IO_STATE_FREE, |
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EFCT_HW_IO_STATE_INUSE, |
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EFCT_HW_IO_STATE_WAIT_FREE, |
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EFCT_HW_IO_STATE_WAIT_SEC_HIO, |
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}; |
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#define EFCT_TARGET_WRITE_SKIPS 1 |
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#define EFCT_TARGET_READ_SKIPS 2 |
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struct efct_hw; |
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struct efct_io; |
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#define EFCT_CMD_CTX_POOL_SZ 32 |
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/** |
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* HW command context. |
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* Stores the state for the asynchronous commands sent to the hardware. |
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*/ |
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struct efct_command_ctx { |
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struct list_head list_entry; |
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int (*cb)(struct efct_hw *hw, int status, u8 *mqe, void *arg); |
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void *arg; /* Argument for callback */ |
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/* buffer holding command / results */ |
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u8 buf[SLI4_BMBX_SIZE]; |
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void *ctx; /* upper layer context */ |
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}; |
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struct efct_hw_sgl { |
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uintptr_t addr; |
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size_t len; |
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}; |
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union efct_hw_io_param_u { |
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struct sli_bls_params bls; |
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struct sli_els_params els; |
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struct sli_ct_params fc_ct; |
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struct sli_fcp_tgt_params fcp_tgt; |
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}; |
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/* WQ steering mode */ |
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enum efct_hw_wq_steering { |
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EFCT_HW_WQ_STEERING_CLASS, |
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EFCT_HW_WQ_STEERING_REQUEST, |
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EFCT_HW_WQ_STEERING_CPU, |
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}; |
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/* HW wqe object */ |
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struct efct_hw_wqe { |
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struct list_head list_entry; |
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bool abort_wqe_submit_needed; |
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bool send_abts; |
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u32 id; |
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u32 abort_reqtag; |
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u8 *wqebuf; |
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}; |
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struct efct_hw_io; |
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/* Typedef for HW "done" callback */ |
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typedef int (*efct_hw_done_t)(struct efct_hw_io *, u32 len, int status, |
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u32 ext, void *ul_arg); |
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/** |
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* HW IO object. |
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* |
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* Stores the per-IO information necessary |
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* for both SLI and efct. |
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* @ref: reference counter for hw io object |
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* @state: state of IO: free, busy, wait_free |
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* @list_entry used for busy, wait_free, free lists |
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* @wqe Work queue object, with link for pending |
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* @hw pointer back to hardware context |
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* @xfer_rdy transfer ready data |
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* @type IO type |
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* @xbusy Exchange is active in FW |
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* @abort_in_progress if TRUE, abort is in progress |
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* @status_saved if TRUE, latched status should be returned |
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* @wq_class WQ class if steering mode is Class |
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* @reqtag request tag for this HW IO |
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* @wq WQ assigned to the exchange |
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* @done Function called on IO completion |
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* @arg argument passed to IO done callback |
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* @abort_done Function called on abort completion |
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* @abort_arg argument passed to abort done callback |
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* @wq_steering WQ steering mode request |
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* @saved_status Saved status |
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* @saved_len Status length |
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* @saved_ext Saved extended status |
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* @eq EQ on which this HIO came up |
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* @sge_offset SGE data offset |
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* @def_sgl_count Count of SGEs in default SGL |
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* @abort_reqtag request tag for an abort of this HW IO |
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* @indicator Exchange indicator |
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* @def_sgl default SGL |
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* @sgl pointer to current active SGL |
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* @sgl_count count of SGEs in io->sgl |
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* @first_data_sge index of first data SGE |
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* @n_sge number of active SGEs |
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*/ |
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struct efct_hw_io { |
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struct kref ref; |
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enum efct_hw_io_state state; |
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void (*release)(struct kref *arg); |
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struct list_head list_entry; |
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struct efct_hw_wqe wqe; |
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struct efct_hw *hw; |
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struct efc_dma xfer_rdy; |
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u16 type; |
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bool xbusy; |
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int abort_in_progress; |
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bool status_saved; |
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u8 wq_class; |
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u16 reqtag; |
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struct hw_wq *wq; |
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efct_hw_done_t done; |
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void *arg; |
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efct_hw_done_t abort_done; |
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void *abort_arg; |
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enum efct_hw_wq_steering wq_steering; |
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u32 saved_status; |
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u32 saved_len; |
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u32 saved_ext; |
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struct hw_eq *eq; |
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u32 sge_offset; |
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u32 def_sgl_count; |
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u32 abort_reqtag; |
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u32 indicator; |
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struct efc_dma def_sgl; |
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struct efc_dma *sgl; |
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u32 sgl_count; |
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u32 first_data_sge; |
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u32 n_sge; |
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}; |
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enum efct_hw_port { |
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EFCT_HW_PORT_INIT, |
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EFCT_HW_PORT_SHUTDOWN, |
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}; |
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/* Node group rpi reference */ |
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struct efct_hw_rpi_ref { |
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atomic_t rpi_count; |
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atomic_t rpi_attached; |
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}; |
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enum efct_hw_link_stat { |
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EFCT_HW_LINK_STAT_LINK_FAILURE_COUNT, |
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EFCT_HW_LINK_STAT_LOSS_OF_SYNC_COUNT, |
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EFCT_HW_LINK_STAT_LOSS_OF_SIGNAL_COUNT, |
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EFCT_HW_LINK_STAT_PRIMITIVE_SEQ_COUNT, |
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EFCT_HW_LINK_STAT_INVALID_XMIT_WORD_COUNT, |
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EFCT_HW_LINK_STAT_CRC_COUNT, |
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EFCT_HW_LINK_STAT_PRIMITIVE_SEQ_TIMEOUT_COUNT, |
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EFCT_HW_LINK_STAT_ELASTIC_BUFFER_OVERRUN_COUNT, |
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EFCT_HW_LINK_STAT_ARB_TIMEOUT_COUNT, |
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EFCT_HW_LINK_STAT_ADVERTISED_RCV_B2B_CREDIT, |
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EFCT_HW_LINK_STAT_CURR_RCV_B2B_CREDIT, |
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EFCT_HW_LINK_STAT_ADVERTISED_XMIT_B2B_CREDIT, |
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EFCT_HW_LINK_STAT_CURR_XMIT_B2B_CREDIT, |
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EFCT_HW_LINK_STAT_RCV_EOFA_COUNT, |
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EFCT_HW_LINK_STAT_RCV_EOFDTI_COUNT, |
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EFCT_HW_LINK_STAT_RCV_EOFNI_COUNT, |
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EFCT_HW_LINK_STAT_RCV_SOFF_COUNT, |
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EFCT_HW_LINK_STAT_RCV_DROPPED_NO_AER_COUNT, |
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EFCT_HW_LINK_STAT_RCV_DROPPED_NO_RPI_COUNT, |
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EFCT_HW_LINK_STAT_RCV_DROPPED_NO_XRI_COUNT, |
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EFCT_HW_LINK_STAT_MAX, |
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}; |
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enum efct_hw_host_stat { |
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EFCT_HW_HOST_STAT_TX_KBYTE_COUNT, |
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EFCT_HW_HOST_STAT_RX_KBYTE_COUNT, |
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EFCT_HW_HOST_STAT_TX_FRAME_COUNT, |
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EFCT_HW_HOST_STAT_RX_FRAME_COUNT, |
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EFCT_HW_HOST_STAT_TX_SEQ_COUNT, |
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EFCT_HW_HOST_STAT_RX_SEQ_COUNT, |
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EFCT_HW_HOST_STAT_TOTAL_EXCH_ORIG, |
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EFCT_HW_HOST_STAT_TOTAL_EXCH_RESP, |
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EFCT_HW_HOSY_STAT_RX_P_BSY_COUNT, |
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EFCT_HW_HOST_STAT_RX_F_BSY_COUNT, |
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EFCT_HW_HOST_STAT_DROP_FRM_DUE_TO_NO_RQ_BUF_COUNT, |
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EFCT_HW_HOST_STAT_EMPTY_RQ_TIMEOUT_COUNT, |
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EFCT_HW_HOST_STAT_DROP_FRM_DUE_TO_NO_XRI_COUNT, |
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EFCT_HW_HOST_STAT_EMPTY_XRI_POOL_COUNT, |
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EFCT_HW_HOST_STAT_MAX, |
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}; |
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enum efct_hw_state { |
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EFCT_HW_STATE_UNINITIALIZED, |
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EFCT_HW_STATE_QUEUES_ALLOCATED, |
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EFCT_HW_STATE_ACTIVE, |
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EFCT_HW_STATE_RESET_IN_PROGRESS, |
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EFCT_HW_STATE_TEARDOWN_IN_PROGRESS, |
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}; |
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struct efct_hw_link_stat_counts { |
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u8 overflow; |
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u32 counter; |
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}; |
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struct efct_hw_host_stat_counts { |
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u32 counter; |
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}; |
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/* Structure used for the hash lookup of queue IDs */ |
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struct efct_queue_hash { |
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bool in_use; |
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u16 id; |
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u16 index; |
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}; |
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/* WQ callback object */ |
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struct hw_wq_callback { |
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u16 instance_index; /* use for request tag */ |
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void (*callback)(void *arg, u8 *cqe, int status); |
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void *arg; |
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struct list_head list_entry; |
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}; |
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struct reqtag_pool { |
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spinlock_t lock; /* pool lock */ |
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struct hw_wq_callback *tags[U16_MAX]; |
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struct list_head freelist; |
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}; |
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struct efct_hw_config { |
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u32 n_eq; |
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u32 n_cq; |
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u32 n_mq; |
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u32 n_rq; |
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u32 n_wq; |
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u32 n_io; |
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u32 n_sgl; |
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u32 speed; |
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u32 topology; |
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/* size of the buffers for first burst */ |
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u32 rq_default_buffer_size; |
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u8 esoc; |
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/* MRQ RQ selection policy */ |
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u8 rq_selection_policy; |
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/* RQ quanta if rq_selection_policy == 2 */ |
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u8 rr_quanta; |
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u32 filter_def[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; |
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}; |
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struct efct_hw { |
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struct efct *os; |
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struct sli4 sli; |
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u16 ulp_start; |
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u16 ulp_max; |
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u32 dump_size; |
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enum efct_hw_state state; |
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bool hw_setup_called; |
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u8 sliport_healthcheck; |
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u16 fcf_indicator; |
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/* HW configuration */ |
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struct efct_hw_config config; |
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/* calculated queue sizes for each type */ |
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u32 num_qentries[SLI4_QTYPE_MAX]; |
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/* Storage for SLI queue objects */ |
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struct sli4_queue wq[EFCT_HW_MAX_NUM_WQ]; |
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struct sli4_queue rq[EFCT_HW_MAX_NUM_RQ]; |
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u16 hw_rq_lookup[EFCT_HW_MAX_NUM_RQ]; |
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struct sli4_queue mq[EFCT_HW_MAX_NUM_MQ]; |
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struct sli4_queue cq[EFCT_HW_MAX_NUM_CQ]; |
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struct sli4_queue eq[EFCT_HW_MAX_NUM_EQ]; |
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/* HW queue */ |
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u32 eq_count; |
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u32 cq_count; |
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u32 mq_count; |
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u32 wq_count; |
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u32 rq_count; |
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u32 cmd_head_count; |
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struct list_head eq_list; |
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struct efct_queue_hash cq_hash[EFCT_HW_Q_HASH_SIZE]; |
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struct efct_queue_hash rq_hash[EFCT_HW_Q_HASH_SIZE]; |
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struct efct_queue_hash wq_hash[EFCT_HW_Q_HASH_SIZE]; |
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|
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/* Storage for HW queue objects */ |
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struct hw_wq *hw_wq[EFCT_HW_MAX_NUM_WQ]; |
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struct hw_rq *hw_rq[EFCT_HW_MAX_NUM_RQ]; |
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struct hw_mq *hw_mq[EFCT_HW_MAX_NUM_MQ]; |
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struct hw_cq *hw_cq[EFCT_HW_MAX_NUM_CQ]; |
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struct hw_eq *hw_eq[EFCT_HW_MAX_NUM_EQ]; |
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/* count of hw_rq[] entries */ |
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u32 hw_rq_count; |
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/* count of multirq RQs */ |
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u32 hw_mrq_count; |
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struct hw_wq **wq_cpu_array; |
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|
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/* Sequence objects used in incoming frame processing */ |
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struct efc_hw_sequence *seq_pool; |
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|
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/* Maintain an ordered, linked list of outstanding HW commands. */ |
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struct mutex bmbx_lock; |
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spinlock_t cmd_lock; |
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struct list_head cmd_head; |
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struct list_head cmd_pending; |
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mempool_t *cmd_ctx_pool; |
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mempool_t *mbox_rqst_pool; |
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struct sli4_link_event link; |
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|
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/* pointer array of IO objects */ |
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struct efct_hw_io **io; |
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/* array of WQE buffs mapped to IO objects */ |
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u8 *wqe_buffs; |
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|
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/* IO lock to synchronize list access */ |
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spinlock_t io_lock; |
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/* List of IO objects in use */ |
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struct list_head io_inuse; |
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/* List of IO objects waiting to be freed */ |
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struct list_head io_wait_free; |
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/* List of IO objects available for allocation */ |
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struct list_head io_free; |
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|
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struct efc_dma loop_map; |
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struct efc_dma xfer_rdy; |
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struct efc_dma rnode_mem; |
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atomic_t io_alloc_failed_count; |
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|
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/* stat: wq sumbit count */ |
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u32 tcmd_wq_submit[EFCT_HW_MAX_NUM_WQ]; |
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/* stat: wq complete count */ |
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u32 tcmd_wq_complete[EFCT_HW_MAX_NUM_WQ]; |
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|
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atomic_t send_frame_seq_id; |
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struct reqtag_pool *wq_reqtag_pool; |
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}; |
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enum efct_hw_io_count_type { |
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EFCT_HW_IO_INUSE_COUNT, |
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EFCT_HW_IO_FREE_COUNT, |
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EFCT_HW_IO_WAIT_FREE_COUNT, |
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EFCT_HW_IO_N_TOTAL_IO_COUNT, |
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}; |
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|
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/* HW queue data structures */ |
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struct hw_eq { |
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struct list_head list_entry; |
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enum sli4_qtype type; |
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u32 instance; |
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u32 entry_count; |
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u32 entry_size; |
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struct efct_hw *hw; |
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struct sli4_queue *queue; |
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struct list_head cq_list; |
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u32 use_count; |
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}; |
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struct hw_cq { |
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struct list_head list_entry; |
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enum sli4_qtype type; |
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u32 instance; |
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u32 entry_count; |
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u32 entry_size; |
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struct hw_eq *eq; |
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struct sli4_queue *queue; |
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struct list_head q_list; |
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u32 use_count; |
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}; |
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|
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struct hw_q { |
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struct list_head list_entry; |
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enum sli4_qtype type; |
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}; |
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struct hw_mq { |
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struct list_head list_entry; |
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enum sli4_qtype type; |
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u32 instance; |
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|
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u32 entry_count; |
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u32 entry_size; |
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struct hw_cq *cq; |
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struct sli4_queue *queue; |
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|
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u32 use_count; |
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}; |
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struct hw_wq { |
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struct list_head list_entry; |
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enum sli4_qtype type; |
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u32 instance; |
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struct efct_hw *hw; |
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|
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u32 entry_count; |
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u32 entry_size; |
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struct hw_cq *cq; |
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struct sli4_queue *queue; |
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u32 class; |
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|
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/* WQ consumed */ |
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u32 wqec_set_count; |
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u32 wqec_count; |
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u32 free_count; |
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u32 total_submit_count; |
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struct list_head pending_list; |
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|
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/* HW IO allocated for use with Send Frame */ |
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struct efct_hw_io *send_frame_io; |
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|
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/* Stats */ |
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u32 use_count; |
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u32 wq_pending_count; |
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}; |
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|
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struct hw_rq { |
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struct list_head list_entry; |
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enum sli4_qtype type; |
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u32 instance; |
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|
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u32 entry_count; |
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u32 use_count; |
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u32 hdr_entry_size; |
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u32 first_burst_entry_size; |
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u32 data_entry_size; |
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bool is_mrq; |
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u32 base_mrq_id; |
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|
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struct hw_cq *cq; |
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|
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u8 filter_mask; |
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struct sli4_queue *hdr; |
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struct sli4_queue *first_burst; |
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struct sli4_queue *data; |
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|
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struct efc_hw_rq_buffer *hdr_buf; |
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struct efc_hw_rq_buffer *fb_buf; |
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struct efc_hw_rq_buffer *payload_buf; |
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/* RQ tracker for this RQ */ |
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struct efc_hw_sequence **rq_tracker; |
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}; |
|
|
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struct efct_hw_send_frame_context { |
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struct efct_hw *hw; |
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struct hw_wq_callback *wqcb; |
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struct efct_hw_wqe wqe; |
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void (*callback)(int status, void *arg); |
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void *arg; |
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|
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/* General purpose elements */ |
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struct efc_hw_sequence *seq; |
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struct efc_dma payload; |
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}; |
|
|
|
struct efct_hw_grp_hdr { |
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u32 size; |
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__be32 magic_number; |
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u32 word2; |
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u8 rev_name[128]; |
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u8 date[12]; |
|
u8 revision[32]; |
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}; |
|
|
|
static inline int |
|
efct_hw_get_link_speed(struct efct_hw *hw) { |
|
return hw->link.speed; |
|
} |
|
|
|
int |
|
efct_hw_setup(struct efct_hw *hw, void *os, struct pci_dev *pdev); |
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int efct_hw_init(struct efct_hw *hw); |
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int |
|
efct_hw_parse_filter(struct efct_hw *hw, void *value); |
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int |
|
efct_hw_init_queues(struct efct_hw *hw); |
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int |
|
efct_hw_map_wq_cpu(struct efct_hw *hw); |
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uint64_t |
|
efct_get_wwnn(struct efct_hw *hw); |
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uint64_t |
|
efct_get_wwpn(struct efct_hw *hw); |
|
|
|
int efct_hw_rx_allocate(struct efct_hw *hw); |
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int efct_hw_rx_post(struct efct_hw *hw); |
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void efct_hw_rx_free(struct efct_hw *hw); |
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int |
|
efct_hw_command(struct efct_hw *hw, u8 *cmd, u32 opts, void *cb, |
|
void *arg); |
|
int |
|
efct_issue_mbox_rqst(void *base, void *cmd, void *cb, void *arg); |
|
|
|
struct efct_hw_io *efct_hw_io_alloc(struct efct_hw *hw); |
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int efct_hw_io_free(struct efct_hw *hw, struct efct_hw_io *io); |
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u8 efct_hw_io_inuse(struct efct_hw *hw, struct efct_hw_io *io); |
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int |
|
efct_hw_io_send(struct efct_hw *hw, enum efct_hw_io_type type, |
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struct efct_hw_io *io, union efct_hw_io_param_u *iparam, |
|
void *cb, void *arg); |
|
int |
|
efct_hw_io_register_sgl(struct efct_hw *hw, struct efct_hw_io *io, |
|
struct efc_dma *sgl, |
|
u32 sgl_count); |
|
int |
|
efct_hw_io_init_sges(struct efct_hw *hw, |
|
struct efct_hw_io *io, enum efct_hw_io_type type); |
|
|
|
int |
|
efct_hw_io_add_sge(struct efct_hw *hw, struct efct_hw_io *io, |
|
uintptr_t addr, u32 length); |
|
int |
|
efct_hw_io_abort(struct efct_hw *hw, struct efct_hw_io *io_to_abort, |
|
bool send_abts, void *cb, void *arg); |
|
u32 |
|
efct_hw_io_get_count(struct efct_hw *hw, |
|
enum efct_hw_io_count_type io_count_type); |
|
struct efct_hw_io |
|
*efct_hw_io_lookup(struct efct_hw *hw, u32 indicator); |
|
void efct_hw_io_abort_all(struct efct_hw *hw); |
|
void efct_hw_io_free_internal(struct kref *arg); |
|
|
|
/* HW WQ request tag API */ |
|
struct reqtag_pool *efct_hw_reqtag_pool_alloc(struct efct_hw *hw); |
|
void efct_hw_reqtag_pool_free(struct efct_hw *hw); |
|
struct hw_wq_callback |
|
*efct_hw_reqtag_alloc(struct efct_hw *hw, |
|
void (*callback)(void *arg, u8 *cqe, |
|
int status), void *arg); |
|
void |
|
efct_hw_reqtag_free(struct efct_hw *hw, struct hw_wq_callback *wqcb); |
|
struct hw_wq_callback |
|
*efct_hw_reqtag_get_instance(struct efct_hw *hw, u32 instance_index); |
|
|
|
/* RQ completion handlers for RQ pair mode */ |
|
int |
|
efct_hw_rqpair_process_rq(struct efct_hw *hw, |
|
struct hw_cq *cq, u8 *cqe); |
|
int |
|
efct_hw_rqpair_sequence_free(struct efct_hw *hw, struct efc_hw_sequence *seq); |
|
static inline void |
|
efct_hw_sequence_copy(struct efc_hw_sequence *dst, |
|
struct efc_hw_sequence *src) |
|
{ |
|
/* Copy src to dst, then zero out the linked list link */ |
|
*dst = *src; |
|
} |
|
|
|
int |
|
efct_efc_hw_sequence_free(struct efc *efc, struct efc_hw_sequence *seq); |
|
|
|
static inline int |
|
efct_hw_sequence_free(struct efct_hw *hw, struct efc_hw_sequence *seq) |
|
{ |
|
/* Only RQ pair mode is supported */ |
|
return efct_hw_rqpair_sequence_free(hw, seq); |
|
} |
|
|
|
int |
|
efct_hw_eq_process(struct efct_hw *hw, struct hw_eq *eq, |
|
u32 max_isr_time_msec); |
|
void efct_hw_cq_process(struct efct_hw *hw, struct hw_cq *cq); |
|
void |
|
efct_hw_wq_process(struct efct_hw *hw, struct hw_cq *cq, |
|
u8 *cqe, int status, u16 rid); |
|
void |
|
efct_hw_xabt_process(struct efct_hw *hw, struct hw_cq *cq, |
|
u8 *cqe, u16 rid); |
|
int |
|
efct_hw_process(struct efct_hw *hw, u32 vector, u32 max_isr_time_msec); |
|
int |
|
efct_hw_queue_hash_find(struct efct_queue_hash *hash, u16 id); |
|
int efct_hw_wq_write(struct hw_wq *wq, struct efct_hw_wqe *wqe); |
|
int |
|
efct_hw_send_frame(struct efct_hw *hw, struct fc_frame_header *hdr, |
|
u8 sof, u8 eof, struct efc_dma *payload, |
|
struct efct_hw_send_frame_context *ctx, |
|
void (*callback)(void *arg, u8 *cqe, int status), |
|
void *arg); |
|
int |
|
efct_els_hw_srrs_send(struct efc *efc, struct efc_disc_io *io); |
|
int |
|
efct_efc_bls_send(struct efc *efc, u32 type, struct sli_bls_params *bls); |
|
int |
|
efct_hw_bls_send(struct efct *efct, u32 type, struct sli_bls_params *bls_params, |
|
void *cb, void *arg); |
|
|
|
/* Function for retrieving link statistics */ |
|
int |
|
efct_hw_get_link_stats(struct efct_hw *hw, |
|
u8 req_ext_counters, |
|
u8 clear_overflow_flags, |
|
u8 clear_all_counters, |
|
void (*efct_hw_link_stat_cb_t)(int status, |
|
u32 num_counters, |
|
struct efct_hw_link_stat_counts *counters, void *arg), |
|
void *arg); |
|
/* Function for retrieving host statistics */ |
|
int |
|
efct_hw_get_host_stats(struct efct_hw *hw, |
|
u8 cc, |
|
void (*efct_hw_host_stat_cb_t)(int status, |
|
u32 num_counters, |
|
struct efct_hw_host_stat_counts *counters, void *arg), |
|
void *arg); |
|
int |
|
efct_hw_firmware_write(struct efct_hw *hw, struct efc_dma *dma, |
|
u32 size, u32 offset, int last, |
|
void (*cb)(int status, u32 bytes_written, |
|
u32 change_status, void *arg), |
|
void *arg); |
|
typedef void (*efct_hw_async_cb_t)(struct efct_hw *hw, int status, |
|
u8 *mqe, void *arg); |
|
int |
|
efct_hw_async_call(struct efct_hw *hw, efct_hw_async_cb_t callback, void *arg); |
|
|
|
struct hw_eq *efct_hw_new_eq(struct efct_hw *hw, u32 entry_count); |
|
struct hw_cq *efct_hw_new_cq(struct hw_eq *eq, u32 entry_count); |
|
u32 |
|
efct_hw_new_cq_set(struct hw_eq *eqs[], struct hw_cq *cqs[], |
|
u32 num_cqs, u32 entry_count); |
|
struct hw_mq *efct_hw_new_mq(struct hw_cq *cq, u32 entry_count); |
|
struct hw_wq |
|
*efct_hw_new_wq(struct hw_cq *cq, u32 entry_count); |
|
u32 |
|
efct_hw_new_rq_set(struct hw_cq *cqs[], struct hw_rq *rqs[], |
|
u32 num_rq_pairs, u32 entry_count); |
|
void efct_hw_del_eq(struct hw_eq *eq); |
|
void efct_hw_del_cq(struct hw_cq *cq); |
|
void efct_hw_del_mq(struct hw_mq *mq); |
|
void efct_hw_del_wq(struct hw_wq *wq); |
|
void efct_hw_del_rq(struct hw_rq *rq); |
|
void efct_hw_queue_teardown(struct efct_hw *hw); |
|
void efct_hw_teardown(struct efct_hw *hw); |
|
int |
|
efct_hw_reset(struct efct_hw *hw, enum efct_hw_reset reset); |
|
|
|
int |
|
efct_hw_port_control(struct efct_hw *hw, enum efct_hw_port ctrl, |
|
uintptr_t value, |
|
void (*cb)(int status, uintptr_t value, void *arg), |
|
void *arg); |
|
|
|
#endif /* __EFCT_H__ */
|
|
|