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503 lines
11 KiB
503 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd |
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// http://www.samsung.com |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/module.h> |
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#include <linux/regmap.h> |
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#include <linux/mfd/samsung/core.h> |
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#include <linux/mfd/samsung/irq.h> |
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#include <linux/mfd/samsung/s2mps11.h> |
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#include <linux/mfd/samsung/s2mps14.h> |
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#include <linux/mfd/samsung/s2mpu02.h> |
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#include <linux/mfd/samsung/s5m8763.h> |
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#include <linux/mfd/samsung/s5m8767.h> |
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static const struct regmap_irq s2mps11_irqs[] = { |
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[S2MPS11_IRQ_PWRONF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRONF_MASK, |
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}, |
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[S2MPS11_IRQ_PWRONR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRONR_MASK, |
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}, |
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[S2MPS11_IRQ_JIGONBF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_JIGONBF_MASK, |
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}, |
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[S2MPS11_IRQ_JIGONBR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_JIGONBR_MASK, |
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}, |
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[S2MPS11_IRQ_ACOKBF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_ACOKBF_MASK, |
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}, |
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[S2MPS11_IRQ_ACOKBR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_ACOKBR_MASK, |
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}, |
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[S2MPS11_IRQ_PWRON1S] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRON1S_MASK, |
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}, |
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[S2MPS11_IRQ_MRB] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_MRB_MASK, |
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}, |
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[S2MPS11_IRQ_RTC60S] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTC60S_MASK, |
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}, |
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[S2MPS11_IRQ_RTCA1] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTCA1_MASK, |
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}, |
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[S2MPS11_IRQ_RTCA0] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTCA0_MASK, |
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}, |
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[S2MPS11_IRQ_SMPL] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_SMPL_MASK, |
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}, |
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[S2MPS11_IRQ_RTC1S] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTC1S_MASK, |
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}, |
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[S2MPS11_IRQ_WTSR] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_WTSR_MASK, |
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}, |
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[S2MPS11_IRQ_INT120C] = { |
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.reg_offset = 2, |
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.mask = S2MPS11_IRQ_INT120C_MASK, |
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}, |
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[S2MPS11_IRQ_INT140C] = { |
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.reg_offset = 2, |
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.mask = S2MPS11_IRQ_INT140C_MASK, |
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}, |
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}; |
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static const struct regmap_irq s2mps14_irqs[] = { |
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[S2MPS14_IRQ_PWRONF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRONF_MASK, |
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}, |
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[S2MPS14_IRQ_PWRONR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRONR_MASK, |
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}, |
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[S2MPS14_IRQ_JIGONBF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_JIGONBF_MASK, |
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}, |
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[S2MPS14_IRQ_JIGONBR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_JIGONBR_MASK, |
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}, |
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[S2MPS14_IRQ_ACOKBF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_ACOKBF_MASK, |
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}, |
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[S2MPS14_IRQ_ACOKBR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_ACOKBR_MASK, |
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}, |
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[S2MPS14_IRQ_PWRON1S] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRON1S_MASK, |
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}, |
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[S2MPS14_IRQ_MRB] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_MRB_MASK, |
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}, |
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[S2MPS14_IRQ_RTC60S] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTC60S_MASK, |
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}, |
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[S2MPS14_IRQ_RTCA1] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTCA1_MASK, |
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}, |
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[S2MPS14_IRQ_RTCA0] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTCA0_MASK, |
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}, |
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[S2MPS14_IRQ_SMPL] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_SMPL_MASK, |
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}, |
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[S2MPS14_IRQ_RTC1S] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTC1S_MASK, |
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}, |
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[S2MPS14_IRQ_WTSR] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_WTSR_MASK, |
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}, |
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[S2MPS14_IRQ_INT120C] = { |
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.reg_offset = 2, |
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.mask = S2MPS11_IRQ_INT120C_MASK, |
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}, |
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[S2MPS14_IRQ_INT140C] = { |
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.reg_offset = 2, |
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.mask = S2MPS11_IRQ_INT140C_MASK, |
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}, |
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[S2MPS14_IRQ_TSD] = { |
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.reg_offset = 2, |
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.mask = S2MPS14_IRQ_TSD_MASK, |
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}, |
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}; |
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static const struct regmap_irq s2mpu02_irqs[] = { |
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[S2MPU02_IRQ_PWRONF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRONF_MASK, |
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}, |
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[S2MPU02_IRQ_PWRONR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRONR_MASK, |
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}, |
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[S2MPU02_IRQ_JIGONBF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_JIGONBF_MASK, |
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}, |
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[S2MPU02_IRQ_JIGONBR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_JIGONBR_MASK, |
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}, |
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[S2MPU02_IRQ_ACOKBF] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_ACOKBF_MASK, |
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}, |
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[S2MPU02_IRQ_ACOKBR] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_ACOKBR_MASK, |
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}, |
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[S2MPU02_IRQ_PWRON1S] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_PWRON1S_MASK, |
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}, |
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[S2MPU02_IRQ_MRB] = { |
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.reg_offset = 0, |
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.mask = S2MPS11_IRQ_MRB_MASK, |
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}, |
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[S2MPU02_IRQ_RTC60S] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTC60S_MASK, |
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}, |
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[S2MPU02_IRQ_RTCA1] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTCA1_MASK, |
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}, |
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[S2MPU02_IRQ_RTCA0] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTCA0_MASK, |
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}, |
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[S2MPU02_IRQ_SMPL] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_SMPL_MASK, |
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}, |
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[S2MPU02_IRQ_RTC1S] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_RTC1S_MASK, |
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}, |
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[S2MPU02_IRQ_WTSR] = { |
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.reg_offset = 1, |
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.mask = S2MPS11_IRQ_WTSR_MASK, |
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}, |
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[S2MPU02_IRQ_INT120C] = { |
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.reg_offset = 2, |
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.mask = S2MPS11_IRQ_INT120C_MASK, |
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}, |
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[S2MPU02_IRQ_INT140C] = { |
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.reg_offset = 2, |
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.mask = S2MPS11_IRQ_INT140C_MASK, |
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}, |
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[S2MPU02_IRQ_TSD] = { |
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.reg_offset = 2, |
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.mask = S2MPS14_IRQ_TSD_MASK, |
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}, |
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}; |
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static const struct regmap_irq s5m8767_irqs[] = { |
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[S5M8767_IRQ_PWRR] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_PWRR_MASK, |
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}, |
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[S5M8767_IRQ_PWRF] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_PWRF_MASK, |
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}, |
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[S5M8767_IRQ_PWR1S] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_PWR1S_MASK, |
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}, |
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[S5M8767_IRQ_JIGR] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_JIGR_MASK, |
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}, |
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[S5M8767_IRQ_JIGF] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_JIGF_MASK, |
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}, |
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[S5M8767_IRQ_LOWBAT2] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_LOWBAT2_MASK, |
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}, |
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[S5M8767_IRQ_LOWBAT1] = { |
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.reg_offset = 0, |
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.mask = S5M8767_IRQ_LOWBAT1_MASK, |
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}, |
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[S5M8767_IRQ_MRB] = { |
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.reg_offset = 1, |
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.mask = S5M8767_IRQ_MRB_MASK, |
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}, |
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[S5M8767_IRQ_DVSOK2] = { |
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.reg_offset = 1, |
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.mask = S5M8767_IRQ_DVSOK2_MASK, |
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}, |
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[S5M8767_IRQ_DVSOK3] = { |
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.reg_offset = 1, |
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.mask = S5M8767_IRQ_DVSOK3_MASK, |
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}, |
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[S5M8767_IRQ_DVSOK4] = { |
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.reg_offset = 1, |
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.mask = S5M8767_IRQ_DVSOK4_MASK, |
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}, |
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[S5M8767_IRQ_RTC60S] = { |
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.reg_offset = 2, |
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.mask = S5M8767_IRQ_RTC60S_MASK, |
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}, |
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[S5M8767_IRQ_RTCA1] = { |
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.reg_offset = 2, |
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.mask = S5M8767_IRQ_RTCA1_MASK, |
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}, |
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[S5M8767_IRQ_RTCA2] = { |
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.reg_offset = 2, |
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.mask = S5M8767_IRQ_RTCA2_MASK, |
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}, |
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[S5M8767_IRQ_SMPL] = { |
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.reg_offset = 2, |
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.mask = S5M8767_IRQ_SMPL_MASK, |
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}, |
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[S5M8767_IRQ_RTC1S] = { |
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.reg_offset = 2, |
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.mask = S5M8767_IRQ_RTC1S_MASK, |
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}, |
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[S5M8767_IRQ_WTSR] = { |
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.reg_offset = 2, |
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.mask = S5M8767_IRQ_WTSR_MASK, |
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}, |
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}; |
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static const struct regmap_irq s5m8763_irqs[] = { |
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[S5M8763_IRQ_DCINF] = { |
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.reg_offset = 0, |
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.mask = S5M8763_IRQ_DCINF_MASK, |
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}, |
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[S5M8763_IRQ_DCINR] = { |
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.reg_offset = 0, |
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.mask = S5M8763_IRQ_DCINR_MASK, |
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}, |
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[S5M8763_IRQ_JIGF] = { |
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.reg_offset = 0, |
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.mask = S5M8763_IRQ_JIGF_MASK, |
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}, |
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[S5M8763_IRQ_JIGR] = { |
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.reg_offset = 0, |
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.mask = S5M8763_IRQ_JIGR_MASK, |
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}, |
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[S5M8763_IRQ_PWRONF] = { |
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.reg_offset = 0, |
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.mask = S5M8763_IRQ_PWRONF_MASK, |
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}, |
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[S5M8763_IRQ_PWRONR] = { |
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.reg_offset = 0, |
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.mask = S5M8763_IRQ_PWRONR_MASK, |
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}, |
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[S5M8763_IRQ_WTSREVNT] = { |
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.reg_offset = 1, |
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.mask = S5M8763_IRQ_WTSREVNT_MASK, |
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}, |
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[S5M8763_IRQ_SMPLEVNT] = { |
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.reg_offset = 1, |
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.mask = S5M8763_IRQ_SMPLEVNT_MASK, |
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}, |
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[S5M8763_IRQ_ALARM1] = { |
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.reg_offset = 1, |
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.mask = S5M8763_IRQ_ALARM1_MASK, |
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}, |
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[S5M8763_IRQ_ALARM0] = { |
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.reg_offset = 1, |
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.mask = S5M8763_IRQ_ALARM0_MASK, |
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}, |
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[S5M8763_IRQ_ONKEY1S] = { |
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.reg_offset = 2, |
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.mask = S5M8763_IRQ_ONKEY1S_MASK, |
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}, |
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[S5M8763_IRQ_TOPOFFR] = { |
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.reg_offset = 2, |
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.mask = S5M8763_IRQ_TOPOFFR_MASK, |
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}, |
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[S5M8763_IRQ_DCINOVPR] = { |
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.reg_offset = 2, |
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.mask = S5M8763_IRQ_DCINOVPR_MASK, |
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}, |
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[S5M8763_IRQ_CHGRSTF] = { |
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.reg_offset = 2, |
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.mask = S5M8763_IRQ_CHGRSTF_MASK, |
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}, |
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[S5M8763_IRQ_DONER] = { |
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.reg_offset = 2, |
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.mask = S5M8763_IRQ_DONER_MASK, |
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}, |
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[S5M8763_IRQ_CHGFAULT] = { |
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.reg_offset = 2, |
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.mask = S5M8763_IRQ_CHGFAULT_MASK, |
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}, |
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[S5M8763_IRQ_LOBAT1] = { |
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.reg_offset = 3, |
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.mask = S5M8763_IRQ_LOBAT1_MASK, |
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}, |
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[S5M8763_IRQ_LOBAT2] = { |
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.reg_offset = 3, |
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.mask = S5M8763_IRQ_LOBAT2_MASK, |
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}, |
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}; |
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static const struct regmap_irq_chip s2mps11_irq_chip = { |
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.name = "s2mps11", |
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.irqs = s2mps11_irqs, |
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.num_irqs = ARRAY_SIZE(s2mps11_irqs), |
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.num_regs = 3, |
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.status_base = S2MPS11_REG_INT1, |
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.mask_base = S2MPS11_REG_INT1M, |
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.ack_base = S2MPS11_REG_INT1, |
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}; |
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#define S2MPS1X_IRQ_CHIP_COMMON_DATA \ |
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.irqs = s2mps14_irqs, \ |
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.num_irqs = ARRAY_SIZE(s2mps14_irqs), \ |
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.num_regs = 3, \ |
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.status_base = S2MPS14_REG_INT1, \ |
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.mask_base = S2MPS14_REG_INT1M, \ |
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.ack_base = S2MPS14_REG_INT1 \ |
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static const struct regmap_irq_chip s2mps13_irq_chip = { |
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.name = "s2mps13", |
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S2MPS1X_IRQ_CHIP_COMMON_DATA, |
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}; |
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static const struct regmap_irq_chip s2mps14_irq_chip = { |
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.name = "s2mps14", |
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S2MPS1X_IRQ_CHIP_COMMON_DATA, |
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}; |
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static const struct regmap_irq_chip s2mps15_irq_chip = { |
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.name = "s2mps15", |
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S2MPS1X_IRQ_CHIP_COMMON_DATA, |
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}; |
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static const struct regmap_irq_chip s2mpu02_irq_chip = { |
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.name = "s2mpu02", |
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.irqs = s2mpu02_irqs, |
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.num_irqs = ARRAY_SIZE(s2mpu02_irqs), |
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.num_regs = 3, |
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.status_base = S2MPU02_REG_INT1, |
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.mask_base = S2MPU02_REG_INT1M, |
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.ack_base = S2MPU02_REG_INT1, |
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}; |
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static const struct regmap_irq_chip s5m8767_irq_chip = { |
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.name = "s5m8767", |
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.irqs = s5m8767_irqs, |
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.num_irqs = ARRAY_SIZE(s5m8767_irqs), |
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.num_regs = 3, |
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.status_base = S5M8767_REG_INT1, |
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.mask_base = S5M8767_REG_INT1M, |
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.ack_base = S5M8767_REG_INT1, |
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}; |
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static const struct regmap_irq_chip s5m8763_irq_chip = { |
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.name = "s5m8763", |
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.irqs = s5m8763_irqs, |
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.num_irqs = ARRAY_SIZE(s5m8763_irqs), |
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.num_regs = 4, |
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.status_base = S5M8763_REG_IRQ1, |
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.mask_base = S5M8763_REG_IRQM1, |
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.ack_base = S5M8763_REG_IRQ1, |
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}; |
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int sec_irq_init(struct sec_pmic_dev *sec_pmic) |
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{ |
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int ret = 0; |
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int type = sec_pmic->device_type; |
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const struct regmap_irq_chip *sec_irq_chip; |
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if (!sec_pmic->irq) { |
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dev_warn(sec_pmic->dev, |
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"No interrupt specified, no interrupts\n"); |
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return 0; |
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} |
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switch (type) { |
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case S5M8763X: |
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sec_irq_chip = &s5m8763_irq_chip; |
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break; |
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case S5M8767X: |
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sec_irq_chip = &s5m8767_irq_chip; |
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break; |
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case S2MPA01: |
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sec_irq_chip = &s2mps14_irq_chip; |
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break; |
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case S2MPS11X: |
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sec_irq_chip = &s2mps11_irq_chip; |
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break; |
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case S2MPS13X: |
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sec_irq_chip = &s2mps13_irq_chip; |
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break; |
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case S2MPS14X: |
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sec_irq_chip = &s2mps14_irq_chip; |
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break; |
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case S2MPS15X: |
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sec_irq_chip = &s2mps15_irq_chip; |
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break; |
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case S2MPU02: |
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sec_irq_chip = &s2mpu02_irq_chip; |
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break; |
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default: |
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dev_err(sec_pmic->dev, "Unknown device type %lu\n", |
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sec_pmic->device_type); |
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return -EINVAL; |
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} |
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ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, |
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sec_pmic->irq, IRQF_ONESHOT, |
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0, sec_irq_chip, &sec_pmic->irq_data); |
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if (ret != 0) { |
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dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret); |
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return ret; |
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} |
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|
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/* |
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* The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11 |
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* so the interrupt number must be consistent. |
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*/ |
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BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(sec_irq_init); |
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|
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MODULE_AUTHOR("Sangbeom Kim <[email protected]>"); |
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MODULE_AUTHOR("Chanwoo Choi <[email protected]>"); |
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MODULE_AUTHOR("Krzysztof Kozlowski <[email protected]>"); |
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MODULE_DESCRIPTION("Interrupt support for the S5M MFD"); |
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MODULE_LICENSE("GPL");
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