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188 lines
4.9 KiB
188 lines
4.9 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Allwinner sun50i(H6) USB 3.0 phy driver |
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* |
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* Copyright (C) 2017 Icenowy Zheng <[email protected]> |
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* |
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* Based on phy-sun9i-usb.c, which is: |
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* |
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* Copyright (C) 2014-2015 Chen-Yu Tsai <[email protected]> |
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* |
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* Based on code from Allwinner BSP, which is: |
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* |
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* Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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/* Interface Status and Control Registers */ |
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#define SUNXI_ISCR 0x00 |
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#define SUNXI_PIPE_CLOCK_CONTROL 0x14 |
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#define SUNXI_PHY_TUNE_LOW 0x18 |
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#define SUNXI_PHY_TUNE_HIGH 0x1c |
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#define SUNXI_PHY_EXTERNAL_CONTROL 0x20 |
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/* USB2.0 Interface Status and Control Register */ |
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#define SUNXI_ISCR_FORCE_VBUS (3 << 12) |
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/* PIPE Clock Control Register */ |
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#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) |
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/* PHY External Control Register */ |
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#define SUNXI_PEC_EXTERN_VBUS (3 << 1) |
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#define SUNXI_PEC_SSC_EN (1 << 24) |
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#define SUNXI_PEC_REF_SSP_EN (1 << 26) |
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/* PHY Tune High Register */ |
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#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) |
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#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) |
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#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) |
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#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) |
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#define SUNXI_TX_SWING_FULL(n) ((n) << 6) |
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#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) |
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#define SUNXI_LOS_BIAS(n) ((n) << 3) |
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#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) |
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#define SUNXI_TXVBOOSTLVL(n) ((n) << 0) |
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#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0) |
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struct sun50i_usb3_phy { |
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struct phy *phy; |
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void __iomem *regs; |
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struct reset_control *reset; |
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struct clk *clk; |
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}; |
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static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy) |
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{ |
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u32 val; |
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val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); |
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val |= SUNXI_PEC_EXTERN_VBUS; |
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val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; |
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writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); |
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val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); |
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val |= SUNXI_PCC_PIPE_CLK_OPEN; |
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writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); |
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val = readl(phy->regs + SUNXI_ISCR); |
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val |= SUNXI_ISCR_FORCE_VBUS; |
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writel(val, phy->regs + SUNXI_ISCR); |
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/* |
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* All the magic numbers written to the PHY_TUNE_{LOW_HIGH} |
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* registers are directly taken from the BSP USB3 driver from |
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* Allwiner. |
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*/ |
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writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); |
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val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); |
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val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | |
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SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | |
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SUNXI_TX_DEEMPH_3P5DB_MASK); |
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val |= SUNXI_TXVBOOSTLVL(0x7); |
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val |= SUNXI_LOS_BIAS(0x7); |
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val |= SUNXI_TX_SWING_FULL(0x55); |
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val |= SUNXI_TX_DEEMPH_6DB(0x20); |
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val |= SUNXI_TX_DEEMPH_3P5DB(0x15); |
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writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); |
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} |
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static int sun50i_usb3_phy_init(struct phy *_phy) |
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{ |
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struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); |
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int ret; |
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ret = clk_prepare_enable(phy->clk); |
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if (ret) |
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return ret; |
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ret = reset_control_deassert(phy->reset); |
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if (ret) { |
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clk_disable_unprepare(phy->clk); |
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return ret; |
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} |
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sun50i_usb3_phy_open(phy); |
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return 0; |
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} |
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static int sun50i_usb3_phy_exit(struct phy *_phy) |
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{ |
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struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); |
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reset_control_assert(phy->reset); |
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clk_disable_unprepare(phy->clk); |
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return 0; |
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} |
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static const struct phy_ops sun50i_usb3_phy_ops = { |
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.init = sun50i_usb3_phy_init, |
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.exit = sun50i_usb3_phy_exit, |
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.owner = THIS_MODULE, |
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}; |
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static int sun50i_usb3_phy_probe(struct platform_device *pdev) |
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{ |
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struct sun50i_usb3_phy *phy; |
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struct device *dev = &pdev->dev; |
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struct phy_provider *phy_provider; |
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); |
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if (!phy) |
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return -ENOMEM; |
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phy->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(phy->clk)) { |
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if (PTR_ERR(phy->clk) != -EPROBE_DEFER) |
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dev_err(dev, "failed to get phy clock\n"); |
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return PTR_ERR(phy->clk); |
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} |
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phy->reset = devm_reset_control_get(dev, NULL); |
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if (IS_ERR(phy->reset)) { |
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dev_err(dev, "failed to get reset control\n"); |
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return PTR_ERR(phy->reset); |
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} |
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phy->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(phy->regs)) |
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return PTR_ERR(phy->regs); |
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phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops); |
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if (IS_ERR(phy->phy)) { |
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dev_err(dev, "failed to create PHY\n"); |
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return PTR_ERR(phy->phy); |
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} |
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phy_set_drvdata(phy->phy, phy); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id sun50i_usb3_phy_of_match[] = { |
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{ .compatible = "allwinner,sun50i-h6-usb3-phy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match); |
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static struct platform_driver sun50i_usb3_phy_driver = { |
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.probe = sun50i_usb3_phy_probe, |
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.driver = { |
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.of_match_table = sun50i_usb3_phy_of_match, |
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.name = "sun50i-usb3-phy", |
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} |
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}; |
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module_platform_driver(sun50i_usb3_phy_driver); |
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MODULE_DESCRIPTION("Allwinner H6 USB 3.0 phy driver"); |
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MODULE_AUTHOR("Icenowy Zheng <[email protected]>"); |
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MODULE_LICENSE("GPL");
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