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968 lines
23 KiB
968 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* drivers/net/phy/realtek.c |
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* |
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* Driver for Realtek PHYs |
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* |
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* Author: Johnson Leung <[email protected]> |
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* |
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* Copyright (c) 2004 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/phy.h> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#define RTL821x_PHYSR 0x11 |
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#define RTL821x_PHYSR_DUPLEX BIT(13) |
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#define RTL821x_PHYSR_SPEED GENMASK(15, 14) |
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#define RTL821x_INER 0x12 |
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#define RTL8211B_INER_INIT 0x6400 |
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#define RTL8211E_INER_LINK_STATUS BIT(10) |
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#define RTL8211F_INER_LINK_STATUS BIT(4) |
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#define RTL821x_INSR 0x13 |
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#define RTL821x_EXT_PAGE_SELECT 0x1e |
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#define RTL821x_PAGE_SELECT 0x1f |
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#define RTL8211F_PHYCR1 0x18 |
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#define RTL8211F_INSR 0x1d |
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#define RTL8211F_TX_DELAY BIT(8) |
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#define RTL8211F_RX_DELAY BIT(3) |
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#define RTL8211F_ALDPS_PLL_OFF BIT(1) |
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#define RTL8211F_ALDPS_ENABLE BIT(2) |
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#define RTL8211F_ALDPS_XTAL_OFF BIT(12) |
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|
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#define RTL8211E_CTRL_DELAY BIT(13) |
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#define RTL8211E_TX_DELAY BIT(12) |
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#define RTL8211E_RX_DELAY BIT(11) |
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#define RTL8201F_ISR 0x1e |
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#define RTL8201F_ISR_ANERR BIT(15) |
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#define RTL8201F_ISR_DUPLEX BIT(13) |
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#define RTL8201F_ISR_LINK BIT(11) |
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#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ |
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RTL8201F_ISR_DUPLEX | \ |
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RTL8201F_ISR_LINK) |
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#define RTL8201F_IER 0x13 |
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#define RTL8366RB_POWER_SAVE 0x15 |
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#define RTL8366RB_POWER_SAVE_ON BIT(12) |
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#define RTL_SUPPORTS_5000FULL BIT(14) |
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#define RTL_SUPPORTS_2500FULL BIT(13) |
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#define RTL_SUPPORTS_10000FULL BIT(0) |
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#define RTL_ADV_2500FULL BIT(7) |
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#define RTL_LPADV_10000FULL BIT(11) |
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#define RTL_LPADV_5000FULL BIT(6) |
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#define RTL_LPADV_2500FULL BIT(5) |
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#define RTL9000A_GINMR 0x14 |
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#define RTL9000A_GINMR_LINK_STATUS BIT(4) |
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#define RTLGEN_SPEED_MASK 0x0630 |
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#define RTL_GENERIC_PHYID 0x001cc800 |
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MODULE_DESCRIPTION("Realtek PHY driver"); |
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MODULE_AUTHOR("Johnson Leung"); |
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MODULE_LICENSE("GPL"); |
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static int rtl821x_read_page(struct phy_device *phydev) |
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{ |
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return __phy_read(phydev, RTL821x_PAGE_SELECT); |
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} |
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static int rtl821x_write_page(struct phy_device *phydev, int page) |
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{ |
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return __phy_write(phydev, RTL821x_PAGE_SELECT, page); |
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} |
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static int rtl8201_ack_interrupt(struct phy_device *phydev) |
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{ |
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int err; |
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err = phy_read(phydev, RTL8201F_ISR); |
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return (err < 0) ? err : 0; |
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} |
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static int rtl821x_ack_interrupt(struct phy_device *phydev) |
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{ |
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int err; |
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err = phy_read(phydev, RTL821x_INSR); |
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return (err < 0) ? err : 0; |
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} |
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static int rtl8211f_ack_interrupt(struct phy_device *phydev) |
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{ |
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int err; |
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err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); |
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return (err < 0) ? err : 0; |
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} |
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static int rtl8201_config_intr(struct phy_device *phydev) |
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{ |
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u16 val; |
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int err; |
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
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err = rtl8201_ack_interrupt(phydev); |
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if (err) |
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return err; |
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val = BIT(13) | BIT(12) | BIT(11); |
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err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); |
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} else { |
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val = 0; |
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err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); |
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if (err) |
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return err; |
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err = rtl8201_ack_interrupt(phydev); |
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} |
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return err; |
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} |
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static int rtl8211b_config_intr(struct phy_device *phydev) |
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{ |
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int err; |
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
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err = rtl821x_ack_interrupt(phydev); |
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if (err) |
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return err; |
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err = phy_write(phydev, RTL821x_INER, |
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RTL8211B_INER_INIT); |
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} else { |
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err = phy_write(phydev, RTL821x_INER, 0); |
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if (err) |
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return err; |
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err = rtl821x_ack_interrupt(phydev); |
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} |
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return err; |
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} |
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static int rtl8211e_config_intr(struct phy_device *phydev) |
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{ |
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int err; |
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
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err = rtl821x_ack_interrupt(phydev); |
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if (err) |
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return err; |
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err = phy_write(phydev, RTL821x_INER, |
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RTL8211E_INER_LINK_STATUS); |
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} else { |
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err = phy_write(phydev, RTL821x_INER, 0); |
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if (err) |
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return err; |
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err = rtl821x_ack_interrupt(phydev); |
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} |
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return err; |
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} |
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static int rtl8211f_config_intr(struct phy_device *phydev) |
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{ |
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u16 val; |
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int err; |
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
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err = rtl8211f_ack_interrupt(phydev); |
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if (err) |
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return err; |
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val = RTL8211F_INER_LINK_STATUS; |
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err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); |
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} else { |
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val = 0; |
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err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); |
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if (err) |
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return err; |
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err = rtl8211f_ack_interrupt(phydev); |
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} |
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return err; |
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} |
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static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) |
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{ |
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int irq_status; |
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irq_status = phy_read(phydev, RTL8201F_ISR); |
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if (irq_status < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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if (!(irq_status & RTL8201F_ISR_MASK)) |
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return IRQ_NONE; |
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phy_trigger_machine(phydev); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) |
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{ |
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int irq_status, irq_enabled; |
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irq_status = phy_read(phydev, RTL821x_INSR); |
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if (irq_status < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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irq_enabled = phy_read(phydev, RTL821x_INER); |
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if (irq_enabled < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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if (!(irq_status & irq_enabled)) |
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return IRQ_NONE; |
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phy_trigger_machine(phydev); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) |
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{ |
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int irq_status; |
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irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); |
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if (irq_status < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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if (!(irq_status & RTL8211F_INER_LINK_STATUS)) |
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return IRQ_NONE; |
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phy_trigger_machine(phydev); |
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return IRQ_HANDLED; |
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} |
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static int rtl8211_config_aneg(struct phy_device *phydev) |
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{ |
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int ret; |
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ret = genphy_config_aneg(phydev); |
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if (ret < 0) |
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return ret; |
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/* Quirk was copied from vendor driver. Unfortunately it includes no |
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* description of the magic numbers. |
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*/ |
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if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { |
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phy_write(phydev, 0x17, 0x2138); |
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phy_write(phydev, 0x0e, 0x0260); |
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} else { |
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phy_write(phydev, 0x17, 0x2108); |
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phy_write(phydev, 0x0e, 0x0000); |
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} |
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return 0; |
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} |
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static int rtl8211c_config_init(struct phy_device *phydev) |
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{ |
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/* RTL8211C has an issue when operating in Gigabit slave mode */ |
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return phy_set_bits(phydev, MII_CTRL1000, |
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CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
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} |
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static int rtl8211f_config_init(struct phy_device *phydev) |
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{ |
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struct device *dev = &phydev->mdio.dev; |
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u16 val_txdly, val_rxdly; |
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u16 val; |
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int ret; |
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val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF; |
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phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val); |
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switch (phydev->interface) { |
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case PHY_INTERFACE_MODE_RGMII: |
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val_txdly = 0; |
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val_rxdly = 0; |
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break; |
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case PHY_INTERFACE_MODE_RGMII_RXID: |
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val_txdly = 0; |
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val_rxdly = RTL8211F_RX_DELAY; |
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break; |
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case PHY_INTERFACE_MODE_RGMII_TXID: |
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val_txdly = RTL8211F_TX_DELAY; |
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val_rxdly = 0; |
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break; |
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case PHY_INTERFACE_MODE_RGMII_ID: |
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val_txdly = RTL8211F_TX_DELAY; |
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val_rxdly = RTL8211F_RX_DELAY; |
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break; |
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default: /* the rest of the modes imply leaving delay as is. */ |
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return 0; |
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} |
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ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, |
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val_txdly); |
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if (ret < 0) { |
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dev_err(dev, "Failed to update the TX delay register\n"); |
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return ret; |
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} else if (ret) { |
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dev_dbg(dev, |
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"%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", |
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val_txdly ? "Enabling" : "Disabling"); |
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} else { |
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dev_dbg(dev, |
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"2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", |
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val_txdly ? "enabled" : "disabled"); |
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} |
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ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, |
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val_rxdly); |
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if (ret < 0) { |
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dev_err(dev, "Failed to update the RX delay register\n"); |
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return ret; |
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} else if (ret) { |
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dev_dbg(dev, |
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"%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", |
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val_rxdly ? "Enabling" : "Disabling"); |
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} else { |
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dev_dbg(dev, |
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"2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", |
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val_rxdly ? "enabled" : "disabled"); |
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} |
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return 0; |
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} |
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static int rtl8211e_config_init(struct phy_device *phydev) |
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{ |
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int ret = 0, oldpage; |
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u16 val; |
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/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ |
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switch (phydev->interface) { |
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case PHY_INTERFACE_MODE_RGMII: |
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val = RTL8211E_CTRL_DELAY | 0; |
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break; |
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case PHY_INTERFACE_MODE_RGMII_ID: |
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val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; |
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break; |
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case PHY_INTERFACE_MODE_RGMII_RXID: |
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val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; |
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break; |
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case PHY_INTERFACE_MODE_RGMII_TXID: |
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val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; |
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break; |
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default: /* the rest of the modes imply leaving delays as is. */ |
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return 0; |
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} |
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|
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/* According to a sample driver there is a 0x1c config register on the |
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* 0xa4 extension page (0x7) layout. It can be used to disable/enable |
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* the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. |
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* The configuration register definition: |
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* 14 = reserved |
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* 13 = Force Tx RX Delay controlled by bit12 bit11, |
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* 12 = RX Delay, 11 = TX Delay |
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* 10:0 = Test && debug settings reserved by realtek |
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*/ |
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oldpage = phy_select_page(phydev, 0x7); |
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if (oldpage < 0) |
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goto err_restore_page; |
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ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); |
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if (ret) |
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goto err_restore_page; |
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ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY |
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| RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, |
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val); |
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err_restore_page: |
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return phy_restore_page(phydev, oldpage, ret); |
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} |
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static int rtl8211b_suspend(struct phy_device *phydev) |
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{ |
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phy_write(phydev, MII_MMD_DATA, BIT(9)); |
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|
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return genphy_suspend(phydev); |
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} |
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static int rtl8211b_resume(struct phy_device *phydev) |
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{ |
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phy_write(phydev, MII_MMD_DATA, 0); |
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|
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return genphy_resume(phydev); |
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} |
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static int rtl8366rb_config_init(struct phy_device *phydev) |
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{ |
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int ret; |
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|
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ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, |
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RTL8366RB_POWER_SAVE_ON); |
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if (ret) { |
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dev_err(&phydev->mdio.dev, |
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"error enabling power management\n"); |
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} |
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|
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return ret; |
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} |
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|
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/* get actual speed to cover the downshift case */ |
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static int rtlgen_get_speed(struct phy_device *phydev) |
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{ |
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int val; |
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|
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if (!phydev->link) |
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return 0; |
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|
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val = phy_read_paged(phydev, 0xa43, 0x12); |
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if (val < 0) |
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return val; |
|
|
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switch (val & RTLGEN_SPEED_MASK) { |
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case 0x0000: |
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phydev->speed = SPEED_10; |
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break; |
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case 0x0010: |
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phydev->speed = SPEED_100; |
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break; |
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case 0x0020: |
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phydev->speed = SPEED_1000; |
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break; |
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case 0x0200: |
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phydev->speed = SPEED_10000; |
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break; |
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case 0x0210: |
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phydev->speed = SPEED_2500; |
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break; |
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case 0x0220: |
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phydev->speed = SPEED_5000; |
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break; |
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default: |
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break; |
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} |
|
|
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return 0; |
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} |
|
|
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static int rtlgen_read_status(struct phy_device *phydev) |
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{ |
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int ret; |
|
|
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ret = genphy_read_status(phydev); |
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if (ret < 0) |
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return ret; |
|
|
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return rtlgen_get_speed(phydev); |
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} |
|
|
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static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) |
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{ |
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int ret; |
|
|
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if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) { |
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rtl821x_write_page(phydev, 0xa5c); |
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ret = __phy_read(phydev, 0x12); |
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rtl821x_write_page(phydev, 0); |
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} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { |
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rtl821x_write_page(phydev, 0xa5d); |
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ret = __phy_read(phydev, 0x10); |
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rtl821x_write_page(phydev, 0); |
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} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { |
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rtl821x_write_page(phydev, 0xa5d); |
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ret = __phy_read(phydev, 0x11); |
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rtl821x_write_page(phydev, 0); |
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} else { |
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ret = -EOPNOTSUPP; |
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} |
|
|
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return ret; |
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} |
|
|
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static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, |
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u16 val) |
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{ |
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int ret; |
|
|
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if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { |
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rtl821x_write_page(phydev, 0xa5d); |
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ret = __phy_write(phydev, 0x10, val); |
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rtl821x_write_page(phydev, 0); |
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} else { |
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ret = -EOPNOTSUPP; |
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} |
|
|
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return ret; |
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} |
|
|
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static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) |
|
{ |
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int ret = rtlgen_read_mmd(phydev, devnum, regnum); |
|
|
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if (ret != -EOPNOTSUPP) |
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return ret; |
|
|
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if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) { |
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rtl821x_write_page(phydev, 0xa6e); |
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ret = __phy_read(phydev, 0x16); |
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rtl821x_write_page(phydev, 0); |
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} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { |
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rtl821x_write_page(phydev, 0xa6d); |
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ret = __phy_read(phydev, 0x12); |
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rtl821x_write_page(phydev, 0); |
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} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { |
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rtl821x_write_page(phydev, 0xa6d); |
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ret = __phy_read(phydev, 0x10); |
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rtl821x_write_page(phydev, 0); |
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} |
|
|
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return ret; |
|
} |
|
|
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static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, |
|
u16 val) |
|
{ |
|
int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); |
|
|
|
if (ret != -EOPNOTSUPP) |
|
return ret; |
|
|
|
if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { |
|
rtl821x_write_page(phydev, 0xa6d); |
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ret = __phy_write(phydev, 0x12, val); |
|
rtl821x_write_page(phydev, 0); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int rtl822x_get_features(struct phy_device *phydev) |
|
{ |
|
int val; |
|
|
|
val = phy_read_paged(phydev, 0xa61, 0x13); |
|
if (val < 0) |
|
return val; |
|
|
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
|
phydev->supported, val & RTL_SUPPORTS_2500FULL); |
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, |
|
phydev->supported, val & RTL_SUPPORTS_5000FULL); |
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, |
|
phydev->supported, val & RTL_SUPPORTS_10000FULL); |
|
|
|
return genphy_read_abilities(phydev); |
|
} |
|
|
|
static int rtl822x_config_aneg(struct phy_device *phydev) |
|
{ |
|
int ret = 0; |
|
|
|
if (phydev->autoneg == AUTONEG_ENABLE) { |
|
u16 adv2500 = 0; |
|
|
|
if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
|
phydev->advertising)) |
|
adv2500 = RTL_ADV_2500FULL; |
|
|
|
ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, |
|
RTL_ADV_2500FULL, adv2500); |
|
if (ret < 0) |
|
return ret; |
|
} |
|
|
|
return __genphy_config_aneg(phydev, ret); |
|
} |
|
|
|
static int rtl822x_read_status(struct phy_device *phydev) |
|
{ |
|
int ret; |
|
|
|
if (phydev->autoneg == AUTONEG_ENABLE) { |
|
int lpadv = phy_read_paged(phydev, 0xa5d, 0x13); |
|
|
|
if (lpadv < 0) |
|
return lpadv; |
|
|
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, |
|
phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL); |
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, |
|
phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL); |
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
|
phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL); |
|
} |
|
|
|
ret = genphy_read_status(phydev); |
|
if (ret < 0) |
|
return ret; |
|
|
|
return rtlgen_get_speed(phydev); |
|
} |
|
|
|
static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) |
|
{ |
|
int val; |
|
|
|
phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); |
|
val = phy_read(phydev, 0x13); |
|
phy_write(phydev, RTL821x_PAGE_SELECT, 0); |
|
|
|
return val >= 0 && val & RTL_SUPPORTS_2500FULL; |
|
} |
|
|
|
static int rtlgen_match_phy_device(struct phy_device *phydev) |
|
{ |
|
return phydev->phy_id == RTL_GENERIC_PHYID && |
|
!rtlgen_supports_2_5gbps(phydev); |
|
} |
|
|
|
static int rtl8226_match_phy_device(struct phy_device *phydev) |
|
{ |
|
return phydev->phy_id == RTL_GENERIC_PHYID && |
|
rtlgen_supports_2_5gbps(phydev); |
|
} |
|
|
|
static int rtlgen_resume(struct phy_device *phydev) |
|
{ |
|
int ret = genphy_resume(phydev); |
|
|
|
/* Internal PHY's from RTL8168h up may not be instantly ready */ |
|
msleep(20); |
|
|
|
return ret; |
|
} |
|
|
|
static int rtl9000a_config_init(struct phy_device *phydev) |
|
{ |
|
phydev->autoneg = AUTONEG_DISABLE; |
|
phydev->speed = SPEED_100; |
|
phydev->duplex = DUPLEX_FULL; |
|
|
|
return 0; |
|
} |
|
|
|
static int rtl9000a_config_aneg(struct phy_device *phydev) |
|
{ |
|
int ret; |
|
u16 ctl = 0; |
|
|
|
switch (phydev->master_slave_set) { |
|
case MASTER_SLAVE_CFG_MASTER_FORCE: |
|
ctl |= CTL1000_AS_MASTER; |
|
break; |
|
case MASTER_SLAVE_CFG_SLAVE_FORCE: |
|
break; |
|
case MASTER_SLAVE_CFG_UNKNOWN: |
|
case MASTER_SLAVE_CFG_UNSUPPORTED: |
|
return 0; |
|
default: |
|
phydev_warn(phydev, "Unsupported Master/Slave mode\n"); |
|
return -EOPNOTSUPP; |
|
} |
|
|
|
ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); |
|
if (ret == 1) |
|
ret = genphy_soft_reset(phydev); |
|
|
|
return ret; |
|
} |
|
|
|
static int rtl9000a_read_status(struct phy_device *phydev) |
|
{ |
|
int ret; |
|
|
|
phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; |
|
phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; |
|
|
|
ret = genphy_update_link(phydev); |
|
if (ret) |
|
return ret; |
|
|
|
ret = phy_read(phydev, MII_CTRL1000); |
|
if (ret < 0) |
|
return ret; |
|
if (ret & CTL1000_AS_MASTER) |
|
phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; |
|
else |
|
phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; |
|
|
|
ret = phy_read(phydev, MII_STAT1000); |
|
if (ret < 0) |
|
return ret; |
|
if (ret & LPA_1000MSRES) |
|
phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; |
|
else |
|
phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; |
|
|
|
return 0; |
|
} |
|
|
|
static int rtl9000a_ack_interrupt(struct phy_device *phydev) |
|
{ |
|
int err; |
|
|
|
err = phy_read(phydev, RTL8211F_INSR); |
|
|
|
return (err < 0) ? err : 0; |
|
} |
|
|
|
static int rtl9000a_config_intr(struct phy_device *phydev) |
|
{ |
|
u16 val; |
|
int err; |
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
|
err = rtl9000a_ack_interrupt(phydev); |
|
if (err) |
|
return err; |
|
|
|
val = (u16)~RTL9000A_GINMR_LINK_STATUS; |
|
err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); |
|
} else { |
|
val = ~0; |
|
err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); |
|
if (err) |
|
return err; |
|
|
|
err = rtl9000a_ack_interrupt(phydev); |
|
} |
|
|
|
return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); |
|
} |
|
|
|
static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) |
|
{ |
|
int irq_status; |
|
|
|
irq_status = phy_read(phydev, RTL8211F_INSR); |
|
if (irq_status < 0) { |
|
phy_error(phydev); |
|
return IRQ_NONE; |
|
} |
|
|
|
if (!(irq_status & RTL8211F_INER_LINK_STATUS)) |
|
return IRQ_NONE; |
|
|
|
phy_trigger_machine(phydev); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static struct phy_driver realtek_drvs[] = { |
|
{ |
|
PHY_ID_MATCH_EXACT(0x00008201), |
|
.name = "RTL8201CP Ethernet", |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc816), |
|
.name = "RTL8201F Fast Ethernet", |
|
.config_intr = &rtl8201_config_intr, |
|
.handle_interrupt = rtl8201_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_MODEL(0x001cc880), |
|
.name = "RTL8208 Fast Ethernet", |
|
.read_mmd = genphy_read_mmd_unsupported, |
|
.write_mmd = genphy_write_mmd_unsupported, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc910), |
|
.name = "RTL8211 Gigabit Ethernet", |
|
.config_aneg = rtl8211_config_aneg, |
|
.read_mmd = &genphy_read_mmd_unsupported, |
|
.write_mmd = &genphy_write_mmd_unsupported, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc912), |
|
.name = "RTL8211B Gigabit Ethernet", |
|
.config_intr = &rtl8211b_config_intr, |
|
.handle_interrupt = rtl821x_handle_interrupt, |
|
.read_mmd = &genphy_read_mmd_unsupported, |
|
.write_mmd = &genphy_write_mmd_unsupported, |
|
.suspend = rtl8211b_suspend, |
|
.resume = rtl8211b_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc913), |
|
.name = "RTL8211C Gigabit Ethernet", |
|
.config_init = rtl8211c_config_init, |
|
.read_mmd = &genphy_read_mmd_unsupported, |
|
.write_mmd = &genphy_write_mmd_unsupported, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc914), |
|
.name = "RTL8211DN Gigabit Ethernet", |
|
.config_intr = rtl8211e_config_intr, |
|
.handle_interrupt = rtl821x_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc915), |
|
.name = "RTL8211E Gigabit Ethernet", |
|
.config_init = &rtl8211e_config_init, |
|
.config_intr = &rtl8211e_config_intr, |
|
.handle_interrupt = rtl821x_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc916), |
|
.name = "RTL8211F Gigabit Ethernet", |
|
.config_init = &rtl8211f_config_init, |
|
.read_status = rtlgen_read_status, |
|
.config_intr = &rtl8211f_config_intr, |
|
.handle_interrupt = rtl8211f_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
.name = "Generic FE-GE Realtek PHY", |
|
.match_phy_device = rtlgen_match_phy_device, |
|
.read_status = rtlgen_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
.read_mmd = rtlgen_read_mmd, |
|
.write_mmd = rtlgen_write_mmd, |
|
}, { |
|
.name = "RTL8226 2.5Gbps PHY", |
|
.match_phy_device = rtl8226_match_phy_device, |
|
.get_features = rtl822x_get_features, |
|
.config_aneg = rtl822x_config_aneg, |
|
.read_status = rtl822x_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
.read_mmd = rtl822x_read_mmd, |
|
.write_mmd = rtl822x_write_mmd, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc840), |
|
.name = "RTL8226B_RTL8221B 2.5Gbps PHY", |
|
.get_features = rtl822x_get_features, |
|
.config_aneg = rtl822x_config_aneg, |
|
.read_status = rtl822x_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
.read_mmd = rtl822x_read_mmd, |
|
.write_mmd = rtl822x_write_mmd, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc838), |
|
.name = "RTL8226-CG 2.5Gbps PHY", |
|
.get_features = rtl822x_get_features, |
|
.config_aneg = rtl822x_config_aneg, |
|
.read_status = rtl822x_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc848), |
|
.name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", |
|
.get_features = rtl822x_get_features, |
|
.config_aneg = rtl822x_config_aneg, |
|
.read_status = rtl822x_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc849), |
|
.name = "RTL8221B-VB-CG 2.5Gbps PHY", |
|
.get_features = rtl822x_get_features, |
|
.config_aneg = rtl822x_config_aneg, |
|
.read_status = rtl822x_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc84a), |
|
.name = "RTL8221B-VM-CG 2.5Gbps PHY", |
|
.get_features = rtl822x_get_features, |
|
.config_aneg = rtl822x_config_aneg, |
|
.read_status = rtl822x_read_status, |
|
.suspend = genphy_suspend, |
|
.resume = rtlgen_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001cc961), |
|
.name = "RTL8366RB Gigabit Ethernet", |
|
.config_init = &rtl8366rb_config_init, |
|
/* These interrupts are handled by the irq controller |
|
* embedded inside the RTL8366RB, they get unmasked when the |
|
* irq is requested and ACKed by reading the status register, |
|
* which is done by the irqchip code. |
|
*/ |
|
.config_intr = genphy_no_config_intr, |
|
.handle_interrupt = genphy_handle_interrupt_no_ack, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
}, { |
|
PHY_ID_MATCH_EXACT(0x001ccb00), |
|
.name = "RTL9000AA_RTL9000AN Ethernet", |
|
.features = PHY_BASIC_T1_FEATURES, |
|
.config_init = rtl9000a_config_init, |
|
.config_aneg = rtl9000a_config_aneg, |
|
.read_status = rtl9000a_read_status, |
|
.config_intr = rtl9000a_config_intr, |
|
.handle_interrupt = rtl9000a_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
.read_page = rtl821x_read_page, |
|
.write_page = rtl821x_write_page, |
|
}, |
|
}; |
|
|
|
module_phy_driver(realtek_drvs); |
|
|
|
static const struct mdio_device_id __maybe_unused realtek_tbl[] = { |
|
{ PHY_ID_MATCH_VENDOR(0x001cc800) }, |
|
{ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(mdio, realtek_tbl);
|
|
|