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455 lines
13 KiB
455 lines
13 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Huawei HiNIC PCI Express Linux driver |
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* Copyright(c) 2017 Huawei Technologies Co., Ltd |
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*/ |
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#ifndef HINIC_HW_WQE_H |
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#define HINIC_HW_WQE_H |
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#include "hinic_common.h" |
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#define HINIC_CMDQ_CTRL_PI_SHIFT 0 |
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#define HINIC_CMDQ_CTRL_CMD_SHIFT 16 |
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#define HINIC_CMDQ_CTRL_MOD_SHIFT 24 |
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#define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT 29 |
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#define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT 31 |
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#define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF |
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#define HINIC_CMDQ_CTRL_CMD_MASK 0xFF |
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#define HINIC_CMDQ_CTRL_MOD_MASK 0x1F |
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#define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3 |
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#define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1 |
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#define HINIC_CMDQ_CTRL_SET(val, member) \ |
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(((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \ |
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<< HINIC_CMDQ_CTRL_##member##_SHIFT) |
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#define HINIC_CMDQ_CTRL_GET(val, member) \ |
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(((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \ |
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& HINIC_CMDQ_CTRL_##member##_MASK) |
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#define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0 |
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#define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT 15 |
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#define HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT 22 |
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#define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT 23 |
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#define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT 27 |
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#define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT 29 |
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#define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT 31 |
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#define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF |
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#define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1 |
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#define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1 |
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#define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK 0x1 |
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#define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK 0x3 |
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#define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK 0x3 |
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#define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK 0x1 |
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#define HINIC_CMDQ_WQE_HEADER_SET(val, member) \ |
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(((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \ |
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<< HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) |
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#define HINIC_CMDQ_WQE_HEADER_GET(val, member) \ |
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(((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \ |
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& HINIC_CMDQ_WQE_HEADER_##member##_MASK) |
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#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 |
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#define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16 |
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#define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22 |
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#define HINIC_SQ_CTRL_LEN_SHIFT 29 |
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#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF |
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#define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F |
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#define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1 |
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#define HINIC_SQ_CTRL_LEN_MASK 0x3 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT 28 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT 29 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFF |
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#define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF |
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#define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK 0x1 |
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#define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7 |
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#define HINIC_SQ_CTRL_SET(val, member) \ |
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(((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \ |
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<< HINIC_SQ_CTRL_##member##_SHIFT) |
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#define HINIC_SQ_CTRL_GET(val, member) \ |
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(((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \ |
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& HINIC_SQ_CTRL_##member##_MASK) |
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#define HINIC_SQ_CTRL_CLEAR(val, member) \ |
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((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \ |
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<< HINIC_SQ_CTRL_##member##_SHIFT))) |
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#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0 |
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#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8 |
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#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10 |
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#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12 |
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#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13 |
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/* 1 bit reserved */ |
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#define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15 |
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#define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16 |
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#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF |
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#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3 |
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#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3 |
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#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1 |
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#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1 |
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/* 1 bit reserved */ |
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#define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1 |
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#define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF |
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#define HINIC_SQ_TASK_INFO0_SET(val, member) \ |
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(((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \ |
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HINIC_SQ_TASK_INFO0_##member##_SHIFT) |
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/* 8 bits reserved */ |
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#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8 |
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#define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16 |
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#define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT 24 |
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/* 8 bits reserved */ |
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#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF |
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#define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFF |
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#define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFF |
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#define HINIC_SQ_TASK_INFO1_SET(val, member) \ |
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(((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \ |
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HINIC_SQ_TASK_INFO1_##member##_SHIFT) |
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#define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0 |
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#define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8 |
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#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16 |
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/* 1 bit reserved */ |
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#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 24 |
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/* 8 bits reserved */ |
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#define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFF |
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#define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFF |
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#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7 |
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/* 1 bit reserved */ |
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#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3 |
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/* 8 bits reserved */ |
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#define HINIC_SQ_TASK_INFO2_SET(val, member) \ |
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(((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \ |
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HINIC_SQ_TASK_INFO2_##member##_SHIFT) |
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/* 31 bits reserved */ |
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#define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31 |
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/* 31 bits reserved */ |
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#define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1 |
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#define HINIC_SQ_TASK_INFO4_SET(val, member) \ |
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(((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \ |
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HINIC_SQ_TASK_INFO4_##member##_SHIFT) |
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#define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31 |
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#define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1 |
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#define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT 0 |
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#define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK 0xFFFFU |
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#define HINIC_RQ_CQE_STATUS_GET(val, member) \ |
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(((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \ |
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HINIC_RQ_CQE_STATUS_##member##_MASK) |
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#define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \ |
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((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \ |
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HINIC_RQ_CQE_STATUS_##member##_SHIFT))) |
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#define HINIC_RQ_CQE_SGE_LEN_SHIFT 16 |
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#define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF |
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#define HINIC_RQ_CQE_SGE_GET(val, member) \ |
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(((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \ |
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HINIC_RQ_CQE_SGE_##member##_MASK) |
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#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 |
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#define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15 |
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#define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27 |
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#define HINIC_RQ_CTRL_LEN_SHIFT 29 |
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#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF |
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#define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1 |
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#define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3 |
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#define HINIC_RQ_CTRL_LEN_MASK 0x3 |
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#define HINIC_RQ_CTRL_SET(val, member) \ |
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(((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \ |
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HINIC_RQ_CTRL_##member##_SHIFT) |
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#define HINIC_SQ_WQE_SIZE(nr_sges) \ |
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(sizeof(struct hinic_sq_ctrl) + \ |
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sizeof(struct hinic_sq_task) + \ |
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(nr_sges) * sizeof(struct hinic_sq_bufdesc)) |
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#define HINIC_SCMD_DATA_LEN 16 |
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#define HINIC_MAX_SQ_BUFDESCS 17 |
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#define HINIC_SQ_WQE_MAX_SIZE 320 |
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#define HINIC_RQ_WQE_SIZE 32 |
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#define HINIC_MSS_DEFAULT 0x3E00 |
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#define HINIC_MSS_MIN 0x50 |
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#define RQ_CQE_STATUS_NUM_LRO_SHIFT 16 |
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#define RQ_CQE_STATUS_NUM_LRO_MASK 0xFFU |
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#define RQ_CQE_STATUS_GET(val, member) (((val) >> \ |
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RQ_CQE_STATUS_##member##_SHIFT) & \ |
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RQ_CQE_STATUS_##member##_MASK) |
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#define HINIC_GET_RX_NUM_LRO(status) \ |
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RQ_CQE_STATUS_GET(status, NUM_LRO) |
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#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT 0 |
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#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK 0xFFFU |
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#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT 21 |
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#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK 0x1U |
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#define RQ_CQE_OFFOLAD_TYPE_GET(val, member) (((val) >> \ |
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RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \ |
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RQ_CQE_OFFOLAD_TYPE_##member##_MASK) |
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#define HINIC_GET_RX_PKT_TYPE(offload_type) \ |
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RQ_CQE_OFFOLAD_TYPE_GET(offload_type, PKT_TYPE) |
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#define HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type) \ |
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RQ_CQE_OFFOLAD_TYPE_GET(offload_type, VLAN_EN) |
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#define RQ_CQE_SGE_VLAN_MASK 0xFFFFU |
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#define RQ_CQE_SGE_VLAN_SHIFT 0 |
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#define RQ_CQE_SGE_GET(val, member) (((val) >> \ |
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RQ_CQE_SGE_##member##_SHIFT) & \ |
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RQ_CQE_SGE_##member##_MASK) |
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#define HINIC_GET_RX_VLAN_TAG(vlan_len) \ |
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RQ_CQE_SGE_GET(vlan_len, VLAN) |
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#define HINIC_RSS_TYPE_VALID_SHIFT 23 |
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#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24 |
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#define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25 |
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#define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26 |
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#define HINIC_RSS_TYPE_IPV6_SHIFT 27 |
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#define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28 |
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#define HINIC_RSS_TYPE_IPV4_SHIFT 29 |
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#define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30 |
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#define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31 |
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#define HINIC_RSS_TYPE_SET(val, member) \ |
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(((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT) |
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#define HINIC_RSS_TYPE_GET(val, member) \ |
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(((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1) |
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enum hinic_l4offload_type { |
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HINIC_L4_OFF_DISABLE = 0, |
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HINIC_TCP_OFFLOAD_ENABLE = 1, |
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HINIC_SCTP_OFFLOAD_ENABLE = 2, |
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HINIC_UDP_OFFLOAD_ENABLE = 3, |
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}; |
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enum hinic_vlan_offload { |
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HINIC_VLAN_OFF_DISABLE = 0, |
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HINIC_VLAN_OFF_ENABLE = 1, |
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}; |
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enum hinic_pkt_parsed { |
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HINIC_PKT_NOT_PARSED = 0, |
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HINIC_PKT_PARSED = 1, |
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}; |
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enum hinic_l3_offload_type { |
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L3TYPE_UNKNOWN = 0, |
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IPV6_PKT = 1, |
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IPV4_PKT_NO_CHKSUM_OFFLOAD = 2, |
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IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3, |
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}; |
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enum hinic_l4_offload_type { |
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OFFLOAD_DISABLE = 0, |
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TCP_OFFLOAD_ENABLE = 1, |
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SCTP_OFFLOAD_ENABLE = 2, |
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UDP_OFFLOAD_ENABLE = 3, |
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}; |
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enum hinic_l4_tunnel_type { |
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NOT_TUNNEL, |
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TUNNEL_UDP_NO_CSUM, |
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TUNNEL_UDP_CSUM, |
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}; |
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enum hinic_outer_l3type { |
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HINIC_OUTER_L3TYPE_UNKNOWN = 0, |
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HINIC_OUTER_L3TYPE_IPV6 = 1, |
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HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2, |
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HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3, |
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}; |
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enum hinic_media_type { |
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HINIC_MEDIA_UNKNOWN = 0, |
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}; |
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enum hinic_l2type { |
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HINIC_L2TYPE_ETH = 0, |
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}; |
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enum hinc_tunnel_l4type { |
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HINIC_TUNNEL_L4TYPE_UNKNOWN = 0, |
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}; |
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struct hinic_cmdq_header { |
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u32 header_info; |
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u32 saved_data; |
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}; |
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struct hinic_status { |
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u32 status_info; |
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}; |
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struct hinic_ctrl { |
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u32 ctrl_info; |
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}; |
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struct hinic_sge_resp { |
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struct hinic_sge sge; |
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u32 rsvd; |
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}; |
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struct hinic_cmdq_completion { |
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/* HW Format */ |
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union { |
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struct hinic_sge_resp sge_resp; |
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u64 direct_resp; |
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}; |
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}; |
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struct hinic_scmd_bufdesc { |
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u32 buf_len; |
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u32 rsvd; |
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u8 data[HINIC_SCMD_DATA_LEN]; |
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}; |
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struct hinic_lcmd_bufdesc { |
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struct hinic_sge sge; |
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u32 rsvd1; |
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u64 rsvd2; |
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u64 rsvd3; |
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}; |
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struct hinic_cmdq_wqe_scmd { |
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struct hinic_cmdq_header header; |
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u64 rsvd; |
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struct hinic_status status; |
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struct hinic_ctrl ctrl; |
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struct hinic_cmdq_completion completion; |
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struct hinic_scmd_bufdesc buf_desc; |
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}; |
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struct hinic_cmdq_wqe_lcmd { |
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struct hinic_cmdq_header header; |
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struct hinic_status status; |
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struct hinic_ctrl ctrl; |
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struct hinic_cmdq_completion completion; |
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struct hinic_lcmd_bufdesc buf_desc; |
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}; |
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struct hinic_cmdq_direct_wqe { |
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struct hinic_cmdq_wqe_scmd wqe_scmd; |
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}; |
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struct hinic_cmdq_wqe { |
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/* HW Format */ |
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union { |
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struct hinic_cmdq_direct_wqe direct_wqe; |
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struct hinic_cmdq_wqe_lcmd wqe_lcmd; |
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}; |
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}; |
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struct hinic_sq_ctrl { |
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u32 ctrl_info; |
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u32 queue_info; |
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}; |
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struct hinic_sq_task { |
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u32 pkt_info0; |
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u32 pkt_info1; |
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u32 pkt_info2; |
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u32 ufo_v6_identify; |
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u32 pkt_info4; |
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u32 zero_pad; |
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}; |
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struct hinic_sq_bufdesc { |
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struct hinic_sge sge; |
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u32 rsvd; |
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}; |
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struct hinic_sq_wqe { |
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struct hinic_sq_ctrl ctrl; |
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struct hinic_sq_task task; |
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struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS]; |
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}; |
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struct hinic_rq_cqe { |
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u32 status; |
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u32 len; |
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u32 offload_type; |
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u32 rsvd3; |
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u32 rsvd4; |
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u32 rsvd5; |
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u32 rsvd6; |
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u32 rsvd7; |
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}; |
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struct hinic_rq_ctrl { |
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u32 ctrl_info; |
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}; |
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struct hinic_rq_cqe_sect { |
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struct hinic_sge sge; |
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u32 rsvd; |
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}; |
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struct hinic_rq_bufdesc { |
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u32 hi_addr; |
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u32 lo_addr; |
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}; |
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struct hinic_rq_wqe { |
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struct hinic_rq_ctrl ctrl; |
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u32 rsvd; |
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struct hinic_rq_cqe_sect cqe_sect; |
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struct hinic_rq_bufdesc buf_desc; |
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}; |
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struct hinic_hw_wqe { |
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/* HW Format */ |
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union { |
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struct hinic_cmdq_wqe cmdq_wqe; |
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struct hinic_sq_wqe sq_wqe; |
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struct hinic_rq_wqe rq_wqe; |
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}; |
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}; |
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#endif
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