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434 lines
12 KiB
434 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ |
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/* |
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Copyright (c) 2001, 2002 by D-Link Corporation |
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Written by Edward Peng.<[email protected]> |
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Created 03-May-2001, base on Linux' sundance.c. |
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*/ |
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#ifndef __DL2K_H__ |
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#define __DL2K_H__ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/timer.h> |
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#include <linux/errno.h> |
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#include <linux/ioport.h> |
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#include <linux/slab.h> |
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#include <linux/interrupt.h> |
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#include <linux/pci.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/skbuff.h> |
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#include <linux/crc32.h> |
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#include <linux/ethtool.h> |
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#include <linux/mii.h> |
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#include <linux/bitops.h> |
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#include <asm/processor.h> /* Processor type for cache alignment. */ |
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#include <asm/io.h> |
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#include <linux/uaccess.h> |
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#include <linux/delay.h> |
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#include <linux/spinlock.h> |
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#include <linux/time.h> |
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#define TX_RING_SIZE 256 |
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#define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/ |
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#define RX_RING_SIZE 256 |
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#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc) |
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#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc) |
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/* Offsets to the device registers. |
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Unlike software-only systems, device drivers interact with complex hardware. |
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It's not useful to define symbolic names for every register bit in the |
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device. The name can only partially document the semantics and make |
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the driver longer and more difficult to read. |
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In general, only the important configuration values or bits changed |
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multiple times should be defined symbolically. |
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*/ |
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enum dl2x_offsets { |
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/* I/O register offsets */ |
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DMACtrl = 0x00, |
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RxDMAStatus = 0x08, |
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TFDListPtr0 = 0x10, |
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TFDListPtr1 = 0x14, |
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TxDMABurstThresh = 0x18, |
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TxDMAUrgentThresh = 0x19, |
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TxDMAPollPeriod = 0x1a, |
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RFDListPtr0 = 0x1c, |
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RFDListPtr1 = 0x20, |
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RxDMABurstThresh = 0x24, |
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RxDMAUrgentThresh = 0x25, |
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RxDMAPollPeriod = 0x26, |
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RxDMAIntCtrl = 0x28, |
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DebugCtrl = 0x2c, |
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ASICCtrl = 0x30, |
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FifoCtrl = 0x38, |
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RxEarlyThresh = 0x3a, |
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FlowOffThresh = 0x3c, |
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FlowOnThresh = 0x3e, |
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TxStartThresh = 0x44, |
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EepromData = 0x48, |
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EepromCtrl = 0x4a, |
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ExpromAddr = 0x4c, |
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Exprodata = 0x50, |
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WakeEvent = 0x51, |
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CountDown = 0x54, |
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IntStatusAck = 0x5a, |
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IntEnable = 0x5c, |
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IntStatus = 0x5e, |
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TxStatus = 0x60, |
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MACCtrl = 0x6c, |
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VLANTag = 0x70, |
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PhyCtrl = 0x76, |
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StationAddr0 = 0x78, |
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StationAddr1 = 0x7a, |
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StationAddr2 = 0x7c, |
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VLANId = 0x80, |
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MaxFrameSize = 0x86, |
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ReceiveMode = 0x88, |
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HashTable0 = 0x8c, |
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HashTable1 = 0x90, |
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RmonStatMask = 0x98, |
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StatMask = 0x9c, |
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RxJumboFrames = 0xbc, |
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TCPCheckSumErrors = 0xc0, |
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IPCheckSumErrors = 0xc2, |
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UDPCheckSumErrors = 0xc4, |
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TxJumboFrames = 0xf4, |
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/* Ethernet MIB statistic register offsets */ |
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OctetRcvOk = 0xa8, |
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McstOctetRcvOk = 0xac, |
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BcstOctetRcvOk = 0xb0, |
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FramesRcvOk = 0xb4, |
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McstFramesRcvdOk = 0xb8, |
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BcstFramesRcvdOk = 0xbe, |
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MacControlFramesRcvd = 0xc6, |
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FrameTooLongErrors = 0xc8, |
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InRangeLengthErrors = 0xca, |
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FramesCheckSeqErrors = 0xcc, |
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FramesLostRxErrors = 0xce, |
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OctetXmtOk = 0xd0, |
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McstOctetXmtOk = 0xd4, |
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BcstOctetXmtOk = 0xd8, |
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FramesXmtOk = 0xdc, |
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McstFramesXmtdOk = 0xe0, |
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FramesWDeferredXmt = 0xe4, |
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LateCollisions = 0xe8, |
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MultiColFrames = 0xec, |
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SingleColFrames = 0xf0, |
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BcstFramesXmtdOk = 0xf6, |
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CarrierSenseErrors = 0xf8, |
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MacControlFramesXmtd = 0xfa, |
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FramesAbortXSColls = 0xfc, |
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FramesWEXDeferal = 0xfe, |
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/* RMON statistic register offsets */ |
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EtherStatsCollisions = 0x100, |
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EtherStatsOctetsTransmit = 0x104, |
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EtherStatsPktsTransmit = 0x108, |
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EtherStatsPkts64OctetTransmit = 0x10c, |
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EtherStats65to127OctetsTransmit = 0x110, |
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EtherStatsPkts128to255OctetsTransmit = 0x114, |
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EtherStatsPkts256to511OctetsTransmit = 0x118, |
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EtherStatsPkts512to1023OctetsTransmit = 0x11c, |
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EtherStatsPkts1024to1518OctetsTransmit = 0x120, |
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EtherStatsCRCAlignErrors = 0x124, |
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EtherStatsUndersizePkts = 0x128, |
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EtherStatsFragments = 0x12c, |
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EtherStatsJabbers = 0x130, |
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EtherStatsOctets = 0x134, |
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EtherStatsPkts = 0x138, |
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EtherStats64Octets = 0x13c, |
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EtherStatsPkts65to127Octets = 0x140, |
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EtherStatsPkts128to255Octets = 0x144, |
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EtherStatsPkts256to511Octets = 0x148, |
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EtherStatsPkts512to1023Octets = 0x14c, |
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EtherStatsPkts1024to1518Octets = 0x150, |
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}; |
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/* Bits in the interrupt status/mask registers. */ |
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enum IntStatus_bits { |
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InterruptStatus = 0x0001, |
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HostError = 0x0002, |
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MACCtrlFrame = 0x0008, |
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TxComplete = 0x0004, |
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RxComplete = 0x0010, |
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RxEarly = 0x0020, |
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IntRequested = 0x0040, |
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UpdateStats = 0x0080, |
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LinkEvent = 0x0100, |
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TxDMAComplete = 0x0200, |
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RxDMAComplete = 0x0400, |
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RFDListEnd = 0x0800, |
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RxDMAPriority = 0x1000, |
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}; |
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/* Bits in the ReceiveMode register. */ |
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enum ReceiveMode_bits { |
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ReceiveUnicast = 0x0001, |
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ReceiveMulticast = 0x0002, |
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ReceiveBroadcast = 0x0004, |
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ReceiveAllFrames = 0x0008, |
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ReceiveMulticastHash = 0x0010, |
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ReceiveIPMulticast = 0x0020, |
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ReceiveVLANMatch = 0x0100, |
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ReceiveVLANHash = 0x0200, |
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}; |
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/* Bits in MACCtrl. */ |
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enum MACCtrl_bits { |
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DuplexSelect = 0x20, |
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TxFlowControlEnable = 0x80, |
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RxFlowControlEnable = 0x0100, |
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RcvFCS = 0x200, |
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AutoVLANtagging = 0x1000, |
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AutoVLANuntagging = 0x2000, |
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StatsEnable = 0x00200000, |
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StatsDisable = 0x00400000, |
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StatsEnabled = 0x00800000, |
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TxEnable = 0x01000000, |
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TxDisable = 0x02000000, |
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TxEnabled = 0x04000000, |
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RxEnable = 0x08000000, |
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RxDisable = 0x10000000, |
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RxEnabled = 0x20000000, |
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}; |
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enum ASICCtrl_LoWord_bits { |
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PhyMedia = 0x0080, |
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}; |
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enum ASICCtrl_HiWord_bits { |
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GlobalReset = 0x0001, |
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RxReset = 0x0002, |
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TxReset = 0x0004, |
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DMAReset = 0x0008, |
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FIFOReset = 0x0010, |
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NetworkReset = 0x0020, |
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HostReset = 0x0040, |
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ResetBusy = 0x0400, |
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}; |
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#define IPG_AC_LED_MODE BIT(14) |
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#define IPG_AC_LED_SPEED BIT(27) |
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#define IPG_AC_LED_MODE_BIT_1 BIT(29) |
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/* Transmit Frame Control bits */ |
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enum TFC_bits { |
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DwordAlign = 0x00000000, |
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WordAlignDisable = 0x00030000, |
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WordAlign = 0x00020000, |
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TCPChecksumEnable = 0x00040000, |
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UDPChecksumEnable = 0x00080000, |
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IPChecksumEnable = 0x00100000, |
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FCSAppendDisable = 0x00200000, |
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TxIndicate = 0x00400000, |
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TxDMAIndicate = 0x00800000, |
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FragCountShift = 24, |
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VLANTagInsert = 0x0000000010000000, |
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TFDDone = 0x80000000, |
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VIDShift = 32, |
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UsePriorityShift = 48, |
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}; |
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/* Receive Frames Status bits */ |
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enum RFS_bits { |
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RxFIFOOverrun = 0x00010000, |
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RxRuntFrame = 0x00020000, |
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RxAlignmentError = 0x00040000, |
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RxFCSError = 0x00080000, |
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RxOverSizedFrame = 0x00100000, |
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RxLengthError = 0x00200000, |
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VLANDetected = 0x00400000, |
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TCPDetected = 0x00800000, |
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TCPError = 0x01000000, |
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UDPDetected = 0x02000000, |
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UDPError = 0x04000000, |
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IPDetected = 0x08000000, |
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IPError = 0x10000000, |
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FrameStart = 0x20000000, |
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FrameEnd = 0x40000000, |
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RFDDone = 0x80000000, |
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TCIShift = 32, |
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RFS_Errors = 0x003f0000, |
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}; |
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#define MII_RESET_TIME_OUT 10000 |
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/* MII register */ |
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enum _mii_reg { |
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MII_PHY_SCR = 16, |
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}; |
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/* PCS register */ |
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enum _pcs_reg { |
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PCS_BMCR = 0, |
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PCS_BMSR = 1, |
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PCS_ANAR = 4, |
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PCS_ANLPAR = 5, |
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PCS_ANER = 6, |
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PCS_ANNPT = 7, |
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PCS_ANLPRNP = 8, |
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PCS_ESR = 15, |
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}; |
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/* IEEE Extened Status Register */ |
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enum _mii_esr { |
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MII_ESR_1000BX_FD = 0x8000, |
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MII_ESR_1000BX_HD = 0x4000, |
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MII_ESR_1000BT_FD = 0x2000, |
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MII_ESR_1000BT_HD = 0x1000, |
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}; |
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/* PHY Specific Control Register */ |
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#if 0 |
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typedef union t_MII_PHY_SCR { |
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u16 image; |
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struct { |
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u16 disable_jabber:1; // bit 0 |
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u16 polarity_reversal:1; // bit 1 |
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u16 SEQ_test:1; // bit 2 |
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u16 _bit_3:1; // bit 3 |
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u16 disable_CLK125:1; // bit 4 |
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u16 mdi_crossover_mode:2; // bit 6:5 |
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u16 enable_ext_dist:1; // bit 7 |
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u16 _bit_8_9:2; // bit 9:8 |
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u16 force_link:1; // bit 10 |
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u16 assert_CRS:1; // bit 11 |
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u16 rcv_fifo_depth:2; // bit 13:12 |
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u16 xmit_fifo_depth:2; // bit 15:14 |
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} bits; |
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} PHY_SCR_t, *PPHY_SCR_t; |
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#endif |
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typedef enum t_MII_ADMIN_STATUS { |
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adm_reset, |
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adm_operational, |
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adm_loopback, |
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adm_power_down, |
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adm_isolate |
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} MII_ADMIN_t, *PMII_ADMIN_t; |
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/* Physical Coding Sublayer Management (PCS) */ |
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/* PCS control and status registers bitmap as the same as MII */ |
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/* PCS Extended Status register bitmap as the same as MII */ |
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/* PCS ANAR */ |
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enum _pcs_anar { |
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PCS_ANAR_NEXT_PAGE = 0x8000, |
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PCS_ANAR_REMOTE_FAULT = 0x3000, |
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PCS_ANAR_ASYMMETRIC = 0x0100, |
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PCS_ANAR_PAUSE = 0x0080, |
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PCS_ANAR_HALF_DUPLEX = 0x0040, |
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PCS_ANAR_FULL_DUPLEX = 0x0020, |
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}; |
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/* PCS ANLPAR */ |
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enum _pcs_anlpar { |
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PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, |
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PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT, |
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PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC, |
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PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE, |
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PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX, |
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PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX, |
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}; |
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typedef struct t_SROM { |
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u16 config_param; /* 0x00 */ |
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u16 asic_ctrl; /* 0x02 */ |
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u16 sub_vendor_id; /* 0x04 */ |
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u16 sub_system_id; /* 0x06 */ |
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u16 pci_base_1; /* 0x08 (IP1000A only) */ |
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u16 pci_base_2; /* 0x0a (IP1000A only) */ |
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u16 led_mode; /* 0x0c (IP1000A only) */ |
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u16 reserved1[9]; /* 0x0e-0x1f */ |
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u8 mac_addr[6]; /* 0x20-0x25 */ |
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u8 reserved2[10]; /* 0x26-0x2f */ |
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u8 sib[204]; /* 0x30-0xfb */ |
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u32 crc; /* 0xfc-0xff */ |
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} SROM_t, *PSROM_t; |
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/* Ioctl custom data */ |
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struct ioctl_data { |
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char signature[10]; |
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int cmd; |
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int len; |
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char *data; |
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}; |
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/* The Rx and Tx buffer descriptors. */ |
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struct netdev_desc { |
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__le64 next_desc; |
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__le64 status; |
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__le64 fraginfo; |
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}; |
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#define PRIV_ALIGN 15 /* Required alignment mask */ |
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/* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment |
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within the structure. */ |
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struct netdev_private { |
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/* Descriptor rings first for alignment. */ |
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struct netdev_desc *rx_ring; |
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struct netdev_desc *tx_ring; |
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struct sk_buff *rx_skbuff[RX_RING_SIZE]; |
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struct sk_buff *tx_skbuff[TX_RING_SIZE]; |
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dma_addr_t tx_ring_dma; |
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dma_addr_t rx_ring_dma; |
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struct pci_dev *pdev; |
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void __iomem *ioaddr; |
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void __iomem *eeprom_addr; |
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spinlock_t tx_lock; |
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spinlock_t rx_lock; |
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unsigned int rx_buf_sz; /* Based on MTU+slack. */ |
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unsigned int speed; /* Operating speed */ |
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unsigned int vlan; /* VLAN Id */ |
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unsigned int chip_id; /* PCI table chip id */ |
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unsigned int rx_coalesce; /* Maximum frames each RxDMAComplete intr */ |
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unsigned int rx_timeout; /* Wait time between RxDMAComplete intr */ |
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unsigned int tx_coalesce; /* Maximum frames each tx interrupt */ |
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unsigned int full_duplex:1; /* Full-duplex operation requested. */ |
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unsigned int an_enable:2; /* Auto-Negotiated Enable */ |
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unsigned int jumbo:1; /* Jumbo frame enable */ |
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unsigned int coalesce:1; /* Rx coalescing enable */ |
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unsigned int tx_flow:1; /* Tx flow control enable */ |
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unsigned int rx_flow:1; /* Rx flow control enable */ |
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unsigned int phy_media:1; /* 1: fiber, 0: copper */ |
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unsigned int link_status:1; /* Current link status */ |
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struct netdev_desc *last_tx; /* Last Tx descriptor used. */ |
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unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */ |
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unsigned long cur_tx, old_tx; |
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struct timer_list timer; |
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int wake_polarity; |
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char name[256]; /* net device description */ |
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u8 duplex_polarity; |
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u16 mcast_filter[4]; |
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u16 advertising; /* NWay media advertisement */ |
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u16 negotiate; /* Negotiated media */ |
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int phy_addr; /* PHY addresses. */ |
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u16 led_mode; /* LED mode read from EEPROM (IP1000A only) */ |
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}; |
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/* The station address location in the EEPROM. */ |
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/* The struct pci_device_id consist of: |
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vendor, device Vendor and device ID to match (or PCI_ANY_ID) |
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subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID) |
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class Device class to match. The class_mask tells which bits |
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class_mask of the class are honored during the comparison. |
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driver_data Data private to the driver. |
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*/ |
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#define CHIP_IP1000A 1 |
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static const struct pci_device_id rio_pci_tbl[] = { |
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{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, }, |
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{0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, }, |
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{ PCI_VDEVICE(SUNDANCE, 0x1023), CHIP_IP1000A }, |
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{ PCI_VDEVICE(SUNDANCE, 0x2021), CHIP_IP1000A }, |
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{ PCI_VDEVICE(DLINK, 0x9021), CHIP_IP1000A }, |
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{ PCI_VDEVICE(DLINK, 0x4020), CHIP_IP1000A }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE (pci, rio_pci_tbl); |
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#define TX_TIMEOUT (4*HZ) |
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#define PACKET_SIZE 1536 |
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#define MAX_JUMBO 8000 |
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#define RIO_IO_SIZE 340 |
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#define DEFAULT_RXC 5 |
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#define DEFAULT_RXT 750 |
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#define DEFAULT_TXC 1 |
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#define MAX_TXC 8 |
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#endif /* __DL2K_H__ */
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