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348 lines
8.7 KiB
348 lines
8.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* cavium_ptp.c - PTP 1588 clock on Cavium hardware |
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* Copyright (c) 2003-2015, 2017 Cavium, Inc. |
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*/ |
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#include <linux/device.h> |
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#include <linux/module.h> |
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#include <linux/timecounter.h> |
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#include <linux/pci.h> |
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#include "cavium_ptp.h" |
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#define DRV_NAME "cavium_ptp" |
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#define PCI_DEVICE_ID_CAVIUM_PTP 0xA00C |
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#define PCI_SUBSYS_DEVID_88XX_PTP 0xA10C |
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#define PCI_SUBSYS_DEVID_81XX_PTP 0XA20C |
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#define PCI_SUBSYS_DEVID_83XX_PTP 0xA30C |
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#define PCI_DEVICE_ID_CAVIUM_RST 0xA00E |
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#define PCI_PTP_BAR_NO 0 |
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#define PCI_RST_BAR_NO 0 |
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#define PTP_CLOCK_CFG 0xF00ULL |
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#define PTP_CLOCK_CFG_PTP_EN BIT(0) |
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#define PTP_CLOCK_LO 0xF08ULL |
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#define PTP_CLOCK_HI 0xF10ULL |
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#define PTP_CLOCK_COMP 0xF18ULL |
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#define RST_BOOT 0x1600ULL |
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#define CLOCK_BASE_RATE 50000000ULL |
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static u64 ptp_cavium_clock_get(void) |
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{ |
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struct pci_dev *pdev; |
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void __iomem *base; |
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u64 ret = CLOCK_BASE_RATE * 16; |
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pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, |
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PCI_DEVICE_ID_CAVIUM_RST, NULL); |
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if (!pdev) |
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goto error; |
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base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO); |
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if (!base) |
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goto error_put_pdev; |
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ret = CLOCK_BASE_RATE * ((readq(base + RST_BOOT) >> 33) & 0x3f); |
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iounmap(base); |
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error_put_pdev: |
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pci_dev_put(pdev); |
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error: |
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return ret; |
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} |
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struct cavium_ptp *cavium_ptp_get(void) |
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{ |
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struct cavium_ptp *ptp; |
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struct pci_dev *pdev; |
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pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, |
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PCI_DEVICE_ID_CAVIUM_PTP, NULL); |
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if (!pdev) |
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return ERR_PTR(-ENODEV); |
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ptp = pci_get_drvdata(pdev); |
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if (!ptp) |
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ptp = ERR_PTR(-EPROBE_DEFER); |
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if (IS_ERR(ptp)) |
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pci_dev_put(pdev); |
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return ptp; |
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} |
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EXPORT_SYMBOL(cavium_ptp_get); |
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void cavium_ptp_put(struct cavium_ptp *ptp) |
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{ |
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if (!ptp) |
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return; |
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pci_dev_put(ptp->pdev); |
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} |
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EXPORT_SYMBOL(cavium_ptp_put); |
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/** |
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* cavium_ptp_adjfine() - Adjust ptp frequency |
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* @ptp_info: PTP clock info |
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* @scaled_ppm: how much to adjust by, in parts per million, but with a |
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* 16 bit binary fractional field |
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*/ |
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static int cavium_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) |
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{ |
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struct cavium_ptp *clock = |
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container_of(ptp_info, struct cavium_ptp, ptp_info); |
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unsigned long flags; |
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u64 comp; |
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u64 adj; |
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bool neg_adj = false; |
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if (scaled_ppm < 0) { |
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neg_adj = true; |
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scaled_ppm = -scaled_ppm; |
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} |
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/* The hardware adds the clock compensation value to the PTP clock |
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* on every coprocessor clock cycle. Typical convention is that it |
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* represent number of nanosecond betwen each cycle. In this |
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* convention compensation value is in 64 bit fixed-point |
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* representation where upper 32 bits are number of nanoseconds |
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* and lower is fractions of nanosecond. |
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* The scaled_ppm represent the ratio in "parts per bilion" by which the |
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* compensation value should be corrected. |
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* To calculate new compenstation value we use 64bit fixed point |
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* arithmetic on following formula |
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* comp = tbase + tbase * scaled_ppm / (1M * 2^16) |
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* where tbase is the basic compensation value calculated initialy |
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* in cavium_ptp_init() -> tbase = 1/Hz. Then we use endian |
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* independent structure definition to write data to PTP register. |
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*/ |
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comp = ((u64)1000000000ull << 32) / clock->clock_rate; |
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adj = comp * scaled_ppm; |
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adj >>= 16; |
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adj = div_u64(adj, 1000000ull); |
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comp = neg_adj ? comp - adj : comp + adj; |
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spin_lock_irqsave(&clock->spin_lock, flags); |
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writeq(comp, clock->reg_base + PTP_CLOCK_COMP); |
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spin_unlock_irqrestore(&clock->spin_lock, flags); |
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return 0; |
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} |
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/** |
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* cavium_ptp_adjtime() - Adjust ptp time |
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* @ptp_info: PTP clock info |
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* @delta: how much to adjust by, in nanosecs |
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*/ |
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static int cavium_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) |
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{ |
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struct cavium_ptp *clock = |
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container_of(ptp_info, struct cavium_ptp, ptp_info); |
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unsigned long flags; |
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spin_lock_irqsave(&clock->spin_lock, flags); |
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timecounter_adjtime(&clock->time_counter, delta); |
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spin_unlock_irqrestore(&clock->spin_lock, flags); |
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/* Sync, for network driver to get latest value */ |
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smp_mb(); |
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return 0; |
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} |
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/** |
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* cavium_ptp_gettime() - Get hardware clock time with adjustment |
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* @ptp_info: PTP clock info |
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* @ts: timespec |
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*/ |
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static int cavium_ptp_gettime(struct ptp_clock_info *ptp_info, |
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struct timespec64 *ts) |
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{ |
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struct cavium_ptp *clock = |
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container_of(ptp_info, struct cavium_ptp, ptp_info); |
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unsigned long flags; |
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u64 nsec; |
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spin_lock_irqsave(&clock->spin_lock, flags); |
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nsec = timecounter_read(&clock->time_counter); |
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spin_unlock_irqrestore(&clock->spin_lock, flags); |
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*ts = ns_to_timespec64(nsec); |
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return 0; |
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} |
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/** |
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* cavium_ptp_settime() - Set hardware clock time. Reset adjustment |
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* @ptp_info: PTP clock info |
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* @ts: timespec |
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*/ |
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static int cavium_ptp_settime(struct ptp_clock_info *ptp_info, |
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const struct timespec64 *ts) |
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{ |
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struct cavium_ptp *clock = |
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container_of(ptp_info, struct cavium_ptp, ptp_info); |
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unsigned long flags; |
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u64 nsec; |
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nsec = timespec64_to_ns(ts); |
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spin_lock_irqsave(&clock->spin_lock, flags); |
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timecounter_init(&clock->time_counter, &clock->cycle_counter, nsec); |
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spin_unlock_irqrestore(&clock->spin_lock, flags); |
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return 0; |
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} |
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/** |
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* cavium_ptp_enable() - Request to enable or disable an ancillary feature. |
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* @ptp_info: PTP clock info |
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* @rq: request |
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* @on: is it on |
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*/ |
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static int cavium_ptp_enable(struct ptp_clock_info *ptp_info, |
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struct ptp_clock_request *rq, int on) |
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{ |
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return -EOPNOTSUPP; |
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} |
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static u64 cavium_ptp_cc_read(const struct cyclecounter *cc) |
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{ |
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struct cavium_ptp *clock = |
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container_of(cc, struct cavium_ptp, cycle_counter); |
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return readq(clock->reg_base + PTP_CLOCK_HI); |
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} |
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static int cavium_ptp_probe(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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struct device *dev = &pdev->dev; |
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struct cavium_ptp *clock; |
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struct cyclecounter *cc; |
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u64 clock_cfg; |
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u64 clock_comp; |
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int err; |
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clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); |
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if (!clock) { |
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err = -ENOMEM; |
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goto error; |
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} |
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clock->pdev = pdev; |
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err = pcim_enable_device(pdev); |
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if (err) |
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goto error_free; |
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err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev)); |
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if (err) |
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goto error_free; |
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clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO]; |
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spin_lock_init(&clock->spin_lock); |
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cc = &clock->cycle_counter; |
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cc->read = cavium_ptp_cc_read; |
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cc->mask = CYCLECOUNTER_MASK(64); |
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cc->mult = 1; |
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cc->shift = 0; |
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timecounter_init(&clock->time_counter, &clock->cycle_counter, |
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ktime_to_ns(ktime_get_real())); |
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clock->clock_rate = ptp_cavium_clock_get(); |
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clock->ptp_info = (struct ptp_clock_info) { |
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.owner = THIS_MODULE, |
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.name = "ThunderX PTP", |
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.max_adj = 1000000000ull, |
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.n_ext_ts = 0, |
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.n_pins = 0, |
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.pps = 0, |
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.adjfine = cavium_ptp_adjfine, |
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.adjtime = cavium_ptp_adjtime, |
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.gettime64 = cavium_ptp_gettime, |
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.settime64 = cavium_ptp_settime, |
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.enable = cavium_ptp_enable, |
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}; |
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clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); |
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clock_cfg |= PTP_CLOCK_CFG_PTP_EN; |
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writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); |
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clock_comp = ((u64)1000000000ull << 32) / clock->clock_rate; |
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writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP); |
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clock->ptp_clock = ptp_clock_register(&clock->ptp_info, dev); |
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if (IS_ERR(clock->ptp_clock)) { |
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err = PTR_ERR(clock->ptp_clock); |
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goto error_stop; |
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} |
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pci_set_drvdata(pdev, clock); |
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return 0; |
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error_stop: |
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clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); |
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clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; |
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writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); |
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pcim_iounmap_regions(pdev, 1 << PCI_PTP_BAR_NO); |
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error_free: |
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devm_kfree(dev, clock); |
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error: |
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/* For `cavium_ptp_get()` we need to differentiate between the case |
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* when the core has not tried to probe this device and the case when |
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* the probe failed. In the later case we pretend that the |
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* initialization was successful and keep the error in |
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* `dev->driver_data`. |
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*/ |
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pci_set_drvdata(pdev, ERR_PTR(err)); |
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return 0; |
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} |
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static void cavium_ptp_remove(struct pci_dev *pdev) |
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{ |
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struct cavium_ptp *clock = pci_get_drvdata(pdev); |
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u64 clock_cfg; |
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if (IS_ERR_OR_NULL(clock)) |
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return; |
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ptp_clock_unregister(clock->ptp_clock); |
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clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); |
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clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; |
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writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); |
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} |
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static const struct pci_device_id cavium_ptp_id_table[] = { |
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP, |
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PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_88XX_PTP) }, |
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP, |
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PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_81XX_PTP) }, |
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP, |
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PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_83XX_PTP) }, |
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{ 0, } |
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}; |
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static struct pci_driver cavium_ptp_driver = { |
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.name = DRV_NAME, |
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.id_table = cavium_ptp_id_table, |
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.probe = cavium_ptp_probe, |
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.remove = cavium_ptp_remove, |
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}; |
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module_pci_driver(cavium_ptp_driver); |
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MODULE_DESCRIPTION(DRV_NAME); |
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MODULE_AUTHOR("Cavium Networks <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DEVICE_TABLE(pci, cavium_ptp_id_table);
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