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143 lines
4.4 KiB
143 lines
4.4 KiB
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ |
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/* Copyright(c) 2014 - 2020 Intel Corporation */ |
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#ifndef __ICP_QAT_HAL_H |
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#define __ICP_QAT_HAL_H |
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#include "icp_qat_fw_loader_handle.h" |
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enum hal_global_csr { |
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MISC_CONTROL = 0xA04, |
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ICP_RESET = 0xA0c, |
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ICP_GLOBAL_CLK_ENABLE = 0xA50 |
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}; |
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enum { |
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MISC_CONTROL_C4XXX = 0xAA0, |
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ICP_RESET_CPP0 = 0x938, |
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ICP_RESET_CPP1 = 0x93c, |
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ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964, |
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ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 |
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}; |
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enum hal_ae_csr { |
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USTORE_ADDRESS = 0x000, |
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USTORE_DATA_LOWER = 0x004, |
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USTORE_DATA_UPPER = 0x008, |
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ALU_OUT = 0x010, |
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CTX_ARB_CNTL = 0x014, |
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CTX_ENABLES = 0x018, |
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CC_ENABLE = 0x01c, |
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CSR_CTX_POINTER = 0x020, |
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CTX_STS_INDIRECT = 0x040, |
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ACTIVE_CTX_STATUS = 0x044, |
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CTX_SIG_EVENTS_INDIRECT = 0x048, |
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CTX_SIG_EVENTS_ACTIVE = 0x04c, |
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CTX_WAKEUP_EVENTS_INDIRECT = 0x050, |
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LM_ADDR_0_INDIRECT = 0x060, |
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LM_ADDR_1_INDIRECT = 0x068, |
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LM_ADDR_2_INDIRECT = 0x0cc, |
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LM_ADDR_3_INDIRECT = 0x0d4, |
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INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0, |
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INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8, |
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INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c, |
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INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114, |
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INDIRECT_T_INDEX = 0x0f8, |
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INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc, |
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FUTURE_COUNT_SIGNAL_INDIRECT = 0x078, |
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TIMESTAMP_LOW = 0x0c0, |
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TIMESTAMP_HIGH = 0x0c4, |
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PROFILE_COUNT = 0x144, |
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SIGNATURE_ENABLE = 0x150, |
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AE_MISC_CONTROL = 0x160, |
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LOCAL_CSR_STATUS = 0x180, |
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}; |
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enum fcu_csr { |
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FCU_CONTROL = 0x8c0, |
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FCU_STATUS = 0x8c4, |
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FCU_STATUS1 = 0x8c8, |
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FCU_DRAM_ADDR_LO = 0x8cc, |
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FCU_DRAM_ADDR_HI = 0x8d0, |
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FCU_RAMBASE_ADDR_HI = 0x8d4, |
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FCU_RAMBASE_ADDR_LO = 0x8d8 |
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}; |
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enum fcu_csr_4xxx { |
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FCU_CONTROL_4XXX = 0x1000, |
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FCU_STATUS_4XXX = 0x1004, |
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FCU_ME_BROADCAST_MASK_TYPE = 0x1008, |
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FCU_AE_LOADED_4XXX = 0x1010, |
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FCU_DRAM_ADDR_LO_4XXX = 0x1014, |
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FCU_DRAM_ADDR_HI_4XXX = 0x1018, |
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}; |
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enum fcu_cmd { |
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FCU_CTRL_CMD_NOOP = 0, |
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FCU_CTRL_CMD_AUTH = 1, |
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FCU_CTRL_CMD_LOAD = 2, |
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FCU_CTRL_CMD_START = 3 |
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}; |
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enum fcu_sts { |
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FCU_STS_NO_STS = 0, |
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FCU_STS_VERI_DONE = 1, |
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FCU_STS_LOAD_DONE = 2, |
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FCU_STS_VERI_FAIL = 3, |
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FCU_STS_LOAD_FAIL = 4, |
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FCU_STS_BUSY = 5 |
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}; |
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#define ALL_AE_MASK 0xFFFFFFFF |
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#define UA_ECS (0x1 << 31) |
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#define ACS_ABO_BITPOS 31 |
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#define ACS_ACNO 0x7 |
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#define CE_ENABLE_BITPOS 0x8 |
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#define CE_LMADDR_0_GLOBAL_BITPOS 16 |
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#define CE_LMADDR_1_GLOBAL_BITPOS 17 |
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#define CE_LMADDR_2_GLOBAL_BITPOS 22 |
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#define CE_LMADDR_3_GLOBAL_BITPOS 23 |
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#define CE_T_INDEX_GLOBAL_BITPOS 21 |
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#define CE_NN_MODE_BITPOS 20 |
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#define CE_REG_PAR_ERR_BITPOS 25 |
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#define CE_BREAKPOINT_BITPOS 27 |
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#define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29 |
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#define CE_INUSE_CONTEXTS_BITPOS 31 |
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#define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS) |
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#define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS) |
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#define XCWE_VOLUNTARY (0x1) |
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#define LCS_STATUS (0x1) |
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#define MMC_SHARE_CS_BITPOS 2 |
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#define WAKEUP_EVENT 0x10000 |
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#define FCU_CTRL_BROADCAST_POS 0x4 |
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#define FCU_CTRL_AE_POS 0x8 |
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#define FCU_AUTH_STS_MASK 0x7 |
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#define FCU_STS_DONE_POS 0x9 |
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#define FCU_STS_AUTHFWLD_POS 0X8 |
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#define FCU_LOADED_AE_POS 0x16 |
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#define FW_AUTH_WAIT_PERIOD 10 |
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#define FW_AUTH_MAX_RETRY 300 |
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#define ICP_QAT_AE_OFFSET 0x20000 |
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#define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000) |
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#define LOCAL_TO_XFER_REG_OFFSET 0x800 |
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#define ICP_QAT_EP_OFFSET 0x3a000 |
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#define ICP_QAT_EP_OFFSET_4XXX 0x200000 /* HI MMIO CSRs */ |
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#define ICP_QAT_AE_OFFSET_4XXX 0x600000 |
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#define ICP_QAT_CAP_OFFSET_4XXX 0x640000 |
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#define SET_CAP_CSR(handle, csr, val) \ |
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ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val) |
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#define GET_CAP_CSR(handle, csr) \ |
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ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr) |
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#define AE_CSR(handle, ae) \ |
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((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12)) |
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#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) |
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#define SET_AE_CSR(handle, ae, csr, val) \ |
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ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val) |
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#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) |
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#define AE_XFER(handle, ae) \ |
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((char __iomem *)(handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12)) |
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#define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \ |
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(((reg) & 0xff) << 2)) |
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#define SET_AE_XFER(handle, ae, reg, val) \ |
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ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val) |
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#define SRAM_WRITE(handle, addr, val) \ |
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ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val) |
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#endif
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