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524 lines
13 KiB
524 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// Copyright (C) 2000-2001 Deep Blue Solutions |
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// Copyright (C) 2002 Shane Nay ([email protected]) |
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// Copyright (C) 2006-2007 Pavel Pisa ([email protected]) |
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// Copyright (C) 2008 Juergen Beisert ([email protected]) |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/clockchips.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/sched_clock.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <soc/imx/timer.h> |
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/* |
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* There are 4 versions of the timer hardware on Freescale MXC hardware. |
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* - MX1/MXL |
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* - MX21, MX27. |
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* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) |
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* - MX6DL, MX6SX, MX6Q(rev1.1+) |
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*/ |
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/* defines common for all i.MX */ |
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#define MXC_TCTL 0x00 |
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#define MXC_TCTL_TEN (1 << 0) /* Enable module */ |
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#define MXC_TPRER 0x04 |
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/* MX1, MX21, MX27 */ |
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#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) |
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#define MX1_2_TCTL_IRQEN (1 << 4) |
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#define MX1_2_TCTL_FRR (1 << 8) |
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#define MX1_2_TCMP 0x08 |
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#define MX1_2_TCN 0x10 |
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#define MX1_2_TSTAT 0x14 |
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/* MX21, MX27 */ |
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#define MX2_TSTAT_CAPT (1 << 1) |
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#define MX2_TSTAT_COMP (1 << 0) |
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/* MX31, MX35, MX25, MX5, MX6 */ |
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#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ |
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#define V2_TCTL_CLK_IPG (1 << 6) |
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#define V2_TCTL_CLK_PER (2 << 6) |
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#define V2_TCTL_CLK_OSC_DIV8 (5 << 6) |
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#define V2_TCTL_FRR (1 << 9) |
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#define V2_TCTL_24MEN (1 << 10) |
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#define V2_TPRER_PRE24M 12 |
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#define V2_IR 0x0c |
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#define V2_TSTAT 0x08 |
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#define V2_TSTAT_OF1 (1 << 0) |
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#define V2_TCN 0x24 |
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#define V2_TCMP 0x10 |
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#define V2_TIMER_RATE_OSC_DIV8 3000000 |
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struct imx_timer { |
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enum imx_gpt_type type; |
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void __iomem *base; |
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int irq; |
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struct clk *clk_per; |
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struct clk *clk_ipg; |
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const struct imx_gpt_data *gpt; |
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struct clock_event_device ced; |
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}; |
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struct imx_gpt_data { |
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int reg_tstat; |
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int reg_tcn; |
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int reg_tcmp; |
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void (*gpt_setup_tctl)(struct imx_timer *imxtm); |
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void (*gpt_irq_enable)(struct imx_timer *imxtm); |
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void (*gpt_irq_disable)(struct imx_timer *imxtm); |
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void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); |
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int (*set_next_event)(unsigned long evt, |
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struct clock_event_device *ced); |
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}; |
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static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) |
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{ |
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return container_of(ced, struct imx_timer, ced); |
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} |
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static void imx1_gpt_irq_disable(struct imx_timer *imxtm) |
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{ |
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unsigned int tmp; |
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tmp = readl_relaxed(imxtm->base + MXC_TCTL); |
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writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); |
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} |
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#define imx21_gpt_irq_disable imx1_gpt_irq_disable |
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static void imx31_gpt_irq_disable(struct imx_timer *imxtm) |
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{ |
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writel_relaxed(0, imxtm->base + V2_IR); |
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} |
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#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable |
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static void imx1_gpt_irq_enable(struct imx_timer *imxtm) |
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{ |
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unsigned int tmp; |
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tmp = readl_relaxed(imxtm->base + MXC_TCTL); |
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writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); |
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} |
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#define imx21_gpt_irq_enable imx1_gpt_irq_enable |
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static void imx31_gpt_irq_enable(struct imx_timer *imxtm) |
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{ |
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writel_relaxed(1<<0, imxtm->base + V2_IR); |
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} |
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#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable |
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static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) |
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{ |
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writel_relaxed(0, imxtm->base + MX1_2_TSTAT); |
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} |
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static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) |
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{ |
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writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, |
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imxtm->base + MX1_2_TSTAT); |
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} |
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static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) |
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{ |
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writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); |
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} |
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#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge |
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static void __iomem *sched_clock_reg; |
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static u64 notrace mxc_read_sched_clock(void) |
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{ |
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return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; |
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} |
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#if defined(CONFIG_ARM) |
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static struct delay_timer imx_delay_timer; |
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static unsigned long imx_read_current_timer(void) |
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{ |
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return readl_relaxed(sched_clock_reg); |
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} |
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#endif |
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static int __init mxc_clocksource_init(struct imx_timer *imxtm) |
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{ |
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unsigned int c = clk_get_rate(imxtm->clk_per); |
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void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; |
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#if defined(CONFIG_ARM) |
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imx_delay_timer.read_current_timer = &imx_read_current_timer; |
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imx_delay_timer.freq = c; |
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register_current_timer_delay(&imx_delay_timer); |
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#endif |
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sched_clock_reg = reg; |
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sched_clock_register(mxc_read_sched_clock, 32, c); |
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return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, |
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clocksource_mmio_readl_up); |
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} |
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/* clock event */ |
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static int mx1_2_set_next_event(unsigned long evt, |
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struct clock_event_device *ced) |
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{ |
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struct imx_timer *imxtm = to_imx_timer(ced); |
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unsigned long tcmp; |
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tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; |
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writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); |
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return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? |
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-ETIME : 0; |
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} |
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static int v2_set_next_event(unsigned long evt, |
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struct clock_event_device *ced) |
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{ |
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struct imx_timer *imxtm = to_imx_timer(ced); |
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unsigned long tcmp; |
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tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; |
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writel_relaxed(tcmp, imxtm->base + V2_TCMP); |
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return evt < 0x7fffffff && |
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(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? |
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-ETIME : 0; |
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} |
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static int mxc_shutdown(struct clock_event_device *ced) |
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{ |
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struct imx_timer *imxtm = to_imx_timer(ced); |
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u32 tcn; |
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/* Disable interrupt in GPT module */ |
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imxtm->gpt->gpt_irq_disable(imxtm); |
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tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); |
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/* Set event time into far-far future */ |
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writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); |
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/* Clear pending interrupt */ |
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imxtm->gpt->gpt_irq_acknowledge(imxtm); |
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#ifdef DEBUG |
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printk(KERN_INFO "%s: changing mode\n", __func__); |
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#endif /* DEBUG */ |
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return 0; |
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} |
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static int mxc_set_oneshot(struct clock_event_device *ced) |
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{ |
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struct imx_timer *imxtm = to_imx_timer(ced); |
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/* Disable interrupt in GPT module */ |
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imxtm->gpt->gpt_irq_disable(imxtm); |
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if (!clockevent_state_oneshot(ced)) { |
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u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); |
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/* Set event time into far-far future */ |
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writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); |
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/* Clear pending interrupt */ |
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imxtm->gpt->gpt_irq_acknowledge(imxtm); |
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} |
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#ifdef DEBUG |
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printk(KERN_INFO "%s: changing mode\n", __func__); |
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#endif /* DEBUG */ |
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/* |
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* Do not put overhead of interrupt enable/disable into |
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* mxc_set_next_event(), the core has about 4 minutes |
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* to call mxc_set_next_event() or shutdown clock after |
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* mode switching |
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*/ |
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imxtm->gpt->gpt_irq_enable(imxtm); |
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return 0; |
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} |
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/* |
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* IRQ handler for the timer |
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*/ |
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *ced = dev_id; |
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struct imx_timer *imxtm = to_imx_timer(ced); |
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uint32_t tstat; |
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tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); |
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imxtm->gpt->gpt_irq_acknowledge(imxtm); |
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ced->event_handler(ced); |
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return IRQ_HANDLED; |
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} |
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static int __init mxc_clockevent_init(struct imx_timer *imxtm) |
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{ |
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struct clock_event_device *ced = &imxtm->ced; |
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ced->name = "mxc_timer1"; |
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ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; |
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ced->set_state_shutdown = mxc_shutdown; |
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ced->set_state_oneshot = mxc_set_oneshot; |
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ced->tick_resume = mxc_shutdown; |
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ced->set_next_event = imxtm->gpt->set_next_event; |
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ced->rating = 200; |
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ced->cpumask = cpumask_of(0); |
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ced->irq = imxtm->irq; |
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clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per), |
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0xff, 0xfffffffe); |
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return request_irq(imxtm->irq, mxc_timer_interrupt, |
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IRQF_TIMER | IRQF_IRQPOLL, "i.MX Timer Tick", ced); |
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} |
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static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) |
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{ |
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u32 tctl_val; |
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tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; |
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writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); |
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} |
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#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl |
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static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) |
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{ |
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u32 tctl_val; |
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tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; |
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if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) |
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tctl_val |= V2_TCTL_CLK_OSC_DIV8; |
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else |
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tctl_val |= V2_TCTL_CLK_PER; |
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writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); |
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} |
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static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) |
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{ |
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u32 tctl_val; |
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tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; |
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if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { |
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tctl_val |= V2_TCTL_CLK_OSC_DIV8; |
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/* 24 / 8 = 3 MHz */ |
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writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); |
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tctl_val |= V2_TCTL_24MEN; |
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} else { |
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tctl_val |= V2_TCTL_CLK_PER; |
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} |
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writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); |
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} |
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static const struct imx_gpt_data imx1_gpt_data = { |
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.reg_tstat = MX1_2_TSTAT, |
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.reg_tcn = MX1_2_TCN, |
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.reg_tcmp = MX1_2_TCMP, |
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.gpt_irq_enable = imx1_gpt_irq_enable, |
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.gpt_irq_disable = imx1_gpt_irq_disable, |
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.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, |
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.gpt_setup_tctl = imx1_gpt_setup_tctl, |
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.set_next_event = mx1_2_set_next_event, |
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}; |
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static const struct imx_gpt_data imx21_gpt_data = { |
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.reg_tstat = MX1_2_TSTAT, |
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.reg_tcn = MX1_2_TCN, |
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.reg_tcmp = MX1_2_TCMP, |
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.gpt_irq_enable = imx21_gpt_irq_enable, |
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.gpt_irq_disable = imx21_gpt_irq_disable, |
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.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, |
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.gpt_setup_tctl = imx21_gpt_setup_tctl, |
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.set_next_event = mx1_2_set_next_event, |
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}; |
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static const struct imx_gpt_data imx31_gpt_data = { |
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.reg_tstat = V2_TSTAT, |
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.reg_tcn = V2_TCN, |
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.reg_tcmp = V2_TCMP, |
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.gpt_irq_enable = imx31_gpt_irq_enable, |
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.gpt_irq_disable = imx31_gpt_irq_disable, |
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.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, |
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.gpt_setup_tctl = imx31_gpt_setup_tctl, |
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.set_next_event = v2_set_next_event, |
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}; |
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static const struct imx_gpt_data imx6dl_gpt_data = { |
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.reg_tstat = V2_TSTAT, |
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.reg_tcn = V2_TCN, |
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.reg_tcmp = V2_TCMP, |
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.gpt_irq_enable = imx6dl_gpt_irq_enable, |
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.gpt_irq_disable = imx6dl_gpt_irq_disable, |
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.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, |
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.gpt_setup_tctl = imx6dl_gpt_setup_tctl, |
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.set_next_event = v2_set_next_event, |
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}; |
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static int __init _mxc_timer_init(struct imx_timer *imxtm) |
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{ |
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int ret; |
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switch (imxtm->type) { |
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case GPT_TYPE_IMX1: |
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imxtm->gpt = &imx1_gpt_data; |
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break; |
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case GPT_TYPE_IMX21: |
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imxtm->gpt = &imx21_gpt_data; |
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break; |
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case GPT_TYPE_IMX31: |
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imxtm->gpt = &imx31_gpt_data; |
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break; |
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case GPT_TYPE_IMX6DL: |
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imxtm->gpt = &imx6dl_gpt_data; |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (IS_ERR(imxtm->clk_per)) { |
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pr_err("i.MX timer: unable to get clk\n"); |
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return PTR_ERR(imxtm->clk_per); |
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} |
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if (!IS_ERR(imxtm->clk_ipg)) |
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clk_prepare_enable(imxtm->clk_ipg); |
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clk_prepare_enable(imxtm->clk_per); |
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/* |
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* Initialise to a known state (all timers off, and timing reset) |
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*/ |
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writel_relaxed(0, imxtm->base + MXC_TCTL); |
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writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ |
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imxtm->gpt->gpt_setup_tctl(imxtm); |
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/* init and register the timer to the framework */ |
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ret = mxc_clocksource_init(imxtm); |
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if (ret) |
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return ret; |
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return mxc_clockevent_init(imxtm); |
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} |
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void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) |
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{ |
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struct imx_timer *imxtm; |
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imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); |
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BUG_ON(!imxtm); |
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imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); |
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imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); |
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imxtm->base = ioremap(pbase, SZ_4K); |
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BUG_ON(!imxtm->base); |
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imxtm->type = type; |
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imxtm->irq = irq; |
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_mxc_timer_init(imxtm); |
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} |
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static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) |
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{ |
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struct imx_timer *imxtm; |
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static int initialized; |
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int ret; |
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/* Support one instance only */ |
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if (initialized) |
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return 0; |
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imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); |
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if (!imxtm) |
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return -ENOMEM; |
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imxtm->base = of_iomap(np, 0); |
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if (!imxtm->base) |
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return -ENXIO; |
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imxtm->irq = irq_of_parse_and_map(np, 0); |
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if (imxtm->irq <= 0) |
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return -EINVAL; |
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imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); |
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/* Try osc_per first, and fall back to per otherwise */ |
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imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); |
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if (IS_ERR(imxtm->clk_per)) |
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imxtm->clk_per = of_clk_get_by_name(np, "per"); |
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imxtm->type = type; |
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ret = _mxc_timer_init(imxtm); |
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if (ret) |
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return ret; |
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initialized = 1; |
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return 0; |
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} |
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static int __init imx1_timer_init_dt(struct device_node *np) |
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{ |
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return mxc_timer_init_dt(np, GPT_TYPE_IMX1); |
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} |
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static int __init imx21_timer_init_dt(struct device_node *np) |
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{ |
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return mxc_timer_init_dt(np, GPT_TYPE_IMX21); |
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} |
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static int __init imx31_timer_init_dt(struct device_node *np) |
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{ |
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enum imx_gpt_type type = GPT_TYPE_IMX31; |
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/* |
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* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S |
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* GPT device, while they actually have different programming model. |
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* This is a workaround to keep the existing i.MX6DL/S DTBs continue |
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* working with the new kernel. |
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*/ |
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if (of_machine_is_compatible("fsl,imx6dl")) |
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type = GPT_TYPE_IMX6DL; |
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return mxc_timer_init_dt(np, type); |
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} |
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static int __init imx6dl_timer_init_dt(struct device_node *np) |
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{ |
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return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); |
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} |
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TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); |
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TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); |
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TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt); |
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TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); |
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TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); |
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TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); |
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TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); |
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TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); |
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TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); |
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TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); |
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TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); |
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TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
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