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70 lines
2.5 KiB
70 lines
2.5 KiB
/* |
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* This header file contains assembly-language definitions (assembly |
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* macros, etc.) for this specific Xtensa processor's TIE extensions |
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* and options. It is customized to this Xtensa processor configuration. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1999-2008 Tensilica Inc. |
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*/ |
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#ifndef _XTENSA_CORE_TIE_ASM_H |
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#define _XTENSA_CORE_TIE_ASM_H |
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/* Selection parameter values for save-area save/restore macros: */ |
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/* Option vs. TIE: */ |
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ |
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ |
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/* Whether used automatically by compiler: */ |
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ |
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ |
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/* ABI handling across function calls: */ |
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ |
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ |
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ |
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/* Misc */ |
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ |
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state |
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* (not including zero-overhead loop registers). |
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* Save area ptr (clobbered): ptr (1 byte aligned) |
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) |
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*/ |
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL |
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xchal_sa_start \continue, \ofs |
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select |
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xchal_sa_align \ptr, 0, 1024-4, 4, 4 |
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rur \at1, THREADPTR // threadptr option |
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s32i \at1, \ptr, .Lxchal_ofs_ + 0 |
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 |
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.endif |
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.endm // xchal_ncp_store |
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state |
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* (not including zero-overhead loop registers). |
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* Save area ptr (clobbered): ptr (1 byte aligned) |
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) |
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*/ |
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL |
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xchal_sa_start \continue, \ofs |
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select |
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xchal_sa_align \ptr, 0, 1024-4, 4, 4 |
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l32i \at1, \ptr, .Lxchal_ofs_ + 0 |
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wur \at1, THREADPTR // threadptr option |
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 |
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.endif |
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.endm // xchal_ncp_load |
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#define XCHAL_NCP_NUM_ATMPS 1 |
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#define XCHAL_SA_NUM_ATMPS 1 |
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#endif /*_XTENSA_CORE_TIE_ASM_H*/ |
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