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462 lines
11 KiB
462 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/io.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/spi_bitbang.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/platform_data/efm32-spi.h> |
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#include <linux/of.h> |
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#define DRIVER_NAME "efm32-spi" |
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#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) |
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#define REG_CTRL 0x00 |
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#define REG_CTRL_SYNC 0x0001 |
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#define REG_CTRL_CLKPOL 0x0100 |
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#define REG_CTRL_CLKPHA 0x0200 |
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#define REG_CTRL_MSBF 0x0400 |
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#define REG_CTRL_TXBIL 0x1000 |
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#define REG_FRAME 0x04 |
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#define REG_FRAME_DATABITS__MASK 0x000f |
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#define REG_FRAME_DATABITS(n) ((n) - 3) |
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#define REG_CMD 0x0c |
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#define REG_CMD_RXEN 0x0001 |
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#define REG_CMD_RXDIS 0x0002 |
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#define REG_CMD_TXEN 0x0004 |
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#define REG_CMD_TXDIS 0x0008 |
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#define REG_CMD_MASTEREN 0x0010 |
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#define REG_STATUS 0x10 |
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#define REG_STATUS_TXENS 0x0002 |
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#define REG_STATUS_TXC 0x0020 |
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#define REG_STATUS_TXBL 0x0040 |
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#define REG_STATUS_RXDATAV 0x0080 |
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#define REG_CLKDIV 0x14 |
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#define REG_RXDATAX 0x18 |
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#define REG_RXDATAX_RXDATA__MASK 0x01ff |
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#define REG_RXDATAX_PERR 0x4000 |
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#define REG_RXDATAX_FERR 0x8000 |
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#define REG_TXDATA 0x34 |
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#define REG_IF 0x40 |
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#define REG_IF_TXBL 0x0002 |
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#define REG_IF_RXDATAV 0x0004 |
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#define REG_IFS 0x44 |
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#define REG_IFC 0x48 |
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#define REG_IEN 0x4c |
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#define REG_ROUTE 0x54 |
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#define REG_ROUTE_RXPEN 0x0001 |
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#define REG_ROUTE_TXPEN 0x0002 |
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#define REG_ROUTE_CLKPEN 0x0008 |
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#define REG_ROUTE_LOCATION__MASK 0x0700 |
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#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n)) |
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struct efm32_spi_ddata { |
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struct spi_bitbang bitbang; |
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spinlock_t lock; |
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struct clk *clk; |
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void __iomem *base; |
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unsigned int rxirq, txirq; |
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struct efm32_spi_pdata pdata; |
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/* irq data */ |
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struct completion done; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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unsigned tx_len, rx_len; |
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}; |
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#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev)) |
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#define efm32_spi_vdbg(ddata, format, arg...) \ |
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dev_vdbg(ddata_to_dev(ddata), format, ##arg) |
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static void efm32_spi_write32(struct efm32_spi_ddata *ddata, |
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u32 value, unsigned offset) |
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{ |
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writel_relaxed(value, ddata->base + offset); |
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} |
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static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset) |
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{ |
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return readl_relaxed(ddata->base + offset); |
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} |
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static int efm32_spi_setup_transfer(struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); |
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unsigned bpw = t->bits_per_word ?: spi->bits_per_word; |
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unsigned speed = t->speed_hz ?: spi->max_speed_hz; |
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unsigned long clkfreq = clk_get_rate(ddata->clk); |
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u32 clkdiv; |
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efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF | |
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(spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) | |
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(spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL); |
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efm32_spi_write32(ddata, |
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REG_FRAME_DATABITS(bpw), REG_FRAME); |
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if (2 * speed >= clkfreq) |
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clkdiv = 0; |
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else |
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clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4); |
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if (clkdiv > (1U << 21)) |
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return -EINVAL; |
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efm32_spi_write32(ddata, clkdiv, REG_CLKDIV); |
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efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD); |
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efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD); |
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return 0; |
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} |
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static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata) |
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{ |
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u8 val = 0; |
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if (ddata->tx_buf) { |
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val = *ddata->tx_buf; |
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ddata->tx_buf++; |
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} |
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ddata->tx_len--; |
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efm32_spi_write32(ddata, val, REG_TXDATA); |
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efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val); |
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} |
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static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata) |
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{ |
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u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX); |
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efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata); |
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if (ddata->rx_buf) { |
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*ddata->rx_buf = rxdata; |
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ddata->rx_buf++; |
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} |
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ddata->rx_len--; |
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} |
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static void efm32_spi_filltx(struct efm32_spi_ddata *ddata) |
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{ |
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while (ddata->tx_len && |
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ddata->tx_len + 2 > ddata->rx_len && |
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efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) { |
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efm32_spi_tx_u8(ddata); |
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} |
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} |
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static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
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{ |
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struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); |
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int ret = -EBUSY; |
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spin_lock_irq(&ddata->lock); |
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if (ddata->tx_buf || ddata->rx_buf) |
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goto out_unlock; |
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ddata->tx_buf = t->tx_buf; |
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ddata->rx_buf = t->rx_buf; |
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ddata->tx_len = ddata->rx_len = |
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t->len * DIV_ROUND_UP(t->bits_per_word, 8); |
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efm32_spi_filltx(ddata); |
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reinit_completion(&ddata->done); |
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efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN); |
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spin_unlock_irq(&ddata->lock); |
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wait_for_completion(&ddata->done); |
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spin_lock_irq(&ddata->lock); |
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ret = t->len - max(ddata->tx_len, ddata->rx_len); |
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efm32_spi_write32(ddata, 0, REG_IEN); |
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ddata->tx_buf = ddata->rx_buf = NULL; |
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out_unlock: |
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spin_unlock_irq(&ddata->lock); |
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return ret; |
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} |
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static irqreturn_t efm32_spi_rxirq(int irq, void *data) |
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{ |
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struct efm32_spi_ddata *ddata = data; |
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irqreturn_t ret = IRQ_NONE; |
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spin_lock(&ddata->lock); |
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while (ddata->rx_len > 0 && |
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efm32_spi_read32(ddata, REG_STATUS) & |
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REG_STATUS_RXDATAV) { |
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efm32_spi_rx_u8(ddata); |
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ret = IRQ_HANDLED; |
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} |
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if (!ddata->rx_len) { |
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u32 ien = efm32_spi_read32(ddata, REG_IEN); |
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ien &= ~REG_IF_RXDATAV; |
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efm32_spi_write32(ddata, ien, REG_IEN); |
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complete(&ddata->done); |
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} |
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spin_unlock(&ddata->lock); |
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return ret; |
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} |
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static irqreturn_t efm32_spi_txirq(int irq, void *data) |
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{ |
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struct efm32_spi_ddata *ddata = data; |
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efm32_spi_vdbg(ddata, |
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"%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n", |
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__func__, ddata->tx_len, ddata->rx_len, |
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efm32_spi_read32(ddata, REG_IF), |
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efm32_spi_read32(ddata, REG_STATUS)); |
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spin_lock(&ddata->lock); |
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efm32_spi_filltx(ddata); |
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efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n", |
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__func__, ddata->tx_len, ddata->rx_len); |
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if (!ddata->tx_len) { |
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u32 ien = efm32_spi_read32(ddata, REG_IEN); |
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ien &= ~REG_IF_TXBL; |
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efm32_spi_write32(ddata, ien, REG_IEN); |
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efm32_spi_vdbg(ddata, "disable TXBL\n"); |
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} |
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spin_unlock(&ddata->lock); |
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return IRQ_HANDLED; |
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} |
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static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata) |
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{ |
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u32 reg = efm32_spi_read32(ddata, REG_ROUTE); |
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return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK); |
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} |
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static void efm32_spi_probe_dt(struct platform_device *pdev, |
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struct spi_master *master, struct efm32_spi_ddata *ddata) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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u32 location; |
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int ret; |
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ret = of_property_read_u32(np, "energymicro,location", &location); |
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if (ret) |
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/* fall back to wrongly namespaced property */ |
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ret = of_property_read_u32(np, "efm32,location", &location); |
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if (ret) |
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/* fall back to old and (wrongly) generic property "location" */ |
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ret = of_property_read_u32(np, "location", &location); |
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if (!ret) { |
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dev_dbg(&pdev->dev, "using location %u\n", location); |
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} else { |
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/* default to location configured in hardware */ |
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location = efm32_spi_get_configured_location(ddata); |
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dev_info(&pdev->dev, "fall back to location %u\n", location); |
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} |
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ddata->pdata.location = location; |
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} |
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static int efm32_spi_probe(struct platform_device *pdev) |
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{ |
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struct efm32_spi_ddata *ddata; |
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struct resource *res; |
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int ret; |
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struct spi_master *master; |
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struct device_node *np = pdev->dev.of_node; |
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if (!np) |
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return -EINVAL; |
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master = spi_alloc_master(&pdev->dev, sizeof(*ddata)); |
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if (!master) { |
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dev_dbg(&pdev->dev, |
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"failed to allocate spi master controller\n"); |
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return -ENOMEM; |
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} |
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platform_set_drvdata(pdev, master); |
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master->dev.of_node = pdev->dev.of_node; |
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
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master->use_gpio_descriptors = true; |
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ddata = spi_master_get_devdata(master); |
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ddata->bitbang.master = master; |
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ddata->bitbang.setup_transfer = efm32_spi_setup_transfer; |
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ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs; |
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spin_lock_init(&ddata->lock); |
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init_completion(&ddata->done); |
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ddata->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(ddata->clk)) { |
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ret = PTR_ERR(ddata->clk); |
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dev_err(&pdev->dev, "failed to get clock: %d\n", ret); |
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goto err; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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ret = -ENODEV; |
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dev_err(&pdev->dev, "failed to determine base address\n"); |
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goto err; |
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} |
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if (resource_size(res) < 0x60) { |
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ret = -EINVAL; |
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dev_err(&pdev->dev, "memory resource too small\n"); |
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goto err; |
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} |
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ddata->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(ddata->base)) { |
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ret = PTR_ERR(ddata->base); |
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goto err; |
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} |
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ret = platform_get_irq(pdev, 0); |
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if (ret <= 0) |
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goto err; |
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ddata->rxirq = ret; |
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ret = platform_get_irq(pdev, 1); |
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if (ret <= 0) |
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ret = ddata->rxirq + 1; |
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ddata->txirq = ret; |
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ret = clk_prepare_enable(ddata->clk); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret); |
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goto err; |
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} |
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efm32_spi_probe_dt(pdev, master, ddata); |
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efm32_spi_write32(ddata, 0, REG_IEN); |
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efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN | |
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REG_ROUTE_CLKPEN | |
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REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE); |
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ret = request_irq(ddata->rxirq, efm32_spi_rxirq, |
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0, DRIVER_NAME " rx", ddata); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret); |
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goto err_disable_clk; |
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} |
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ret = request_irq(ddata->txirq, efm32_spi_txirq, |
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0, DRIVER_NAME " tx", ddata); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret); |
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goto err_free_rx_irq; |
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} |
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ret = spi_bitbang_start(&ddata->bitbang); |
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if (ret) { |
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dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret); |
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free_irq(ddata->txirq, ddata); |
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err_free_rx_irq: |
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free_irq(ddata->rxirq, ddata); |
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err_disable_clk: |
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clk_disable_unprepare(ddata->clk); |
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err: |
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spi_master_put(master); |
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} |
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return ret; |
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} |
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static int efm32_spi_remove(struct platform_device *pdev) |
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{ |
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struct spi_master *master = platform_get_drvdata(pdev); |
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struct efm32_spi_ddata *ddata = spi_master_get_devdata(master); |
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spi_bitbang_stop(&ddata->bitbang); |
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efm32_spi_write32(ddata, 0, REG_IEN); |
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free_irq(ddata->txirq, ddata); |
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free_irq(ddata->rxirq, ddata); |
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clk_disable_unprepare(ddata->clk); |
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spi_master_put(master); |
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return 0; |
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} |
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static const struct of_device_id efm32_spi_dt_ids[] = { |
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{ |
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.compatible = "energymicro,efm32-spi", |
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}, { |
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/* doesn't follow the "vendor,device" scheme, don't use */ |
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.compatible = "efm32,spi", |
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}, { |
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/* sentinel */ |
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} |
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}; |
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MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids); |
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static struct platform_driver efm32_spi_driver = { |
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.probe = efm32_spi_probe, |
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.remove = efm32_spi_remove, |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = efm32_spi_dt_ids, |
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}, |
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}; |
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module_platform_driver(efm32_spi_driver); |
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MODULE_AUTHOR("Uwe Kleine-Koenig <[email protected]>"); |
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MODULE_DESCRIPTION("EFM32 SPI driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_ALIAS("platform:" DRIVER_NAME);
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