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159 lines
5.9 KiB
159 lines
5.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2014 STMicroelectronics (R&D) Limited |
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* Author: Giuseppe Cavallaro <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/reset/stih407-resets.h> |
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#include "reset-syscfg.h" |
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/* STiH407 Peripheral powerdown definitions. */ |
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static const char stih407_core[] = "st,stih407-core-syscfg"; |
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static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg"; |
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static const char stih407_lpm[] = "st,stih407-lpm-syscfg"; |
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#define STIH407_PDN_0(_bit) \ |
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) |
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#define STIH407_PDN_1(_bit) \ |
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) |
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#define STIH407_PDN_ETH(_bit, _stat) \ |
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_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) |
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/* Powerdown requests control 0 */ |
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#define SYSCFG_5000 0x0 |
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#define SYSSTAT_5500 0x7d0 |
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/* Powerdown requests control 1 (High Speed Links) */ |
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#define SYSCFG_5001 0x4 |
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#define SYSSTAT_5501 0x7d4 |
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/* Ethernet powerdown/status/reset */ |
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#define SYSCFG_4032 0x80 |
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#define SYSSTAT_4520 0x820 |
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#define SYSCFG_4002 0x8 |
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static const struct syscfg_reset_channel_data stih407_powerdowns[] = { |
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[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), |
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[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), |
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[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), |
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[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5), |
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[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4), |
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[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3), |
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[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2), |
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[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1), |
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[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0), |
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[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2), |
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}; |
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/* Reset Generator control 0/1 */ |
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#define SYSCFG_5128 0x200 |
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#define SYSCFG_5131 0x20c |
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#define SYSCFG_5132 0x210 |
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#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ |
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#define STIH407_SRST_CORE(_reg, _bit) \ |
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_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) |
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#define STIH407_SRST_SBC(_reg, _bit) \ |
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_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) |
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#define STIH407_SRST_LPM(_reg, _bit) \ |
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_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) |
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static const struct syscfg_reset_channel_data stih407_softresets[] = { |
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[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), |
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[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), |
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[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), |
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[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29), |
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[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30), |
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[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6), |
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[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6), |
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[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15), |
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[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7), |
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[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16), |
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[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4), |
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[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13), |
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[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22), |
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[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5), |
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[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14), |
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[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3), |
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[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10), |
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[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11), |
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[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12), |
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[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14), |
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[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15), |
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[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21), |
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[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23), |
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[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24), |
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[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30), |
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[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0), |
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[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1), |
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[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2), |
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[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8), |
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[STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26), |
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[STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27), |
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[STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28), |
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[STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2), |
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}; |
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/* PicoPHY reset/control */ |
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#define SYSCFG_5061 0x0f4 |
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static const struct syscfg_reset_channel_data stih407_picophyresets[] = { |
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[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), |
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[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), |
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[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), |
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}; |
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static const struct syscfg_reset_controller_data stih407_powerdown_controller = { |
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.wait_for_ack = true, |
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.nr_channels = ARRAY_SIZE(stih407_powerdowns), |
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.channels = stih407_powerdowns, |
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}; |
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static const struct syscfg_reset_controller_data stih407_softreset_controller = { |
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.wait_for_ack = false, |
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.active_low = true, |
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.nr_channels = ARRAY_SIZE(stih407_softresets), |
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.channels = stih407_softresets, |
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}; |
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static const struct syscfg_reset_controller_data stih407_picophyreset_controller = { |
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.wait_for_ack = false, |
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.nr_channels = ARRAY_SIZE(stih407_picophyresets), |
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.channels = stih407_picophyresets, |
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}; |
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static const struct of_device_id stih407_reset_match[] = { |
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{ |
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.compatible = "st,stih407-powerdown", |
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.data = &stih407_powerdown_controller, |
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}, |
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{ |
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.compatible = "st,stih407-softreset", |
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.data = &stih407_softreset_controller, |
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}, |
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{ |
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.compatible = "st,stih407-picophyreset", |
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.data = &stih407_picophyreset_controller, |
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}, |
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{ /* sentinel */ }, |
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}; |
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static struct platform_driver stih407_reset_driver = { |
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.probe = syscfg_reset_probe, |
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.driver = { |
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.name = "reset-stih407", |
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.of_match_table = stih407_reset_match, |
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}, |
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}; |
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static int __init stih407_reset_init(void) |
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{ |
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return platform_driver_register(&stih407_reset_driver); |
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} |
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arch_initcall(stih407_reset_init);
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