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425 lines
10 KiB
425 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* AMD HSMP Platform Driver |
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* Copyright (c) 2022, AMD. |
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* All Rights Reserved. |
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* |
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* This file provides a device implementation for HSMP interface |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <asm/amd_hsmp.h> |
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#include <asm/amd_nb.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/miscdevice.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/semaphore.h> |
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#define DRIVER_NAME "amd_hsmp" |
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#define DRIVER_VERSION "1.0" |
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/* HSMP Status / Error codes */ |
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#define HSMP_STATUS_NOT_READY 0x00 |
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#define HSMP_STATUS_OK 0x01 |
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#define HSMP_ERR_INVALID_MSG 0xFE |
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#define HSMP_ERR_INVALID_INPUT 0xFF |
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/* Timeout in millsec */ |
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#define HSMP_MSG_TIMEOUT 100 |
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#define HSMP_SHORT_SLEEP 1 |
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#define HSMP_WR true |
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#define HSMP_RD false |
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/* |
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* To access specific HSMP mailbox register, s/w writes the SMN address of HSMP mailbox |
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* register into the SMN_INDEX register, and reads/writes the SMN_DATA reg. |
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* Below are required SMN address for HSMP Mailbox register offsets in SMU address space |
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*/ |
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#define SMN_HSMP_MSG_ID 0x3B10534 |
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#define SMN_HSMP_MSG_RESP 0x3B10980 |
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#define SMN_HSMP_MSG_DATA 0x3B109E0 |
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#define HSMP_INDEX_REG 0xc4 |
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#define HSMP_DATA_REG 0xc8 |
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static struct semaphore *hsmp_sem; |
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static struct miscdevice hsmp_device; |
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static int amd_hsmp_rdwr(struct pci_dev *root, u32 address, |
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u32 *value, bool write) |
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{ |
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int ret; |
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ret = pci_write_config_dword(root, HSMP_INDEX_REG, address); |
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if (ret) |
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return ret; |
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ret = (write ? pci_write_config_dword(root, HSMP_DATA_REG, *value) |
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: pci_read_config_dword(root, HSMP_DATA_REG, value)); |
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return ret; |
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} |
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/* |
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* Send a message to the HSMP port via PCI-e config space registers. |
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* |
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* The caller is expected to zero out any unused arguments. |
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* If a response is expected, the number of response words should be greater than 0. |
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* |
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* Returns 0 for success and populates the requested number of arguments. |
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* Returns a negative error code for failure. |
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*/ |
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static int __hsmp_send_message(struct pci_dev *root, struct hsmp_message *msg) |
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{ |
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unsigned long timeout, short_sleep; |
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u32 mbox_status; |
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u32 index; |
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int ret; |
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/* Clear the status register */ |
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mbox_status = HSMP_STATUS_NOT_READY; |
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ret = amd_hsmp_rdwr(root, SMN_HSMP_MSG_RESP, &mbox_status, HSMP_WR); |
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if (ret) { |
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pr_err("Error %d clearing mailbox status register\n", ret); |
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return ret; |
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} |
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index = 0; |
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/* Write any message arguments */ |
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while (index < msg->num_args) { |
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ret = amd_hsmp_rdwr(root, SMN_HSMP_MSG_DATA + (index << 2), |
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&msg->args[index], HSMP_WR); |
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if (ret) { |
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pr_err("Error %d writing message argument %d\n", ret, index); |
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return ret; |
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} |
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index++; |
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} |
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/* Write the message ID which starts the operation */ |
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ret = amd_hsmp_rdwr(root, SMN_HSMP_MSG_ID, &msg->msg_id, HSMP_WR); |
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if (ret) { |
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pr_err("Error %d writing message ID %u\n", ret, msg->msg_id); |
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return ret; |
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} |
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/* |
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* Depending on when the trigger write completes relative to the SMU |
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* firmware 1 ms cycle, the operation may take from tens of us to 1 ms |
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* to complete. Some operations may take more. Therefore we will try |
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* a few short duration sleeps and switch to long sleeps if we don't |
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* succeed quickly. |
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*/ |
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short_sleep = jiffies + msecs_to_jiffies(HSMP_SHORT_SLEEP); |
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timeout = jiffies + msecs_to_jiffies(HSMP_MSG_TIMEOUT); |
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while (time_before(jiffies, timeout)) { |
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ret = amd_hsmp_rdwr(root, SMN_HSMP_MSG_RESP, &mbox_status, HSMP_RD); |
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if (ret) { |
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pr_err("Error %d reading mailbox status\n", ret); |
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return ret; |
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} |
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if (mbox_status != HSMP_STATUS_NOT_READY) |
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break; |
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if (time_before(jiffies, short_sleep)) |
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usleep_range(50, 100); |
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else |
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usleep_range(1000, 2000); |
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} |
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if (unlikely(mbox_status == HSMP_STATUS_NOT_READY)) { |
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return -ETIMEDOUT; |
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} else if (unlikely(mbox_status == HSMP_ERR_INVALID_MSG)) { |
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return -ENOMSG; |
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} else if (unlikely(mbox_status == HSMP_ERR_INVALID_INPUT)) { |
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return -EINVAL; |
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} else if (unlikely(mbox_status != HSMP_STATUS_OK)) { |
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pr_err("Message ID %u unknown failure (status = 0x%X)\n", |
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msg->msg_id, mbox_status); |
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return -EIO; |
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} |
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/* |
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* SMU has responded OK. Read response data. |
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* SMU reads the input arguments from eight 32 bit registers starting |
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* from SMN_HSMP_MSG_DATA and writes the response data to the same |
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* SMN_HSMP_MSG_DATA address. |
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* We copy the response data if any, back to the args[]. |
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*/ |
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index = 0; |
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while (index < msg->response_sz) { |
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ret = amd_hsmp_rdwr(root, SMN_HSMP_MSG_DATA + (index << 2), |
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&msg->args[index], HSMP_RD); |
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if (ret) { |
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pr_err("Error %d reading response %u for message ID:%u\n", |
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ret, index, msg->msg_id); |
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break; |
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} |
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index++; |
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} |
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return ret; |
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} |
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static int validate_message(struct hsmp_message *msg) |
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{ |
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/* msg_id against valid range of message IDs */ |
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if (msg->msg_id < HSMP_TEST || msg->msg_id >= HSMP_MSG_ID_MAX) |
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return -ENOMSG; |
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/* msg_id is a reserved message ID */ |
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if (hsmp_msg_desc_table[msg->msg_id].type == HSMP_RSVD) |
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return -ENOMSG; |
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/* num_args and response_sz against the HSMP spec */ |
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if (msg->num_args != hsmp_msg_desc_table[msg->msg_id].num_args || |
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msg->response_sz != hsmp_msg_desc_table[msg->msg_id].response_sz) |
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return -EINVAL; |
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return 0; |
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} |
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int hsmp_send_message(struct hsmp_message *msg) |
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{ |
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struct amd_northbridge *nb; |
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int ret; |
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if (!msg) |
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return -EINVAL; |
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nb = node_to_amd_nb(msg->sock_ind); |
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if (!nb || !nb->root) |
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return -ENODEV; |
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ret = validate_message(msg); |
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if (ret) |
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return ret; |
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/* |
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* The time taken by smu operation to complete is between |
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* 10us to 1ms. Sometime it may take more time. |
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* In SMP system timeout of 100 millisecs should |
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* be enough for the previous thread to finish the operation |
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*/ |
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ret = down_timeout(&hsmp_sem[msg->sock_ind], |
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msecs_to_jiffies(HSMP_MSG_TIMEOUT)); |
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if (ret < 0) |
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return ret; |
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ret = __hsmp_send_message(nb->root, msg); |
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up(&hsmp_sem[msg->sock_ind]); |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(hsmp_send_message); |
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static int hsmp_test(u16 sock_ind, u32 value) |
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{ |
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struct hsmp_message msg = { 0 }; |
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struct amd_northbridge *nb; |
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int ret = -ENODEV; |
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nb = node_to_amd_nb(sock_ind); |
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if (!nb || !nb->root) |
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return ret; |
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/* |
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* Test the hsmp port by performing TEST command. The test message |
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* takes one argument and returns the value of that argument + 1. |
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*/ |
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msg.msg_id = HSMP_TEST; |
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msg.num_args = 1; |
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msg.response_sz = 1; |
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msg.args[0] = value; |
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msg.sock_ind = sock_ind; |
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ret = __hsmp_send_message(nb->root, &msg); |
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if (ret) |
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return ret; |
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/* Check the response value */ |
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if (msg.args[0] != (value + 1)) { |
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pr_err("Socket %d test message failed, Expected 0x%08X, received 0x%08X\n", |
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sock_ind, (value + 1), msg.args[0]); |
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return -EBADE; |
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} |
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return ret; |
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} |
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static long hsmp_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) |
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{ |
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int __user *arguser = (int __user *)arg; |
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struct hsmp_message msg = { 0 }; |
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int ret; |
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if (copy_struct_from_user(&msg, sizeof(msg), arguser, sizeof(struct hsmp_message))) |
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return -EFAULT; |
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/* |
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* Check msg_id is within the range of supported msg ids |
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* i.e within the array bounds of hsmp_msg_desc_table |
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*/ |
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if (msg.msg_id < HSMP_TEST || msg.msg_id >= HSMP_MSG_ID_MAX) |
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return -ENOMSG; |
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switch (fp->f_mode & (FMODE_WRITE | FMODE_READ)) { |
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case FMODE_WRITE: |
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/* |
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* Device is opened in O_WRONLY mode |
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* Execute only set/configure commands |
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*/ |
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if (hsmp_msg_desc_table[msg.msg_id].type != HSMP_SET) |
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return -EINVAL; |
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break; |
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case FMODE_READ: |
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/* |
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* Device is opened in O_RDONLY mode |
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* Execute only get/monitor commands |
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*/ |
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if (hsmp_msg_desc_table[msg.msg_id].type != HSMP_GET) |
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return -EINVAL; |
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break; |
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case FMODE_READ | FMODE_WRITE: |
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/* |
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* Device is opened in O_RDWR mode |
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* Execute both get/monitor and set/configure commands |
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*/ |
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break; |
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default: |
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return -EINVAL; |
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} |
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ret = hsmp_send_message(&msg); |
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if (ret) |
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return ret; |
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if (hsmp_msg_desc_table[msg.msg_id].response_sz > 0) { |
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/* Copy results back to user for get/monitor commands */ |
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if (copy_to_user(arguser, &msg, sizeof(struct hsmp_message))) |
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return -EFAULT; |
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} |
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return 0; |
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} |
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static const struct file_operations hsmp_fops = { |
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.owner = THIS_MODULE, |
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.unlocked_ioctl = hsmp_ioctl, |
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.compat_ioctl = hsmp_ioctl, |
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}; |
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static int hsmp_pltdrv_probe(struct platform_device *pdev) |
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{ |
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int i; |
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hsmp_sem = devm_kzalloc(&pdev->dev, |
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(amd_nb_num() * sizeof(struct semaphore)), |
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GFP_KERNEL); |
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if (!hsmp_sem) |
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return -ENOMEM; |
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for (i = 0; i < amd_nb_num(); i++) |
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sema_init(&hsmp_sem[i], 1); |
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hsmp_device.name = "hsmp_cdev"; |
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hsmp_device.minor = MISC_DYNAMIC_MINOR; |
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hsmp_device.fops = &hsmp_fops; |
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hsmp_device.parent = &pdev->dev; |
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hsmp_device.nodename = "hsmp"; |
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hsmp_device.mode = 0644; |
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return misc_register(&hsmp_device); |
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} |
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static int hsmp_pltdrv_remove(struct platform_device *pdev) |
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{ |
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misc_deregister(&hsmp_device); |
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return 0; |
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} |
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static struct platform_driver amd_hsmp_driver = { |
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.probe = hsmp_pltdrv_probe, |
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.remove = hsmp_pltdrv_remove, |
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.driver = { |
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.name = DRIVER_NAME, |
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}, |
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}; |
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static struct platform_device *amd_hsmp_platdev; |
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static int __init hsmp_plt_init(void) |
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{ |
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int ret = -ENODEV; |
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u16 num_sockets; |
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int i; |
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD || boot_cpu_data.x86 < 0x19) { |
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pr_err("HSMP is not supported on Family:%x model:%x\n", |
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boot_cpu_data.x86, boot_cpu_data.x86_model); |
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return ret; |
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} |
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/* |
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* amd_nb_num() returns number of SMN/DF interfaces present in the system |
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* if we have N SMN/DF interfaces that ideally means N sockets |
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*/ |
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num_sockets = amd_nb_num(); |
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if (num_sockets == 0) |
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return ret; |
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/* Test the hsmp interface on each socket */ |
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for (i = 0; i < num_sockets; i++) { |
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ret = hsmp_test(i, 0xDEADBEEF); |
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if (ret) { |
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pr_err("HSMP is not supported on Fam:%x model:%x\n", |
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boot_cpu_data.x86, boot_cpu_data.x86_model); |
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pr_err("Or Is HSMP disabled in BIOS ?\n"); |
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return -EOPNOTSUPP; |
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} |
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} |
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ret = platform_driver_register(&amd_hsmp_driver); |
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if (ret) |
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return ret; |
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amd_hsmp_platdev = platform_device_alloc(DRIVER_NAME, -1); |
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if (!amd_hsmp_platdev) { |
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ret = -ENOMEM; |
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goto drv_unregister; |
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} |
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ret = platform_device_add(amd_hsmp_platdev); |
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if (ret) { |
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platform_device_put(amd_hsmp_platdev); |
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goto drv_unregister; |
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} |
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return 0; |
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drv_unregister: |
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platform_driver_unregister(&amd_hsmp_driver); |
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return ret; |
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} |
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static void __exit hsmp_plt_exit(void) |
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{ |
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platform_device_unregister(amd_hsmp_platdev); |
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platform_driver_unregister(&amd_hsmp_driver); |
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} |
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device_initcall(hsmp_plt_init); |
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module_exit(hsmp_plt_exit); |
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MODULE_DESCRIPTION("AMD HSMP Platform Interface Driver"); |
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MODULE_VERSION(DRIVER_VERSION); |
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MODULE_LICENSE("GPL v2");
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