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264 lines
6.7 KiB
264 lines
6.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Xilinx ZynqMP SHA Driver. |
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* Copyright (c) 2022 Xilinx Inc. |
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*/ |
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#include <linux/cacheflush.h> |
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#include <crypto/hash.h> |
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#include <crypto/internal/hash.h> |
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#include <crypto/sha3.h> |
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#include <linux/crypto.h> |
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#include <linux/device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/firmware/xlnx-zynqmp.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#define ZYNQMP_DMA_BIT_MASK 32U |
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#define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U |
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enum zynqmp_sha_op { |
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ZYNQMP_SHA3_INIT = 1, |
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ZYNQMP_SHA3_UPDATE = 2, |
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ZYNQMP_SHA3_FINAL = 4, |
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}; |
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struct zynqmp_sha_drv_ctx { |
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struct shash_alg sha3_384; |
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struct device *dev; |
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}; |
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struct zynqmp_sha_tfm_ctx { |
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struct device *dev; |
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struct crypto_shash *fbk_tfm; |
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}; |
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struct zynqmp_sha_desc_ctx { |
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struct shash_desc fbk_req; |
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}; |
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static dma_addr_t update_dma_addr, final_dma_addr; |
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static char *ubuf, *fbuf; |
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static int zynqmp_sha_init_tfm(struct crypto_shash *hash) |
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{ |
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const char *fallback_driver_name = crypto_shash_alg_name(hash); |
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struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash); |
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struct shash_alg *alg = crypto_shash_alg(hash); |
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struct crypto_shash *fallback_tfm; |
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struct zynqmp_sha_drv_ctx *drv_ctx; |
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drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384); |
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tfm_ctx->dev = drv_ctx->dev; |
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/* Allocate a fallback and abort if it failed. */ |
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fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0, |
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CRYPTO_ALG_NEED_FALLBACK); |
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if (IS_ERR(fallback_tfm)) |
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return PTR_ERR(fallback_tfm); |
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tfm_ctx->fbk_tfm = fallback_tfm; |
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hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm); |
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return 0; |
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} |
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static void zynqmp_sha_exit_tfm(struct crypto_shash *hash) |
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{ |
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struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash); |
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if (tfm_ctx->fbk_tfm) { |
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crypto_free_shash(tfm_ctx->fbk_tfm); |
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tfm_ctx->fbk_tfm = NULL; |
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} |
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memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx)); |
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} |
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static int zynqmp_sha_init(struct shash_desc *desc) |
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{ |
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struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc); |
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struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm); |
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dctx->fbk_req.tfm = tctx->fbk_tfm; |
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return crypto_shash_init(&dctx->fbk_req); |
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} |
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static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length) |
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{ |
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struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc); |
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return crypto_shash_update(&dctx->fbk_req, data, length); |
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} |
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static int zynqmp_sha_final(struct shash_desc *desc, u8 *out) |
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{ |
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struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc); |
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return crypto_shash_final(&dctx->fbk_req, out); |
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} |
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static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out) |
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{ |
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struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc); |
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return crypto_shash_finup(&dctx->fbk_req, data, length, out); |
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} |
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static int zynqmp_sha_import(struct shash_desc *desc, const void *in) |
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{ |
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struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc); |
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struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm); |
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dctx->fbk_req.tfm = tctx->fbk_tfm; |
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return crypto_shash_import(&dctx->fbk_req, in); |
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} |
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static int zynqmp_sha_export(struct shash_desc *desc, void *out) |
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{ |
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struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc); |
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return crypto_shash_export(&dctx->fbk_req, out); |
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} |
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static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out) |
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{ |
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unsigned int remaining_len = len; |
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int update_size; |
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int ret; |
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ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT); |
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if (ret) |
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return ret; |
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while (remaining_len != 0) { |
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memzero_explicit(ubuf, ZYNQMP_DMA_ALLOC_FIXED_SIZE); |
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if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) { |
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update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE; |
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remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE; |
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} else { |
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update_size = remaining_len; |
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remaining_len = 0; |
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} |
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memcpy(ubuf, data, update_size); |
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flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size); |
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ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE); |
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if (ret) |
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return ret; |
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data += update_size; |
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} |
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ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL); |
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memcpy(out, fbuf, SHA3_384_DIGEST_SIZE); |
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memzero_explicit(fbuf, SHA3_384_DIGEST_SIZE); |
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return ret; |
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} |
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static struct zynqmp_sha_drv_ctx sha3_drv_ctx = { |
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.sha3_384 = { |
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.init = zynqmp_sha_init, |
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.update = zynqmp_sha_update, |
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.final = zynqmp_sha_final, |
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.finup = zynqmp_sha_finup, |
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.digest = zynqmp_sha_digest, |
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.export = zynqmp_sha_export, |
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.import = zynqmp_sha_import, |
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.init_tfm = zynqmp_sha_init_tfm, |
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.exit_tfm = zynqmp_sha_exit_tfm, |
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.descsize = sizeof(struct zynqmp_sha_desc_ctx), |
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.statesize = sizeof(struct sha3_state), |
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.digestsize = SHA3_384_DIGEST_SIZE, |
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.base = { |
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.cra_name = "sha3-384", |
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.cra_driver_name = "zynqmp-sha3-384", |
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.cra_priority = 300, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
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CRYPTO_ALG_ALLOCATES_MEMORY | |
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CRYPTO_ALG_NEED_FALLBACK, |
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.cra_blocksize = SHA3_384_BLOCK_SIZE, |
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.cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx), |
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.cra_alignmask = 3, |
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.cra_module = THIS_MODULE, |
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} |
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} |
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}; |
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static int zynqmp_sha_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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int err; |
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u32 v; |
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/* Verify the hardware is present */ |
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err = zynqmp_pm_get_api_version(&v); |
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if (err) |
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return err; |
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK)); |
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if (err < 0) { |
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dev_err(dev, "No usable DMA configuration\n"); |
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return err; |
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} |
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err = crypto_register_shash(&sha3_drv_ctx.sha3_384); |
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if (err < 0) { |
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dev_err(dev, "Failed to register shash alg.\n"); |
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return err; |
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} |
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sha3_drv_ctx.dev = dev; |
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platform_set_drvdata(pdev, &sha3_drv_ctx); |
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ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL); |
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if (!ubuf) { |
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err = -ENOMEM; |
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goto err_shash; |
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} |
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fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL); |
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if (!fbuf) { |
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err = -ENOMEM; |
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goto err_mem; |
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} |
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return 0; |
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err_mem: |
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dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr); |
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err_shash: |
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crypto_unregister_shash(&sha3_drv_ctx.sha3_384); |
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return err; |
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} |
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static int zynqmp_sha_remove(struct platform_device *pdev) |
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{ |
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sha3_drv_ctx.dev = platform_get_drvdata(pdev); |
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dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr); |
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dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr); |
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crypto_unregister_shash(&sha3_drv_ctx.sha3_384); |
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return 0; |
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} |
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static struct platform_driver zynqmp_sha_driver = { |
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.probe = zynqmp_sha_probe, |
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.remove = zynqmp_sha_remove, |
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.driver = { |
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.name = "zynqmp-sha3-384", |
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}, |
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}; |
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module_platform_driver(zynqmp_sha_driver); |
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MODULE_DESCRIPTION("ZynqMP SHA3 hardware acceleration support."); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_AUTHOR("Harsha <[email protected]>");
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