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227 lines
5.3 KiB
227 lines
5.3 KiB
/* SPDX-License-Identifier: GPL-2.0 |
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* Marvell OcteonTX CPT driver |
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* |
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* Copyright (C) 2019 Marvell International Ltd. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#ifndef __OTX_CPTVF_REQUEST_MANAGER_H |
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#define __OTX_CPTVF_REQUEST_MANAGER_H |
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#include <linux/types.h> |
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#include <linux/crypto.h> |
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#include <linux/pci.h> |
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#include "otx_cpt_hw_types.h" |
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/* |
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* Maximum total number of SG buffers is 100, we divide it equally |
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* between input and output |
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*/ |
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#define OTX_CPT_MAX_SG_IN_CNT 50 |
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#define OTX_CPT_MAX_SG_OUT_CNT 50 |
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/* DMA mode direct or SG */ |
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#define OTX_CPT_DMA_DIRECT_DIRECT 0 |
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#define OTX_CPT_DMA_GATHER_SCATTER 1 |
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/* Context source CPTR or DPTR */ |
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#define OTX_CPT_FROM_CPTR 0 |
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#define OTX_CPT_FROM_DPTR 1 |
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/* CPT instruction queue alignment */ |
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#define OTX_CPT_INST_Q_ALIGNMENT 128 |
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#define OTX_CPT_MAX_REQ_SIZE 65535 |
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/* Default command timeout in seconds */ |
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#define OTX_CPT_COMMAND_TIMEOUT 4 |
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#define OTX_CPT_TIMER_HOLD 0x03F |
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#define OTX_CPT_COUNT_HOLD 32 |
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#define OTX_CPT_TIME_IN_RESET_COUNT 5 |
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/* Minimum and maximum values for interrupt coalescing */ |
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#define OTX_CPT_COALESC_MIN_TIME_WAIT 0x0 |
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#define OTX_CPT_COALESC_MAX_TIME_WAIT ((1<<16)-1) |
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#define OTX_CPT_COALESC_MIN_NUM_WAIT 0x0 |
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#define OTX_CPT_COALESC_MAX_NUM_WAIT ((1<<20)-1) |
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union otx_cpt_opcode_info { |
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u16 flags; |
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struct { |
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u8 major; |
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u8 minor; |
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} s; |
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}; |
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struct otx_cptvf_request { |
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u32 param1; |
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u32 param2; |
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u16 dlen; |
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union otx_cpt_opcode_info opcode; |
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}; |
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struct otx_cpt_buf_ptr { |
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u8 *vptr; |
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dma_addr_t dma_addr; |
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u16 size; |
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}; |
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union otx_cpt_ctrl_info { |
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u32 flags; |
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struct { |
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#if defined(__BIG_ENDIAN_BITFIELD) |
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u32 reserved0:26; |
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u32 grp:3; /* Group bits */ |
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u32 dma_mode:2; /* DMA mode */ |
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u32 se_req:1; /* To SE core */ |
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#else |
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u32 se_req:1; /* To SE core */ |
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u32 dma_mode:2; /* DMA mode */ |
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u32 grp:3; /* Group bits */ |
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u32 reserved0:26; |
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#endif |
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} s; |
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}; |
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/* |
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* CPT_INST_S software command definitions |
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* Words EI (0-3) |
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*/ |
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union otx_cpt_iq_cmd_word0 { |
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u64 u64; |
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struct { |
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__be16 opcode; |
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__be16 param1; |
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__be16 param2; |
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__be16 dlen; |
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} s; |
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}; |
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union otx_cpt_iq_cmd_word3 { |
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u64 u64; |
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struct { |
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#if defined(__BIG_ENDIAN_BITFIELD) |
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u64 grp:3; |
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u64 cptr:61; |
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#else |
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u64 cptr:61; |
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u64 grp:3; |
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#endif |
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} s; |
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}; |
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struct otx_cpt_iq_cmd { |
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union otx_cpt_iq_cmd_word0 cmd; |
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u64 dptr; |
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u64 rptr; |
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union otx_cpt_iq_cmd_word3 cptr; |
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}; |
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struct otx_cpt_sglist_component { |
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union { |
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u64 len; |
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struct { |
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__be16 len0; |
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__be16 len1; |
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__be16 len2; |
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__be16 len3; |
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} s; |
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} u; |
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__be64 ptr0; |
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__be64 ptr1; |
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__be64 ptr2; |
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__be64 ptr3; |
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}; |
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struct otx_cpt_pending_entry { |
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u64 *completion_addr; /* Completion address */ |
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struct otx_cpt_info_buffer *info; |
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/* Kernel async request callback */ |
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void (*callback)(int status, void *arg1, void *arg2); |
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struct crypto_async_request *areq; /* Async request callback arg */ |
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u8 resume_sender; /* Notify sender to resume sending requests */ |
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u8 busy; /* Entry status (free/busy) */ |
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}; |
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struct otx_cpt_pending_queue { |
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struct otx_cpt_pending_entry *head; /* Head of the queue */ |
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u32 front; /* Process work from here */ |
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u32 rear; /* Append new work here */ |
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u32 pending_count; /* Pending requests count */ |
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u32 qlen; /* Queue length */ |
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spinlock_t lock; /* Queue lock */ |
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}; |
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struct otx_cpt_req_info { |
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/* Kernel async request callback */ |
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void (*callback)(int status, void *arg1, void *arg2); |
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struct crypto_async_request *areq; /* Async request callback arg */ |
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struct otx_cptvf_request req;/* Request information (core specific) */ |
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union otx_cpt_ctrl_info ctrl;/* User control information */ |
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struct otx_cpt_buf_ptr in[OTX_CPT_MAX_SG_IN_CNT]; |
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struct otx_cpt_buf_ptr out[OTX_CPT_MAX_SG_OUT_CNT]; |
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u8 *iv_out; /* IV to send back */ |
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u16 rlen; /* Output length */ |
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u8 incnt; /* Number of input buffers */ |
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u8 outcnt; /* Number of output buffers */ |
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u8 req_type; /* Type of request */ |
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u8 is_enc; /* Is a request an encryption request */ |
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u8 is_trunc_hmac;/* Is truncated hmac used */ |
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}; |
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struct otx_cpt_info_buffer { |
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struct otx_cpt_pending_entry *pentry; |
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struct otx_cpt_req_info *req; |
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struct pci_dev *pdev; |
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u64 *completion_addr; |
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u8 *out_buffer; |
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u8 *in_buffer; |
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dma_addr_t dptr_baddr; |
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dma_addr_t rptr_baddr; |
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dma_addr_t comp_baddr; |
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unsigned long time_in; |
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u32 dlen; |
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u32 dma_len; |
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u8 extra_time; |
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}; |
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static inline void do_request_cleanup(struct pci_dev *pdev, |
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struct otx_cpt_info_buffer *info) |
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{ |
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struct otx_cpt_req_info *req; |
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int i; |
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if (info->dptr_baddr) |
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dma_unmap_single(&pdev->dev, info->dptr_baddr, |
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info->dma_len, DMA_BIDIRECTIONAL); |
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if (info->req) { |
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req = info->req; |
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for (i = 0; i < req->outcnt; i++) { |
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if (req->out[i].dma_addr) |
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dma_unmap_single(&pdev->dev, |
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req->out[i].dma_addr, |
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req->out[i].size, |
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DMA_BIDIRECTIONAL); |
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} |
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for (i = 0; i < req->incnt; i++) { |
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if (req->in[i].dma_addr) |
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dma_unmap_single(&pdev->dev, |
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req->in[i].dma_addr, |
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req->in[i].size, |
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DMA_BIDIRECTIONAL); |
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} |
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} |
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kfree_sensitive(info); |
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} |
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struct otx_cptvf_wqe; |
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void otx_cpt_dump_sg_list(struct pci_dev *pdev, struct otx_cpt_req_info *req); |
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void otx_cpt_post_process(struct otx_cptvf_wqe *wqe); |
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int otx_cpt_do_request(struct pci_dev *pdev, struct otx_cpt_req_info *req, |
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int cpu_num); |
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#endif /* __OTX_CPTVF_REQUEST_MANAGER_H */
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