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55 lines
1.1 KiB
C
55 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#ifndef _CCU_SUN8I_H3_H_
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#define _CCU_SUN8I_H3_H_
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#include <dt-bindings/clock/sun8i-h3-ccu.h>
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#include <dt-bindings/reset/sun8i-h3-ccu.h>
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#define CLK_PLL_CPUX 0
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#define CLK_PLL_AUDIO_BASE 1
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_AUDIO_2X 3
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#define CLK_PLL_AUDIO_4X 4
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#define CLK_PLL_AUDIO_8X 5
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/* PLL_VIDEO is exported */
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#define CLK_PLL_VE 7
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#define CLK_PLL_DDR 8
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/* PLL_PERIPH0 exported for PRCM */
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#define CLK_PLL_PERIPH0_2X 10
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#define CLK_PLL_GPU 11
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#define CLK_PLL_PERIPH1 12
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#define CLK_PLL_DE 13
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/* The CPUX clock is exported */
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#define CLK_AXI 15
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#define CLK_AHB1 16
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#define CLK_APB1 17
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#define CLK_APB2 18
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#define CLK_AHB2 19
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/* All the bus gates are exported */
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/* The first bunch of module clocks are exported */
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#define CLK_DRAM 96
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_NUMBER_H3 (CLK_GPU + 1)
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#define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1)
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#endif /* _CCU_SUN8I_H3_H_ */
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