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906 lines
23 KiB
906 lines
23 KiB
/* |
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* Copyright (c) 2012 Intel Corporation. All rights reserved. |
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* Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. |
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* Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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|
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/* |
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* This file contains support for diagnostic functions. It is accessed by |
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* opening the qib_diag device, normally minor number 129. Diagnostic use |
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* of the QLogic_IB chip may render the chip or board unusable until the |
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* driver is unloaded, or in some cases, until the system is rebooted. |
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* |
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* Accesses to the chip through this interface are not similar to going |
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* through the /sys/bus/pci resource mmap interface. |
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*/ |
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|
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#include <linux/io.h> |
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#include <linux/pci.h> |
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#include <linux/poll.h> |
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#include <linux/vmalloc.h> |
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#include <linux/export.h> |
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#include <linux/fs.h> |
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#include <linux/uaccess.h> |
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|
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#include "qib.h" |
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#include "qib_common.h" |
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|
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#undef pr_fmt |
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#define pr_fmt(fmt) QIB_DRV_NAME ": " fmt |
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|
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/* |
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* Each client that opens the diag device must read then write |
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* offset 0, to prevent lossage from random cat or od. diag_state |
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* sequences this "handshake". |
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*/ |
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enum diag_state { UNUSED = 0, OPENED, INIT, READY }; |
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|
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/* State for an individual client. PID so children cannot abuse handshake */ |
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static struct qib_diag_client { |
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struct qib_diag_client *next; |
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struct qib_devdata *dd; |
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pid_t pid; |
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enum diag_state state; |
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} *client_pool; |
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|
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/* |
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* Get a client struct. Recycled if possible, else kmalloc. |
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* Must be called with qib_mutex held |
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*/ |
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static struct qib_diag_client *get_client(struct qib_devdata *dd) |
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{ |
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struct qib_diag_client *dc; |
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|
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dc = client_pool; |
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if (dc) |
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/* got from pool remove it and use */ |
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client_pool = dc->next; |
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else |
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/* None in pool, alloc and init */ |
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dc = kmalloc(sizeof(*dc), GFP_KERNEL); |
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|
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if (dc) { |
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dc->next = NULL; |
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dc->dd = dd; |
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dc->pid = current->pid; |
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dc->state = OPENED; |
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} |
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return dc; |
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} |
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|
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/* |
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* Return to pool. Must be called with qib_mutex held |
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*/ |
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static void return_client(struct qib_diag_client *dc) |
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{ |
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struct qib_devdata *dd = dc->dd; |
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struct qib_diag_client *tdc, *rdc; |
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|
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rdc = NULL; |
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if (dc == dd->diag_client) { |
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dd->diag_client = dc->next; |
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rdc = dc; |
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} else { |
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tdc = dc->dd->diag_client; |
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while (tdc) { |
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if (dc == tdc->next) { |
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tdc->next = dc->next; |
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rdc = dc; |
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break; |
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} |
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tdc = tdc->next; |
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} |
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} |
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if (rdc) { |
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rdc->state = UNUSED; |
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rdc->dd = NULL; |
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rdc->pid = 0; |
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rdc->next = client_pool; |
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client_pool = rdc; |
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} |
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} |
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|
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static int qib_diag_open(struct inode *in, struct file *fp); |
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static int qib_diag_release(struct inode *in, struct file *fp); |
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static ssize_t qib_diag_read(struct file *fp, char __user *data, |
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size_t count, loff_t *off); |
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static ssize_t qib_diag_write(struct file *fp, const char __user *data, |
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size_t count, loff_t *off); |
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|
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static const struct file_operations diag_file_ops = { |
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.owner = THIS_MODULE, |
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.write = qib_diag_write, |
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.read = qib_diag_read, |
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.open = qib_diag_open, |
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.release = qib_diag_release, |
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.llseek = default_llseek, |
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}; |
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static atomic_t diagpkt_count = ATOMIC_INIT(0); |
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static struct cdev *diagpkt_cdev; |
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static struct device *diagpkt_device; |
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|
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static ssize_t qib_diagpkt_write(struct file *fp, const char __user *data, |
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size_t count, loff_t *off); |
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|
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static const struct file_operations diagpkt_file_ops = { |
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.owner = THIS_MODULE, |
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.write = qib_diagpkt_write, |
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.llseek = noop_llseek, |
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}; |
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int qib_diag_add(struct qib_devdata *dd) |
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{ |
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char name[16]; |
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int ret = 0; |
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|
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if (atomic_inc_return(&diagpkt_count) == 1) { |
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ret = qib_cdev_init(QIB_DIAGPKT_MINOR, "ipath_diagpkt", |
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&diagpkt_file_ops, &diagpkt_cdev, |
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&diagpkt_device); |
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if (ret) |
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goto done; |
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} |
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snprintf(name, sizeof(name), "ipath_diag%d", dd->unit); |
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ret = qib_cdev_init(QIB_DIAG_MINOR_BASE + dd->unit, name, |
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&diag_file_ops, &dd->diag_cdev, |
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&dd->diag_device); |
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done: |
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return ret; |
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} |
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static void qib_unregister_observers(struct qib_devdata *dd); |
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|
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void qib_diag_remove(struct qib_devdata *dd) |
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{ |
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struct qib_diag_client *dc; |
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|
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if (atomic_dec_and_test(&diagpkt_count)) |
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qib_cdev_cleanup(&diagpkt_cdev, &diagpkt_device); |
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qib_cdev_cleanup(&dd->diag_cdev, &dd->diag_device); |
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|
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/* |
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* Return all diag_clients of this device. There should be none, |
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* as we are "guaranteed" that no clients are still open |
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*/ |
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while (dd->diag_client) |
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return_client(dd->diag_client); |
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|
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/* Now clean up all unused client structs */ |
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while (client_pool) { |
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dc = client_pool; |
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client_pool = dc->next; |
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kfree(dc); |
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} |
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/* Clean up observer list */ |
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qib_unregister_observers(dd); |
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} |
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|
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/* qib_remap_ioaddr32 - remap an offset into chip address space to __iomem * |
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* |
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* @dd: the qlogic_ib device |
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* @offs: the offset in chip-space |
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* @cntp: Pointer to max (byte) count for transfer starting at offset |
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* This returns a u32 __iomem * so it can be used for both 64 and 32-bit |
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* mapping. It is needed because with the use of PAT for control of |
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* write-combining, the logically contiguous address-space of the chip |
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* may be split into virtually non-contiguous spaces, with different |
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* attributes, which are them mapped to contiguous physical space |
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* based from the first BAR. |
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* |
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* The code below makes the same assumptions as were made in |
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* init_chip_wc_pat() (qib_init.c), copied here: |
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* Assumes chip address space looks like: |
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* - kregs + sregs + cregs + uregs (in any order) |
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* - piobufs (2K and 4K bufs in either order) |
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* or: |
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* - kregs + sregs + cregs (in any order) |
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* - piobufs (2K and 4K bufs in either order) |
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* - uregs |
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* |
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* If cntp is non-NULL, returns how many bytes from offset can be accessed |
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* Returns 0 if the offset is not mapped. |
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*/ |
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static u32 __iomem *qib_remap_ioaddr32(struct qib_devdata *dd, u32 offset, |
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u32 *cntp) |
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{ |
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u32 kreglen; |
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u32 snd_bottom, snd_lim = 0; |
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u32 __iomem *krb32 = (u32 __iomem *)dd->kregbase; |
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u32 __iomem *map = NULL; |
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u32 cnt = 0; |
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u32 tot4k, offs4k; |
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|
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/* First, simplest case, offset is within the first map. */ |
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kreglen = (dd->kregend - dd->kregbase) * sizeof(u64); |
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if (offset < kreglen) { |
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map = krb32 + (offset / sizeof(u32)); |
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cnt = kreglen - offset; |
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goto mapped; |
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} |
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|
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/* |
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* Next check for user regs, the next most common case, |
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* and a cheap check because if they are not in the first map |
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* they are last in chip. |
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*/ |
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if (dd->userbase) { |
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/* If user regs mapped, they are after send, so set limit. */ |
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u32 ulim = (dd->cfgctxts * dd->ureg_align) + dd->uregbase; |
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|
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if (!dd->piovl15base) |
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snd_lim = dd->uregbase; |
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krb32 = (u32 __iomem *)dd->userbase; |
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if (offset >= dd->uregbase && offset < ulim) { |
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map = krb32 + (offset - dd->uregbase) / sizeof(u32); |
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cnt = ulim - offset; |
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goto mapped; |
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} |
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} |
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/* |
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* Lastly, check for offset within Send Buffers. |
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* This is gnarly because struct devdata is deliberately vague |
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* about things like 7322 VL15 buffers, and we are not in |
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* chip-specific code here, so should not make many assumptions. |
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* The one we _do_ make is that the only chip that has more sndbufs |
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* than we admit is the 7322, and it has userregs above that, so |
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* we know the snd_lim. |
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*/ |
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/* Assume 2K buffers are first. */ |
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snd_bottom = dd->pio2k_bufbase; |
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if (snd_lim == 0) { |
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u32 tot2k = dd->piobcnt2k * ALIGN(dd->piosize2k, dd->palign); |
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snd_lim = snd_bottom + tot2k; |
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} |
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/* If 4k buffers exist, account for them by bumping |
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* appropriate limit. |
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*/ |
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tot4k = dd->piobcnt4k * dd->align4k; |
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offs4k = dd->piobufbase >> 32; |
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if (dd->piobcnt4k) { |
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if (snd_bottom > offs4k) |
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snd_bottom = offs4k; |
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else { |
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/* 4k above 2k. Bump snd_lim, if needed*/ |
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if (!dd->userbase || dd->piovl15base) |
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snd_lim = offs4k + tot4k; |
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} |
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} |
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/* |
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* Judgement call: can we ignore the space between SendBuffs and |
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* UserRegs, where we would like to see vl15 buffs, but not more? |
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*/ |
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if (offset >= snd_bottom && offset < snd_lim) { |
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offset -= snd_bottom; |
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map = (u32 __iomem *)dd->piobase + (offset / sizeof(u32)); |
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cnt = snd_lim - offset; |
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} |
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|
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if (!map && offs4k && dd->piovl15base) { |
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snd_lim = offs4k + tot4k + 2 * dd->align4k; |
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if (offset >= (offs4k + tot4k) && offset < snd_lim) { |
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map = (u32 __iomem *)dd->piovl15base + |
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((offset - (offs4k + tot4k)) / sizeof(u32)); |
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cnt = snd_lim - offset; |
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} |
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} |
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mapped: |
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if (cntp) |
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*cntp = cnt; |
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return map; |
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} |
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|
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/* |
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* qib_read_umem64 - read a 64-bit quantity from the chip into user space |
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* @dd: the qlogic_ib device |
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* @uaddr: the location to store the data in user memory |
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* @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore) |
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* @count: number of bytes to copy (multiple of 32 bits) |
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* |
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* This function also localizes all chip memory accesses. |
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* The copy should be written such that we read full cacheline packets |
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* from the chip. This is usually used for a single qword |
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* |
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* NOTE: This assumes the chip address is 64-bit aligned. |
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*/ |
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static int qib_read_umem64(struct qib_devdata *dd, void __user *uaddr, |
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u32 regoffs, size_t count) |
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{ |
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const u64 __iomem *reg_addr; |
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const u64 __iomem *reg_end; |
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u32 limit; |
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int ret; |
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|
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reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); |
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if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { |
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ret = -EINVAL; |
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goto bail; |
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} |
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if (count >= limit) |
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count = limit; |
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reg_end = reg_addr + (count / sizeof(u64)); |
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|
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/* not very efficient, but it works for now */ |
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while (reg_addr < reg_end) { |
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u64 data = readq(reg_addr); |
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|
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if (copy_to_user(uaddr, &data, sizeof(u64))) { |
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ret = -EFAULT; |
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goto bail; |
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} |
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reg_addr++; |
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uaddr += sizeof(u64); |
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} |
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ret = 0; |
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bail: |
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return ret; |
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} |
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|
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/* |
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* qib_write_umem64 - write a 64-bit quantity to the chip from user space |
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* @dd: the qlogic_ib device |
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* @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore) |
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* @uaddr: the source of the data in user memory |
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* @count: the number of bytes to copy (multiple of 32 bits) |
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* |
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* This is usually used for a single qword |
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* NOTE: This assumes the chip address is 64-bit aligned. |
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*/ |
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|
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static int qib_write_umem64(struct qib_devdata *dd, u32 regoffs, |
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const void __user *uaddr, size_t count) |
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{ |
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u64 __iomem *reg_addr; |
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const u64 __iomem *reg_end; |
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u32 limit; |
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int ret; |
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|
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reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); |
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if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { |
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ret = -EINVAL; |
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goto bail; |
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} |
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if (count >= limit) |
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count = limit; |
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reg_end = reg_addr + (count / sizeof(u64)); |
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|
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/* not very efficient, but it works for now */ |
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while (reg_addr < reg_end) { |
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u64 data; |
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|
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if (copy_from_user(&data, uaddr, sizeof(data))) { |
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ret = -EFAULT; |
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goto bail; |
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} |
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writeq(data, reg_addr); |
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|
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reg_addr++; |
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uaddr += sizeof(u64); |
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} |
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ret = 0; |
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bail: |
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return ret; |
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} |
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|
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/* |
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* qib_read_umem32 - read a 32-bit quantity from the chip into user space |
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* @dd: the qlogic_ib device |
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* @uaddr: the location to store the data in user memory |
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* @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore) |
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* @count: number of bytes to copy |
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* |
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* read 32 bit values, not 64 bit; for memories that only |
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* support 32 bit reads; usually a single dword. |
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*/ |
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static int qib_read_umem32(struct qib_devdata *dd, void __user *uaddr, |
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u32 regoffs, size_t count) |
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{ |
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const u32 __iomem *reg_addr; |
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const u32 __iomem *reg_end; |
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u32 limit; |
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int ret; |
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|
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reg_addr = qib_remap_ioaddr32(dd, regoffs, &limit); |
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if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { |
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ret = -EINVAL; |
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goto bail; |
|
} |
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if (count >= limit) |
|
count = limit; |
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reg_end = reg_addr + (count / sizeof(u32)); |
|
|
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/* not very efficient, but it works for now */ |
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while (reg_addr < reg_end) { |
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u32 data = readl(reg_addr); |
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|
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if (copy_to_user(uaddr, &data, sizeof(data))) { |
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ret = -EFAULT; |
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goto bail; |
|
} |
|
|
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reg_addr++; |
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uaddr += sizeof(u32); |
|
|
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} |
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ret = 0; |
|
bail: |
|
return ret; |
|
} |
|
|
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/* |
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* qib_write_umem32 - write a 32-bit quantity to the chip from user space |
|
* @dd: the qlogic_ib device |
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* @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore) |
|
* @uaddr: the source of the data in user memory |
|
* @count: number of bytes to copy |
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* |
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* write 32 bit values, not 64 bit; for memories that only |
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* support 32 bit write; usually a single dword. |
|
*/ |
|
|
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static int qib_write_umem32(struct qib_devdata *dd, u32 regoffs, |
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const void __user *uaddr, size_t count) |
|
{ |
|
u32 __iomem *reg_addr; |
|
const u32 __iomem *reg_end; |
|
u32 limit; |
|
int ret; |
|
|
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reg_addr = qib_remap_ioaddr32(dd, regoffs, &limit); |
|
if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { |
|
ret = -EINVAL; |
|
goto bail; |
|
} |
|
if (count >= limit) |
|
count = limit; |
|
reg_end = reg_addr + (count / sizeof(u32)); |
|
|
|
while (reg_addr < reg_end) { |
|
u32 data; |
|
|
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if (copy_from_user(&data, uaddr, sizeof(data))) { |
|
ret = -EFAULT; |
|
goto bail; |
|
} |
|
writel(data, reg_addr); |
|
|
|
reg_addr++; |
|
uaddr += sizeof(u32); |
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} |
|
ret = 0; |
|
bail: |
|
return ret; |
|
} |
|
|
|
static int qib_diag_open(struct inode *in, struct file *fp) |
|
{ |
|
int unit = iminor(in) - QIB_DIAG_MINOR_BASE; |
|
struct qib_devdata *dd; |
|
struct qib_diag_client *dc; |
|
int ret; |
|
|
|
mutex_lock(&qib_mutex); |
|
|
|
dd = qib_lookup(unit); |
|
|
|
if (dd == NULL || !(dd->flags & QIB_PRESENT) || |
|
!dd->kregbase) { |
|
ret = -ENODEV; |
|
goto bail; |
|
} |
|
|
|
dc = get_client(dd); |
|
if (!dc) { |
|
ret = -ENOMEM; |
|
goto bail; |
|
} |
|
dc->next = dd->diag_client; |
|
dd->diag_client = dc; |
|
fp->private_data = dc; |
|
ret = 0; |
|
bail: |
|
mutex_unlock(&qib_mutex); |
|
|
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return ret; |
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} |
|
|
|
/** |
|
* qib_diagpkt_write - write an IB packet |
|
* @fp: the diag data device file pointer |
|
* @data: qib_diag_pkt structure saying where to get the packet |
|
* @count: size of data to write |
|
* @off: unused by this code |
|
*/ |
|
static ssize_t qib_diagpkt_write(struct file *fp, |
|
const char __user *data, |
|
size_t count, loff_t *off) |
|
{ |
|
u32 __iomem *piobuf; |
|
u32 plen, pbufn, maxlen_reserve; |
|
struct qib_diag_xpkt dp; |
|
u32 *tmpbuf = NULL; |
|
struct qib_devdata *dd; |
|
struct qib_pportdata *ppd; |
|
ssize_t ret = 0; |
|
|
|
if (count != sizeof(dp)) { |
|
ret = -EINVAL; |
|
goto bail; |
|
} |
|
if (copy_from_user(&dp, data, sizeof(dp))) { |
|
ret = -EFAULT; |
|
goto bail; |
|
} |
|
|
|
dd = qib_lookup(dp.unit); |
|
if (!dd || !(dd->flags & QIB_PRESENT) || !dd->kregbase) { |
|
ret = -ENODEV; |
|
goto bail; |
|
} |
|
if (!(dd->flags & QIB_INITTED)) { |
|
/* no hardware, freeze, etc. */ |
|
ret = -ENODEV; |
|
goto bail; |
|
} |
|
|
|
if (dp.version != _DIAG_XPKT_VERS) { |
|
qib_dev_err(dd, "Invalid version %u for diagpkt_write\n", |
|
dp.version); |
|
ret = -EINVAL; |
|
goto bail; |
|
} |
|
/* send count must be an exact number of dwords */ |
|
if (dp.len & 3) { |
|
ret = -EINVAL; |
|
goto bail; |
|
} |
|
if (!dp.port || dp.port > dd->num_pports) { |
|
ret = -EINVAL; |
|
goto bail; |
|
} |
|
ppd = &dd->pport[dp.port - 1]; |
|
|
|
/* |
|
* need total length before first word written, plus 2 Dwords. One Dword |
|
* is for padding so we get the full user data when not aligned on |
|
* a word boundary. The other Dword is to make sure we have room for the |
|
* ICRC which gets tacked on later. |
|
*/ |
|
maxlen_reserve = 2 * sizeof(u32); |
|
if (dp.len > ppd->ibmaxlen - maxlen_reserve) { |
|
ret = -EINVAL; |
|
goto bail; |
|
} |
|
|
|
plen = sizeof(u32) + dp.len; |
|
|
|
tmpbuf = vmalloc(plen); |
|
if (!tmpbuf) { |
|
ret = -ENOMEM; |
|
goto bail; |
|
} |
|
|
|
if (copy_from_user(tmpbuf, |
|
u64_to_user_ptr(dp.data), |
|
dp.len)) { |
|
ret = -EFAULT; |
|
goto bail; |
|
} |
|
|
|
plen >>= 2; /* in dwords */ |
|
|
|
if (dp.pbc_wd == 0) |
|
dp.pbc_wd = plen; |
|
|
|
piobuf = dd->f_getsendbuf(ppd, dp.pbc_wd, &pbufn); |
|
if (!piobuf) { |
|
ret = -EBUSY; |
|
goto bail; |
|
} |
|
/* disarm it just to be extra sure */ |
|
dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbufn)); |
|
|
|
/* disable header check on pbufn for this packet */ |
|
dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_DIS1, NULL); |
|
|
|
writeq(dp.pbc_wd, piobuf); |
|
/* |
|
* Copy all but the trigger word, then flush, so it's written |
|
* to chip before trigger word, then write trigger word, then |
|
* flush again, so packet is sent. |
|
*/ |
|
if (dd->flags & QIB_PIO_FLUSH_WC) { |
|
qib_flush_wc(); |
|
qib_pio_copy(piobuf + 2, tmpbuf, plen - 1); |
|
qib_flush_wc(); |
|
__raw_writel(tmpbuf[plen - 1], piobuf + plen + 1); |
|
} else |
|
qib_pio_copy(piobuf + 2, tmpbuf, plen); |
|
|
|
if (dd->flags & QIB_USE_SPCL_TRIG) { |
|
u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023; |
|
|
|
qib_flush_wc(); |
|
__raw_writel(0xaebecede, piobuf + spcl_off); |
|
} |
|
|
|
/* |
|
* Ensure buffer is written to the chip, then re-enable |
|
* header checks (if supported by chip). The txchk |
|
* code will ensure seen by chip before returning. |
|
*/ |
|
qib_flush_wc(); |
|
qib_sendbuf_done(dd, pbufn); |
|
dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_ENAB1, NULL); |
|
|
|
ret = sizeof(dp); |
|
|
|
bail: |
|
vfree(tmpbuf); |
|
return ret; |
|
} |
|
|
|
static int qib_diag_release(struct inode *in, struct file *fp) |
|
{ |
|
mutex_lock(&qib_mutex); |
|
return_client(fp->private_data); |
|
fp->private_data = NULL; |
|
mutex_unlock(&qib_mutex); |
|
return 0; |
|
} |
|
|
|
/* |
|
* Chip-specific code calls to register its interest in |
|
* a specific range. |
|
*/ |
|
struct diag_observer_list_elt { |
|
struct diag_observer_list_elt *next; |
|
const struct diag_observer *op; |
|
}; |
|
|
|
int qib_register_observer(struct qib_devdata *dd, |
|
const struct diag_observer *op) |
|
{ |
|
struct diag_observer_list_elt *olp; |
|
unsigned long flags; |
|
|
|
if (!dd || !op) |
|
return -EINVAL; |
|
olp = vmalloc(sizeof(*olp)); |
|
if (!olp) |
|
return -ENOMEM; |
|
|
|
spin_lock_irqsave(&dd->qib_diag_trans_lock, flags); |
|
olp->op = op; |
|
olp->next = dd->diag_observer_list; |
|
dd->diag_observer_list = olp; |
|
spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
/* Remove all registered observers when device is closed */ |
|
static void qib_unregister_observers(struct qib_devdata *dd) |
|
{ |
|
struct diag_observer_list_elt *olp; |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&dd->qib_diag_trans_lock, flags); |
|
olp = dd->diag_observer_list; |
|
while (olp) { |
|
/* Pop one observer, let go of lock */ |
|
dd->diag_observer_list = olp->next; |
|
spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags); |
|
vfree(olp); |
|
/* try again. */ |
|
spin_lock_irqsave(&dd->qib_diag_trans_lock, flags); |
|
olp = dd->diag_observer_list; |
|
} |
|
spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags); |
|
} |
|
|
|
/* |
|
* Find the observer, if any, for the specified address. Initial implementation |
|
* is simple stack of observers. This must be called with diag transaction |
|
* lock held. |
|
*/ |
|
static const struct diag_observer *diag_get_observer(struct qib_devdata *dd, |
|
u32 addr) |
|
{ |
|
struct diag_observer_list_elt *olp; |
|
const struct diag_observer *op = NULL; |
|
|
|
olp = dd->diag_observer_list; |
|
while (olp) { |
|
op = olp->op; |
|
if (addr >= op->bottom && addr <= op->top) |
|
break; |
|
olp = olp->next; |
|
} |
|
if (!olp) |
|
op = NULL; |
|
|
|
return op; |
|
} |
|
|
|
static ssize_t qib_diag_read(struct file *fp, char __user *data, |
|
size_t count, loff_t *off) |
|
{ |
|
struct qib_diag_client *dc = fp->private_data; |
|
struct qib_devdata *dd = dc->dd; |
|
ssize_t ret; |
|
|
|
if (dc->pid != current->pid) { |
|
ret = -EPERM; |
|
goto bail; |
|
} |
|
|
|
if (count == 0) |
|
ret = 0; |
|
else if ((count % 4) || (*off % 4)) |
|
/* address or length is not 32-bit aligned, hence invalid */ |
|
ret = -EINVAL; |
|
else if (dc->state < READY && (*off || count != 8)) |
|
ret = -EINVAL; /* prevent cat /dev/qib_diag* */ |
|
else { |
|
unsigned long flags; |
|
u64 data64 = 0; |
|
int use_32; |
|
const struct diag_observer *op; |
|
|
|
use_32 = (count % 8) || (*off % 8); |
|
ret = -1; |
|
spin_lock_irqsave(&dd->qib_diag_trans_lock, flags); |
|
/* |
|
* Check for observer on this address range. |
|
* we only support a single 32 or 64-bit read |
|
* via observer, currently. |
|
*/ |
|
op = diag_get_observer(dd, *off); |
|
if (op) { |
|
u32 offset = *off; |
|
|
|
ret = op->hook(dd, op, offset, &data64, 0, use_32); |
|
} |
|
/* |
|
* We need to release lock before any copy_to_user(), |
|
* whether implicit in qib_read_umem* or explicit below. |
|
*/ |
|
spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags); |
|
if (!op) { |
|
if (use_32) |
|
/* |
|
* Address or length is not 64-bit aligned; |
|
* do 32-bit rd |
|
*/ |
|
ret = qib_read_umem32(dd, data, (u32) *off, |
|
count); |
|
else |
|
ret = qib_read_umem64(dd, data, (u32) *off, |
|
count); |
|
} else if (ret == count) { |
|
/* Below finishes case where observer existed */ |
|
ret = copy_to_user(data, &data64, use_32 ? |
|
sizeof(u32) : sizeof(u64)); |
|
if (ret) |
|
ret = -EFAULT; |
|
} |
|
} |
|
|
|
if (ret >= 0) { |
|
*off += count; |
|
ret = count; |
|
if (dc->state == OPENED) |
|
dc->state = INIT; |
|
} |
|
bail: |
|
return ret; |
|
} |
|
|
|
static ssize_t qib_diag_write(struct file *fp, const char __user *data, |
|
size_t count, loff_t *off) |
|
{ |
|
struct qib_diag_client *dc = fp->private_data; |
|
struct qib_devdata *dd = dc->dd; |
|
ssize_t ret; |
|
|
|
if (dc->pid != current->pid) { |
|
ret = -EPERM; |
|
goto bail; |
|
} |
|
|
|
if (count == 0) |
|
ret = 0; |
|
else if ((count % 4) || (*off % 4)) |
|
/* address or length is not 32-bit aligned, hence invalid */ |
|
ret = -EINVAL; |
|
else if (dc->state < READY && |
|
((*off || count != 8) || dc->state != INIT)) |
|
/* No writes except second-step of init seq */ |
|
ret = -EINVAL; /* before any other write allowed */ |
|
else { |
|
unsigned long flags; |
|
const struct diag_observer *op = NULL; |
|
int use_32 = (count % 8) || (*off % 8); |
|
|
|
/* |
|
* Check for observer on this address range. |
|
* We only support a single 32 or 64-bit write |
|
* via observer, currently. This helps, because |
|
* we would otherwise have to jump through hoops |
|
* to make "diag transaction" meaningful when we |
|
* cannot do a copy_from_user while holding the lock. |
|
*/ |
|
if (count == 4 || count == 8) { |
|
u64 data64; |
|
u32 offset = *off; |
|
|
|
ret = copy_from_user(&data64, data, count); |
|
if (ret) { |
|
ret = -EFAULT; |
|
goto bail; |
|
} |
|
spin_lock_irqsave(&dd->qib_diag_trans_lock, flags); |
|
op = diag_get_observer(dd, *off); |
|
if (op) |
|
ret = op->hook(dd, op, offset, &data64, ~0Ull, |
|
use_32); |
|
spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags); |
|
} |
|
|
|
if (!op) { |
|
if (use_32) |
|
/* |
|
* Address or length is not 64-bit aligned; |
|
* do 32-bit write |
|
*/ |
|
ret = qib_write_umem32(dd, (u32) *off, data, |
|
count); |
|
else |
|
ret = qib_write_umem64(dd, (u32) *off, data, |
|
count); |
|
} |
|
} |
|
|
|
if (ret >= 0) { |
|
*off += count; |
|
ret = count; |
|
if (dc->state == INIT) |
|
dc->state = READY; /* all read/write OK now */ |
|
} |
|
bail: |
|
return ret; |
|
}
|
|
|