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325 lines
10 KiB
325 lines
10 KiB
/* |
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. |
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
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* Copyright (c) 2006 Cisco Systems. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef MTHCA_CMD_H |
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#define MTHCA_CMD_H |
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#include <rdma/ib_verbs.h> |
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#define MTHCA_MAILBOX_SIZE 4096 |
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enum { |
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/* command completed successfully: */ |
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MTHCA_CMD_STAT_OK = 0x00, |
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/* Internal error (such as a bus error) occurred while processing command: */ |
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MTHCA_CMD_STAT_INTERNAL_ERR = 0x01, |
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/* Operation/command not supported or opcode modifier not supported: */ |
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MTHCA_CMD_STAT_BAD_OP = 0x02, |
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/* Parameter not supported or parameter out of range: */ |
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MTHCA_CMD_STAT_BAD_PARAM = 0x03, |
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/* System not enabled or bad system state: */ |
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MTHCA_CMD_STAT_BAD_SYS_STATE = 0x04, |
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/* Attempt to access reserved or unallocaterd resource: */ |
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MTHCA_CMD_STAT_BAD_RESOURCE = 0x05, |
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/* Requested resource is currently executing a command, or is otherwise busy: */ |
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MTHCA_CMD_STAT_RESOURCE_BUSY = 0x06, |
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/* memory error: */ |
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MTHCA_CMD_STAT_DDR_MEM_ERR = 0x07, |
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/* Required capability exceeds device limits: */ |
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MTHCA_CMD_STAT_EXCEED_LIM = 0x08, |
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/* Resource is not in the appropriate state or ownership: */ |
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MTHCA_CMD_STAT_BAD_RES_STATE = 0x09, |
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/* Index out of range: */ |
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MTHCA_CMD_STAT_BAD_INDEX = 0x0a, |
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/* FW image corrupted: */ |
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MTHCA_CMD_STAT_BAD_NVMEM = 0x0b, |
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/* Attempt to modify a QP/EE which is not in the presumed state: */ |
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MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10, |
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/* Bad segment parameters (Address/Size): */ |
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MTHCA_CMD_STAT_BAD_SEG_PARAM = 0x20, |
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/* Memory Region has Memory Windows bound to: */ |
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MTHCA_CMD_STAT_REG_BOUND = 0x21, |
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/* HCA local attached memory not present: */ |
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MTHCA_CMD_STAT_LAM_NOT_PRE = 0x22, |
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/* Bad management packet (silently discarded): */ |
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MTHCA_CMD_STAT_BAD_PKT = 0x30, |
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/* More outstanding CQEs in CQ than new CQ size: */ |
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MTHCA_CMD_STAT_BAD_SIZE = 0x40 |
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}; |
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enum { |
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MTHCA_TRANS_INVALID = 0, |
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MTHCA_TRANS_RST2INIT, |
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MTHCA_TRANS_INIT2INIT, |
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MTHCA_TRANS_INIT2RTR, |
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MTHCA_TRANS_RTR2RTS, |
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MTHCA_TRANS_RTS2RTS, |
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MTHCA_TRANS_SQERR2RTS, |
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MTHCA_TRANS_ANY2ERR, |
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MTHCA_TRANS_RTS2SQD, |
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MTHCA_TRANS_SQD2SQD, |
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MTHCA_TRANS_SQD2RTS, |
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MTHCA_TRANS_ANY2RST, |
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}; |
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enum { |
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DEV_LIM_FLAG_RC = 1 << 0, |
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DEV_LIM_FLAG_UC = 1 << 1, |
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DEV_LIM_FLAG_UD = 1 << 2, |
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DEV_LIM_FLAG_RD = 1 << 3, |
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DEV_LIM_FLAG_RAW_IPV6 = 1 << 4, |
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DEV_LIM_FLAG_RAW_ETHER = 1 << 5, |
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DEV_LIM_FLAG_SRQ = 1 << 6, |
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DEV_LIM_FLAG_IPOIB_CSUM = 1 << 7, |
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DEV_LIM_FLAG_BAD_PKEY_CNTR = 1 << 8, |
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DEV_LIM_FLAG_BAD_QKEY_CNTR = 1 << 9, |
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DEV_LIM_FLAG_MW = 1 << 16, |
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DEV_LIM_FLAG_AUTO_PATH_MIG = 1 << 17, |
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DEV_LIM_FLAG_ATOMIC = 1 << 18, |
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DEV_LIM_FLAG_RAW_MULTI = 1 << 19, |
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DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20, |
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DEV_LIM_FLAG_UD_MULTI = 1 << 21, |
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}; |
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struct mthca_mailbox { |
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dma_addr_t dma; |
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void *buf; |
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}; |
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struct mthca_dev_lim { |
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int max_srq_sz; |
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int max_qp_sz; |
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int reserved_qps; |
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int max_qps; |
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int reserved_srqs; |
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int max_srqs; |
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int reserved_eecs; |
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int max_eecs; |
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int max_cq_sz; |
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int reserved_cqs; |
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int max_cqs; |
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int max_mpts; |
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int reserved_eqs; |
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int max_eqs; |
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int reserved_mtts; |
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int max_mrw_sz; |
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int reserved_mrws; |
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int max_mtt_seg; |
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int max_requester_per_qp; |
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int max_responder_per_qp; |
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int max_rdma_global; |
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int local_ca_ack_delay; |
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int max_mtu; |
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int max_port_width; |
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int max_vl; |
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int num_ports; |
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int max_gids; |
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u16 stat_rate_support; |
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int max_pkeys; |
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u32 flags; |
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int reserved_uars; |
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int uar_size; |
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int min_page_sz; |
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int max_sg; |
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int max_desc_sz; |
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int max_qp_per_mcg; |
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int reserved_mgms; |
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int max_mcgs; |
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int reserved_pds; |
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int max_pds; |
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int reserved_rdds; |
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int max_rdds; |
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int eec_entry_sz; |
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int qpc_entry_sz; |
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int eeec_entry_sz; |
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int eqpc_entry_sz; |
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int eqc_entry_sz; |
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int cqc_entry_sz; |
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int srq_entry_sz; |
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int uar_scratch_entry_sz; |
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int mpt_entry_sz; |
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union { |
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struct { |
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int max_avs; |
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} tavor; |
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struct { |
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int resize_srq; |
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int max_pbl_sz; |
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u8 bmme_flags; |
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u32 reserved_lkey; |
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int lam_required; |
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u64 max_icm_sz; |
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} arbel; |
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} hca; |
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}; |
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struct mthca_adapter { |
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u32 vendor_id; |
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u32 device_id; |
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u32 revision_id; |
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char board_id[MTHCA_BOARD_ID_LEN]; |
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u8 inta_pin; |
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}; |
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struct mthca_init_hca_param { |
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u64 qpc_base; |
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u64 eec_base; |
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u64 srqc_base; |
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u64 cqc_base; |
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u64 eqpc_base; |
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u64 eeec_base; |
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u64 eqc_base; |
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u64 rdb_base; |
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u64 mc_base; |
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u64 mpt_base; |
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u64 mtt_base; |
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u64 uar_scratch_base; |
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u64 uarc_base; |
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u16 log_mc_entry_sz; |
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u16 mc_hash_sz; |
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u8 log_num_qps; |
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u8 log_num_eecs; |
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u8 log_num_srqs; |
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u8 log_num_cqs; |
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u8 log_num_eqs; |
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u8 log_mc_table_sz; |
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u8 mtt_seg_sz; |
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u8 log_mpt_sz; |
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u8 log_uar_sz; |
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u8 log_uarc_sz; |
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}; |
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struct mthca_init_ib_param { |
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int port_width; |
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int vl_cap; |
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int mtu_cap; |
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u16 gid_cap; |
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u16 pkey_cap; |
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int set_guid0; |
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u64 guid0; |
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int set_node_guid; |
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u64 node_guid; |
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int set_si_guid; |
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u64 si_guid; |
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}; |
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struct mthca_set_ib_param { |
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int set_si_guid; |
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int reset_qkey_viol; |
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u64 si_guid; |
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u32 cap_mask; |
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}; |
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int mthca_cmd_init(struct mthca_dev *dev); |
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void mthca_cmd_cleanup(struct mthca_dev *dev); |
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int mthca_cmd_use_events(struct mthca_dev *dev); |
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void mthca_cmd_use_polling(struct mthca_dev *dev); |
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void mthca_cmd_event(struct mthca_dev *dev, u16 token, |
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u8 status, u64 out_param); |
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struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, |
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gfp_t gfp_mask); |
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void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox); |
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int mthca_SYS_EN(struct mthca_dev *dev); |
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int mthca_SYS_DIS(struct mthca_dev *dev); |
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int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm); |
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int mthca_UNMAP_FA(struct mthca_dev *dev); |
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int mthca_RUN_FW(struct mthca_dev *dev); |
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int mthca_QUERY_FW(struct mthca_dev *dev); |
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int mthca_ENABLE_LAM(struct mthca_dev *dev); |
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int mthca_DISABLE_LAM(struct mthca_dev *dev); |
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int mthca_QUERY_DDR(struct mthca_dev *dev); |
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int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, |
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struct mthca_dev_lim *dev_lim); |
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int mthca_QUERY_ADAPTER(struct mthca_dev *dev, |
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struct mthca_adapter *adapter); |
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int mthca_INIT_HCA(struct mthca_dev *dev, |
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struct mthca_init_hca_param *param); |
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int mthca_INIT_IB(struct mthca_dev *dev, |
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struct mthca_init_ib_param *param, |
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int port); |
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int mthca_CLOSE_IB(struct mthca_dev *dev, int port); |
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int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic); |
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int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, |
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int port); |
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int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt); |
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int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt); |
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int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count); |
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int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm); |
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int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev); |
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int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages); |
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int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int mpt_index); |
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int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int mpt_index); |
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int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int num_mtt); |
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int mthca_SYNC_TPT(struct mthca_dev *dev); |
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int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, |
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int eq_num); |
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int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int eq_num); |
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int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int eq_num); |
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int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int cq_num); |
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int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int cq_num); |
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int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size); |
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int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int srq_num); |
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int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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int srq_num); |
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int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, |
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struct mthca_mailbox *mailbox); |
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int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit); |
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int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, |
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enum ib_qp_state next, u32 num, int is_ee, |
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struct mthca_mailbox *mailbox, u32 optmask); |
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int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, |
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struct mthca_mailbox *mailbox); |
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int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn); |
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int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, |
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int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
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const void *in_mad, void *response_mad); |
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int mthca_READ_MGM(struct mthca_dev *dev, int index, |
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struct mthca_mailbox *mailbox); |
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int mthca_WRITE_MGM(struct mthca_dev *dev, int index, |
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struct mthca_mailbox *mailbox); |
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int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
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u16 *hash); |
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int mthca_NOP(struct mthca_dev *dev); |
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#endif /* MTHCA_CMD_H */
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