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2128 lines
57 KiB
2128 lines
57 KiB
/* |
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* Copyright (c) 2016-2017 Hisilicon Limited. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef _HNS_ROCE_HW_V2_H |
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#define _HNS_ROCE_HW_V2_H |
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#include <linux/bitops.h> |
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#define HNS_ROCE_VF_QPC_BT_NUM 256 |
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#define HNS_ROCE_VF_SCCC_BT_NUM 64 |
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#define HNS_ROCE_VF_SRQC_BT_NUM 64 |
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#define HNS_ROCE_VF_CQC_BT_NUM 64 |
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#define HNS_ROCE_VF_MPT_BT_NUM 64 |
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#define HNS_ROCE_VF_EQC_NUM 64 |
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#define HNS_ROCE_VF_SMAC_NUM 32 |
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#define HNS_ROCE_VF_SGID_NUM 32 |
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#define HNS_ROCE_VF_SL_NUM 8 |
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#define HNS_ROCE_VF_GMV_BT_NUM 256 |
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#define HNS_ROCE_V2_MAX_QP_NUM 0x100000 |
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#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200 |
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#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 |
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#define HNS_ROCE_V2_MAX_SRQ 0x100000 |
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#define HNS_ROCE_V2_MAX_SRQ_WR 0x8000 |
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#define HNS_ROCE_V2_MAX_SRQ_SGE 64 |
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#define HNS_ROCE_V2_MAX_CQ_NUM 0x100000 |
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#define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100 |
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#define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000 |
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#define HNS_ROCE_V2_MAX_CQE_NUM 0x400000 |
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#define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000 |
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#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64 |
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#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64 |
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#define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 |
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#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 |
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#define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32 |
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#define HNS_ROCE_V2_UAR_NUM 256 |
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#define HNS_ROCE_V2_PHY_UAR_NUM 1 |
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#define HNS_ROCE_V2_MAX_IRQ_NUM 65 |
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#define HNS_ROCE_V2_COMP_VEC_NUM 63 |
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#define HNS_ROCE_V2_AEQE_VEC_NUM 1 |
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#define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1 |
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#define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000 |
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#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 |
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#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000 |
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#define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000 |
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#define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000 |
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#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 |
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#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 |
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#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 |
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#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 |
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#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16 |
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#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64 |
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#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64 |
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#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48 |
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#define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100 |
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#define HNS_ROCE_V2_CQC_ENTRY_SZ 64 |
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#define HNS_ROCE_V2_SRQC_ENTRY_SZ 64 |
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#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64 |
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#define HNS_ROCE_V2_MTT_ENTRY_SZ 64 |
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#define HNS_ROCE_V2_IDX_ENTRY_SZ 4 |
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#define HNS_ROCE_V2_SCCC_SZ 32 |
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#define HNS_ROCE_V3_SCCC_SZ 64 |
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#define HNS_ROCE_V3_GMV_ENTRY_SZ 32 |
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#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE |
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#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE |
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#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 |
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#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 |
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#define HNS_ROCE_INVALID_LKEY 0x0 |
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#define HNS_ROCE_INVALID_SGE_LENGTH 0x80000000 |
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#define HNS_ROCE_CMQ_TX_TIMEOUT 30000 |
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#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2 |
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#define HNS_ROCE_V2_RSV_QPS 8 |
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#define HNS_ROCE_V2_HW_RST_TIMEOUT 1000 |
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#define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100 |
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#define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20 |
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#define HNS_ROCE_CONTEXT_HOP_NUM 1 |
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#define HNS_ROCE_SCCC_HOP_NUM 1 |
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#define HNS_ROCE_MTT_HOP_NUM 1 |
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#define HNS_ROCE_CQE_HOP_NUM 1 |
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#define HNS_ROCE_SRQWQE_HOP_NUM 1 |
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#define HNS_ROCE_PBL_HOP_NUM 2 |
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#define HNS_ROCE_EQE_HOP_NUM 2 |
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#define HNS_ROCE_IDX_HOP_NUM 1 |
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#define HNS_ROCE_SQWQE_HOP_NUM 2 |
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#define HNS_ROCE_EXT_SGE_HOP_NUM 1 |
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#define HNS_ROCE_RQWQE_HOP_NUM 2 |
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#define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6 |
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#define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2 |
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#define HNS_ROCE_V2_GID_INDEX_NUM 256 |
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#define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18) |
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#define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0 |
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#define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1 |
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#define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2 |
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#define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3 |
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#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4 |
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#define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5 |
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#define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) |
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#define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) |
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#define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) |
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#define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) |
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#define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) |
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#define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) |
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#define HNS_ROCE_CMQ_DESC_NUM_S 3 |
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#define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5 |
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#define check_whether_last_step(hop_num, step_idx) \ |
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((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \ |
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(step_idx == 1 && hop_num == 1) || \ |
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(step_idx == 2 && hop_num == 2)) |
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#define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0 |
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#define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT) |
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#define CMD_CSQ_DESC_NUM 1024 |
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#define CMD_CRQ_DESC_NUM 1024 |
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enum { |
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NO_ARMED = 0x0, |
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REG_NXT_CEQE = 0x2, |
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REG_NXT_SE_CEQE = 0x3 |
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}; |
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#define V2_CQ_DB_REQ_NOT_SOL 0 |
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#define V2_CQ_DB_REQ_NOT 1 |
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#define V2_CQ_STATE_VALID 1 |
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#define V2_QKEY_VAL 0x80010000 |
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#define GID_LEN_V2 16 |
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#define HNS_ROCE_V2_CQE_QPN_MASK 0xfffff |
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enum { |
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HNS_ROCE_V2_WQE_OP_SEND = 0x0, |
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HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1, |
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HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2, |
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HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3, |
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HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4, |
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HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5, |
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HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6, |
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HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7, |
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HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8, |
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HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9, |
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HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa, |
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HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb, |
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HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc, |
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HNS_ROCE_V2_WQE_OP_MASK = 0x1f, |
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}; |
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enum { |
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/* rq operations */ |
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HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0, |
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HNS_ROCE_V2_OPCODE_SEND = 0x1, |
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HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2, |
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HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3, |
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}; |
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enum { |
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HNS_ROCE_V2_SQ_DB = 0x0, |
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HNS_ROCE_V2_RQ_DB = 0x1, |
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HNS_ROCE_V2_SRQ_DB = 0x2, |
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HNS_ROCE_V2_CQ_DB_PTR = 0x3, |
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HNS_ROCE_V2_CQ_DB_NTR = 0x4, |
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}; |
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enum { |
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HNS_ROCE_CQE_V2_SUCCESS = 0x00, |
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HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01, |
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HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02, |
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HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04, |
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HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05, |
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HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06, |
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HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10, |
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HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11, |
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HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12, |
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HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13, |
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HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14, |
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HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15, |
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HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16, |
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HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22, |
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HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23, |
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HNS_ROCE_V2_CQE_STATUS_MASK = 0xff, |
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}; |
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/* CMQ command */ |
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enum hns_roce_opcode_type { |
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HNS_QUERY_FW_VER = 0x0001, |
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HNS_ROCE_OPC_QUERY_HW_VER = 0x8000, |
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HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001, |
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HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004, |
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HNS_ROCE_OPC_QUERY_PF_RES = 0x8400, |
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HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401, |
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HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403, |
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HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404, |
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HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406, |
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HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408, |
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HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409, |
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HNS_ROCE_OPC_CFG_SGID_TB = 0x8500, |
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HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501, |
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HNS_ROCE_OPC_POST_MB = 0x8504, |
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HNS_ROCE_OPC_QUERY_MB_ST = 0x8505, |
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HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, |
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HNS_ROCE_OPC_FUNC_CLEAR = 0x8508, |
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HNS_ROCE_OPC_CLR_SCCC = 0x8509, |
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HNS_ROCE_OPC_QUERY_SCCC = 0x850a, |
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HNS_ROCE_OPC_RESET_SCCC = 0x850b, |
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HNS_ROCE_OPC_CFG_GMV_TBL = 0x850f, |
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HNS_ROCE_OPC_CFG_GMV_BT = 0x8510, |
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HNS_SWITCH_PARAMETER_CFG = 0x1033, |
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}; |
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enum { |
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TYPE_CRQ, |
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TYPE_CSQ, |
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}; |
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enum hns_roce_cmd_return_status { |
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CMD_EXEC_SUCCESS = 0, |
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CMD_NO_AUTH = 1, |
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CMD_NOT_EXEC = 2, |
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CMD_QUEUE_FULL = 3, |
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}; |
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enum hns_roce_sgid_type { |
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GID_TYPE_FLAG_ROCE_V1 = 0, |
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GID_TYPE_FLAG_ROCE_V2_IPV4, |
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GID_TYPE_FLAG_ROCE_V2_IPV6, |
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}; |
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struct hns_roce_v2_cq_context { |
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__le32 byte_4_pg_ceqn; |
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__le32 byte_8_cqn; |
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__le32 cqe_cur_blk_addr; |
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__le32 byte_16_hop_addr; |
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__le32 cqe_nxt_blk_addr; |
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__le32 byte_24_pgsz_addr; |
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__le32 byte_28_cq_pi; |
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__le32 byte_32_cq_ci; |
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__le32 cqe_ba; |
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__le32 byte_40_cqe_ba; |
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__le32 byte_44_db_record; |
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__le32 db_record_addr; |
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__le32 byte_52_cqe_cnt; |
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__le32 byte_56_cqe_period_maxcnt; |
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__le32 cqe_report_timer; |
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__le32 byte_64_se_cqe_idx; |
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}; |
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#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0 |
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#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0 |
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#define V2_CQC_BYTE_4_CQ_ST_S 0 |
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#define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0) |
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#define V2_CQC_BYTE_4_POLL_S 2 |
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#define V2_CQC_BYTE_4_SE_S 3 |
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#define V2_CQC_BYTE_4_OVER_IGNORE_S 4 |
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#define V2_CQC_BYTE_4_COALESCE_S 5 |
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#define V2_CQC_BYTE_4_ARM_ST_S 6 |
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#define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6) |
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#define V2_CQC_BYTE_4_SHIFT_S 8 |
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#define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8) |
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#define V2_CQC_BYTE_4_CMD_SN_S 13 |
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#define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13) |
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#define V2_CQC_BYTE_4_CEQN_S 15 |
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#define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15) |
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#define V2_CQC_BYTE_4_PAGE_OFFSET_S 24 |
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#define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24) |
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#define V2_CQC_BYTE_8_CQN_S 0 |
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#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0) |
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#define V2_CQC_BYTE_8_CQE_SIZE_S 27 |
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#define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27) |
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#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0 |
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#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0) |
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#define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30 |
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#define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30) |
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#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0 |
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#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0) |
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#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24 |
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#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24) |
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#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28 |
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#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28) |
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#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0 |
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#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0) |
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#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0 |
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#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0) |
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#define V2_CQC_BYTE_40_CQE_BA_S 0 |
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#define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0) |
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#define V2_CQC_BYTE_44_DB_RECORD_EN_S 0 |
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#define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1 |
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#define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1) |
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#define V2_CQC_BYTE_52_CQE_CNT_S 0 |
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#define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0) |
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#define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0 |
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#define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0) |
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#define V2_CQC_BYTE_56_CQ_PERIOD_S 16 |
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#define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16) |
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#define V2_CQC_BYTE_64_SE_CQE_IDX_S 0 |
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#define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0) |
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#define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l) |
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#define CQC_STASH CQC_FIELD_LOC(63, 63) |
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struct hns_roce_srq_context { |
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__le32 byte_4_srqn_srqst; |
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__le32 byte_8_limit_wl; |
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__le32 byte_12_xrcd; |
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__le32 byte_16_pi_ci; |
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__le32 wqe_bt_ba; |
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__le32 byte_24_wqe_bt_ba; |
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__le32 byte_28_rqws_pd; |
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__le32 idx_bt_ba; |
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__le32 rsv_idx_bt_ba; |
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__le32 idx_cur_blk_addr; |
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__le32 byte_44_idxbufpgsz_addr; |
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__le32 idx_nxt_blk_addr; |
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__le32 rsv_idxnxtblkaddr; |
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__le32 byte_56_xrc_cqn; |
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__le32 db_record_addr_record_en; |
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__le32 db_record_addr; |
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}; |
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|
|
#define SRQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_srq_context, h, l) |
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#define SRQC_SRQ_ST SRQC_FIELD_LOC(1, 0) |
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#define SRQC_WQE_HOP_NUM SRQC_FIELD_LOC(3, 2) |
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#define SRQC_SHIFT SRQC_FIELD_LOC(7, 4) |
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#define SRQC_SRQN SRQC_FIELD_LOC(31, 8) |
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#define SRQC_LIMIT_WL SRQC_FIELD_LOC(47, 32) |
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#define SRQC_RSV0 SRQC_FIELD_LOC(63, 48) |
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#define SRQC_XRCD SRQC_FIELD_LOC(87, 64) |
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#define SRQC_RSV1 SRQC_FIELD_LOC(95, 88) |
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#define SRQC_PRODUCER_IDX SRQC_FIELD_LOC(111, 96) |
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#define SRQC_CONSUMER_IDX SRQC_FIELD_LOC(127, 112) |
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#define SRQC_WQE_BT_BA_L SRQC_FIELD_LOC(159, 128) |
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#define SRQC_WQE_BT_BA_H SRQC_FIELD_LOC(188, 160) |
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#define SRQC_RSV2 SRQC_FIELD_LOC(191, 189) |
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#define SRQC_PD SRQC_FIELD_LOC(215, 192) |
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#define SRQC_RQWS SRQC_FIELD_LOC(219, 216) |
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#define SRQC_RSV3 SRQC_FIELD_LOC(223, 220) |
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#define SRQC_IDX_BT_BA_L SRQC_FIELD_LOC(255, 224) |
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#define SRQC_IDX_BT_BA_H SRQC_FIELD_LOC(284, 256) |
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#define SRQC_RSV4 SRQC_FIELD_LOC(287, 285) |
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#define SRQC_IDX_CUR_BLK_ADDR_L SRQC_FIELD_LOC(319, 288) |
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#define SRQC_IDX_CUR_BLK_ADDR_H SRQC_FIELD_LOC(339, 320) |
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#define SRQC_RSV5 SRQC_FIELD_LOC(341, 340) |
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#define SRQC_IDX_HOP_NUM SRQC_FIELD_LOC(343, 342) |
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#define SRQC_IDX_BA_PG_SZ SRQC_FIELD_LOC(347, 344) |
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#define SRQC_IDX_BUF_PG_SZ SRQC_FIELD_LOC(351, 348) |
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#define SRQC_IDX_NXT_BLK_ADDR_L SRQC_FIELD_LOC(383, 352) |
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#define SRQC_IDX_NXT_BLK_ADDR_H SRQC_FIELD_LOC(403, 384) |
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#define SRQC_RSV6 SRQC_FIELD_LOC(415, 404) |
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#define SRQC_XRC_CQN SRQC_FIELD_LOC(439, 416) |
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#define SRQC_WQE_BA_PG_SZ SRQC_FIELD_LOC(443, 440) |
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#define SRQC_WQE_BUF_PG_SZ SRQC_FIELD_LOC(447, 444) |
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#define SRQC_DB_RECORD_EN SRQC_FIELD_LOC(448, 448) |
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#define SRQC_DB_RECORD_ADDR_L SRQC_FIELD_LOC(479, 449) |
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#define SRQC_DB_RECORD_ADDR_H SRQC_FIELD_LOC(511, 480) |
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|
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#define SRQC_BYTE_4_SRQ_ST_S 0 |
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#define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0) |
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#define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2 |
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#define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2) |
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|
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#define SRQC_BYTE_4_SRQ_SHIFT_S 4 |
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#define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4) |
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|
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#define SRQC_BYTE_4_SRQN_S 8 |
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#define SRQC_BYTE_4_SRQN_M GENMASK(31, 8) |
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|
#define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0 |
|
#define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0) |
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|
|
#define SRQC_BYTE_12_SRQ_XRCD_S 0 |
|
#define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0) |
|
|
|
#define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0 |
|
#define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0) |
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|
#define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0 |
|
#define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16) |
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|
|
#define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0 |
|
#define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0) |
|
|
|
#define SRQC_BYTE_28_PD_S 0 |
|
#define SRQC_BYTE_28_PD_M GENMASK(23, 0) |
|
|
|
#define SRQC_BYTE_28_RQWS_S 24 |
|
#define SRQC_BYTE_28_RQWS_M GENMASK(27, 24) |
|
|
|
#define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0 |
|
#define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0) |
|
|
|
#define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0 |
|
#define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0) |
|
|
|
#define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22 |
|
#define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22) |
|
|
|
#define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24 |
|
#define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24) |
|
|
|
#define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28 |
|
#define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28) |
|
|
|
#define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0 |
|
#define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0) |
|
|
|
#define SRQC_BYTE_56_SRQ_XRC_CQN_S 0 |
|
#define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0) |
|
|
|
#define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24 |
|
#define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24) |
|
|
|
#define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28 |
|
#define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28) |
|
|
|
#define SRQC_BYTE_60_SRQ_RECORD_EN_S 0 |
|
|
|
#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1 |
|
#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1) |
|
|
|
enum { |
|
V2_MPT_ST_VALID = 0x1, |
|
V2_MPT_ST_FREE = 0x2, |
|
}; |
|
|
|
enum hns_roce_v2_qp_state { |
|
HNS_ROCE_QP_ST_RST, |
|
HNS_ROCE_QP_ST_INIT, |
|
HNS_ROCE_QP_ST_RTR, |
|
HNS_ROCE_QP_ST_RTS, |
|
HNS_ROCE_QP_ST_SQD, |
|
HNS_ROCE_QP_ST_SQER, |
|
HNS_ROCE_QP_ST_ERR, |
|
HNS_ROCE_QP_ST_SQ_DRAINING, |
|
HNS_ROCE_QP_NUM_ST |
|
}; |
|
|
|
struct hns_roce_v2_qp_context_ex { |
|
__le32 data[64]; |
|
}; |
|
struct hns_roce_v2_qp_context { |
|
__le32 byte_4_sqpn_tst; |
|
__le32 wqe_sge_ba; |
|
__le32 byte_12_sq_hop; |
|
__le32 byte_16_buf_ba_pg_sz; |
|
__le32 byte_20_smac_sgid_idx; |
|
__le32 byte_24_mtu_tc; |
|
__le32 byte_28_at_fl; |
|
u8 dgid[GID_LEN_V2]; |
|
__le32 dmac; |
|
__le32 byte_52_udpspn_dmac; |
|
__le32 byte_56_dqpn_err; |
|
__le32 byte_60_qpst_tempid; |
|
__le32 qkey_xrcd; |
|
__le32 byte_68_rq_db; |
|
__le32 rq_db_record_addr; |
|
__le32 byte_76_srqn_op_en; |
|
__le32 byte_80_rnr_rx_cqn; |
|
__le32 byte_84_rq_ci_pi; |
|
__le32 rq_cur_blk_addr; |
|
__le32 byte_92_srq_info; |
|
__le32 byte_96_rx_reqmsn; |
|
__le32 rq_nxt_blk_addr; |
|
__le32 byte_104_rq_sge; |
|
__le32 byte_108_rx_reqepsn; |
|
__le32 rq_rnr_timer; |
|
__le32 rx_msg_len; |
|
__le32 rx_rkey_pkt_info; |
|
__le64 rx_va; |
|
__le32 byte_132_trrl; |
|
__le32 trrl_ba; |
|
__le32 byte_140_raq; |
|
__le32 byte_144_raq; |
|
__le32 byte_148_raq; |
|
__le32 byte_152_raq; |
|
__le32 byte_156_raq; |
|
__le32 byte_160_sq_ci_pi; |
|
__le32 sq_cur_blk_addr; |
|
__le32 byte_168_irrl_idx; |
|
__le32 byte_172_sq_psn; |
|
__le32 byte_176_msg_pktn; |
|
__le32 sq_cur_sge_blk_addr; |
|
__le32 byte_184_irrl_idx; |
|
__le32 cur_sge_offset; |
|
__le32 byte_192_ext_sge; |
|
__le32 byte_196_sq_psn; |
|
__le32 byte_200_sq_max; |
|
__le32 irrl_ba; |
|
__le32 byte_208_irrl; |
|
__le32 byte_212_lsn; |
|
__le32 sq_timer; |
|
__le32 byte_220_retry_psn_msn; |
|
__le32 byte_224_retry_msg; |
|
__le32 rx_sq_cur_blk_addr; |
|
__le32 byte_232_irrl_sge; |
|
__le32 irrl_cur_sge_offset; |
|
__le32 byte_240_irrl_tail; |
|
__le32 byte_244_rnr_rxack; |
|
__le32 byte_248_ack_psn; |
|
__le32 byte_252_err_txcqn; |
|
__le32 byte_256_sqflush_rqcqe; |
|
|
|
struct hns_roce_v2_qp_context_ex ext; |
|
}; |
|
|
|
#define V2_QPC_BYTE_4_TST_S 0 |
|
#define V2_QPC_BYTE_4_TST_M GENMASK(2, 0) |
|
|
|
#define V2_QPC_BYTE_4_SGE_SHIFT_S 3 |
|
#define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3) |
|
|
|
#define V2_QPC_BYTE_4_SQPN_S 8 |
|
#define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8) |
|
|
|
#define V2_QPC_BYTE_12_WQE_SGE_BA_S 0 |
|
#define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0) |
|
|
|
#define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29 |
|
#define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29) |
|
|
|
#define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31 |
|
|
|
#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0 |
|
#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0) |
|
|
|
#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4 |
|
#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4) |
|
|
|
#define V2_QPC_BYTE_16_PD_S 8 |
|
#define V2_QPC_BYTE_16_PD_M GENMASK(31, 8) |
|
|
|
#define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0 |
|
#define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0) |
|
|
|
#define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2 |
|
#define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2) |
|
|
|
#define V2_QPC_BYTE_20_RQWS_S 4 |
|
#define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4) |
|
|
|
#define V2_QPC_BYTE_20_SQ_SHIFT_S 8 |
|
#define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8) |
|
|
|
#define V2_QPC_BYTE_20_RQ_SHIFT_S 12 |
|
#define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12) |
|
|
|
#define V2_QPC_BYTE_20_SGID_IDX_S 16 |
|
#define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16) |
|
|
|
#define V2_QPC_BYTE_20_SMAC_IDX_S 24 |
|
#define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24) |
|
|
|
#define V2_QPC_BYTE_24_HOP_LIMIT_S 0 |
|
#define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0) |
|
|
|
#define V2_QPC_BYTE_24_TC_S 8 |
|
#define V2_QPC_BYTE_24_TC_M GENMASK(15, 8) |
|
|
|
#define V2_QPC_BYTE_24_VLAN_ID_S 16 |
|
#define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16) |
|
|
|
#define V2_QPC_BYTE_24_MTU_S 28 |
|
#define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28) |
|
|
|
#define V2_QPC_BYTE_28_FL_S 0 |
|
#define V2_QPC_BYTE_28_FL_M GENMASK(19, 0) |
|
|
|
#define V2_QPC_BYTE_28_SL_S 20 |
|
#define V2_QPC_BYTE_28_SL_M GENMASK(23, 20) |
|
|
|
#define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24 |
|
|
|
#define V2_QPC_BYTE_28_CE_FLAG_S 25 |
|
|
|
#define V2_QPC_BYTE_28_LBI_S 26 |
|
|
|
#define V2_QPC_BYTE_28_AT_S 27 |
|
#define V2_QPC_BYTE_28_AT_M GENMASK(31, 27) |
|
|
|
#define V2_QPC_BYTE_52_DMAC_S 0 |
|
#define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0) |
|
|
|
#define V2_QPC_BYTE_52_UDPSPN_S 16 |
|
#define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16) |
|
|
|
#define V2_QPC_BYTE_56_DQPN_S 0 |
|
#define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_56_SQ_TX_ERR_S 24 |
|
#define V2_QPC_BYTE_56_SQ_RX_ERR_S 25 |
|
#define V2_QPC_BYTE_56_RQ_TX_ERR_S 26 |
|
#define V2_QPC_BYTE_56_RQ_RX_ERR_S 27 |
|
|
|
#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28 |
|
#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28) |
|
|
|
#define V2_QPC_BYTE_60_TEMPID_S 0 |
|
#define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0) |
|
|
|
#define V2_QPC_BYTE_60_SCC_TOKEN_S 8 |
|
#define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8) |
|
|
|
#define V2_QPC_BYTE_60_SQ_DB_DOING_S 27 |
|
|
|
#define V2_QPC_BYTE_60_RQ_DB_DOING_S 28 |
|
|
|
#define V2_QPC_BYTE_60_QP_ST_S 29 |
|
#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29) |
|
|
|
#define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0 |
|
|
|
#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1 |
|
#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1) |
|
|
|
#define V2_QPC_BYTE_76_SRQN_S 0 |
|
#define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_76_SRQ_EN_S 24 |
|
|
|
#define V2_QPC_BYTE_76_RRE_S 25 |
|
|
|
#define V2_QPC_BYTE_76_RWE_S 26 |
|
|
|
#define V2_QPC_BYTE_76_ATE_S 27 |
|
|
|
#define V2_QPC_BYTE_76_RQIE_S 28 |
|
#define V2_QPC_BYTE_76_EXT_ATE_S 29 |
|
#define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30 |
|
#define V2_QPC_BYTE_80_RX_CQN_S 0 |
|
#define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27 |
|
#define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27) |
|
|
|
#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0 |
|
#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0) |
|
|
|
#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16 |
|
#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16) |
|
|
|
#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0 |
|
#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0) |
|
|
|
#define V2_QPC_BYTE_92_SRQ_INFO_S 20 |
|
#define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20) |
|
|
|
#define V2_QPC_BYTE_96_RX_REQ_MSN_S 0 |
|
#define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0 |
|
#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0) |
|
|
|
#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24 |
|
#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24) |
|
|
|
#define V2_QPC_BYTE_108_INV_CREDIT_S 0 |
|
|
|
#define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3 |
|
|
|
#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4 |
|
#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4) |
|
|
|
#define V2_QPC_BYTE_108_RX_REQ_RNR_S 7 |
|
|
|
#define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8 |
|
#define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8) |
|
|
|
#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0 |
|
#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0) |
|
|
|
#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8 |
|
#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8) |
|
|
|
#define V2_QPC_BYTE_132_TRRL_BA_S 16 |
|
#define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16) |
|
|
|
#define V2_QPC_BYTE_140_TRRL_BA_S 0 |
|
#define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0) |
|
|
|
#define V2_QPC_BYTE_140_RR_MAX_S 12 |
|
#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12) |
|
|
|
#define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15 |
|
|
|
#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16 |
|
#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16) |
|
|
|
#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24 |
|
#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24) |
|
|
|
#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0 |
|
#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25 |
|
#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25) |
|
|
|
#define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31 |
|
|
|
#define V2_QPC_BYTE_148_RQ_MSN_S 0 |
|
#define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24 |
|
#define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24) |
|
|
|
#define V2_QPC_BYTE_152_RAQ_PSN_S 0 |
|
#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0) |
|
|
|
#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24 |
|
#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24) |
|
|
|
#define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0 |
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#define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0 |
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#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0) |
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#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16 |
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#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16) |
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#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0 |
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#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) |
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#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 |
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#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21 |
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#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22 |
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#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22) |
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#define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24 |
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#define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25 |
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#define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26 |
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#define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27 |
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#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28 |
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#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28) |
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#define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0 |
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#define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0) |
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#define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6 |
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#define V2_QPC_BYTE_172_FRE_S 7 |
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#define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8 |
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#define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8) |
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#define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0 |
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#define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24 |
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#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24) |
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#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0 |
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#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0) |
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#define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20 |
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#define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20) |
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#define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0 |
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#define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24 |
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#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24) |
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#define V2_QPC_BYTE_196_IRRL_HEAD_S 0 |
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#define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0) |
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#define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8 |
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#define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8) |
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#define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0 |
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#define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0) |
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#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16 |
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#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16) |
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#define V2_QPC_BYTE_208_IRRL_BA_S 0 |
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#define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0) |
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#define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26 |
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#define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27 |
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#define V2_QPC_BYTE_208_RMT_E2E_S 28 |
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#define V2_QPC_BYTE_208_SR_MAX_S 29 |
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#define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29) |
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#define V2_QPC_BYTE_212_LSN_S 0 |
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#define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24 |
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#define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24) |
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#define V2_QPC_BYTE_212_CHECK_FLG_S 27 |
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#define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27) |
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#define V2_QPC_BYTE_212_RETRY_CNT_S 29 |
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#define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29) |
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#define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0 |
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#define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0) |
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#define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16 |
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#define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16) |
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#define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0 |
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#define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0) |
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#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8 |
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#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8) |
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#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0 |
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#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) |
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#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20 |
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#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20) |
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#define V2_QPC_BYTE_232_SO_LP_VLD_S 29 |
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#define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30 |
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#define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31 |
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#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0 |
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#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0) |
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#define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8 |
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#define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8) |
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#define V2_QPC_BYTE_240_RX_ACK_MSN_S 16 |
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#define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16) |
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#define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0 |
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#define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24 |
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#define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24) |
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#define V2_QPC_BYTE_244_RNR_CNT_S 27 |
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#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27) |
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#define V2_QPC_BYTE_244_LCL_OP_FLG_S 30 |
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#define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31 |
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#define V2_QPC_BYTE_248_IRRL_PSN_S 0 |
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#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24 |
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#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25 |
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#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25) |
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#define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27 |
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#define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28 |
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#define V2_QPC_BYTE_248_CQ_ERR_IND_S 31 |
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#define V2_QPC_BYTE_252_TX_CQN_S 0 |
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#define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0) |
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#define V2_QPC_BYTE_252_SIG_TYPE_S 24 |
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#define V2_QPC_BYTE_252_ERR_TYPE_S 25 |
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#define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25) |
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#define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0 |
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#define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0) |
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#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16 |
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#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16) |
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#define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l) |
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#define QPCEX_STASH QPCEX_FIELD_LOC(82, 82) |
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#define V2_QP_RWE_S 1 /* rdma write enable */ |
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#define V2_QP_RRE_S 2 /* rdma read enable */ |
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#define V2_QP_ATE_S 3 /* rdma atomic enable */ |
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struct hns_roce_v2_cqe { |
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__le32 byte_4; |
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union { |
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__le32 rkey; |
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__le32 immtdata; |
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}; |
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__le32 byte_12; |
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__le32 byte_16; |
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__le32 byte_cnt; |
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u8 smac[4]; |
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__le32 byte_28; |
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__le32 byte_32; |
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__le32 rsv[8]; |
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}; |
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#define V2_CQE_BYTE_4_OPCODE_S 0 |
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#define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0) |
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#define V2_CQE_BYTE_4_RQ_INLINE_S 5 |
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#define V2_CQE_BYTE_4_S_R_S 6 |
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#define V2_CQE_BYTE_4_OWNER_S 7 |
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#define V2_CQE_BYTE_4_STATUS_S 8 |
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#define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8) |
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#define V2_CQE_BYTE_4_WQE_INDX_S 16 |
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#define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16) |
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#define V2_CQE_BYTE_12_XRC_SRQN_S 0 |
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#define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0) |
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#define V2_CQE_BYTE_16_LCL_QPN_S 0 |
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#define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0) |
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#define V2_CQE_BYTE_16_SUB_STATUS_S 24 |
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#define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24) |
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#define V2_CQE_BYTE_28_SMAC_4_S 0 |
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#define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0) |
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#define V2_CQE_BYTE_28_SMAC_5_S 8 |
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#define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8) |
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#define V2_CQE_BYTE_28_PORT_TYPE_S 16 |
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#define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16) |
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#define V2_CQE_BYTE_28_VID_S 18 |
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#define V2_CQE_BYTE_28_VID_M GENMASK(29, 18) |
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#define V2_CQE_BYTE_28_VID_VLD_S 30 |
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#define V2_CQE_BYTE_32_RMT_QPN_S 0 |
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#define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0) |
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#define V2_CQE_BYTE_32_SL_S 24 |
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#define V2_CQE_BYTE_32_SL_M GENMASK(26, 24) |
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#define V2_CQE_BYTE_32_PORTN_S 27 |
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#define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27) |
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#define V2_CQE_BYTE_32_GRH_S 30 |
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#define V2_CQE_BYTE_32_LPK_S 31 |
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struct hns_roce_v2_mpt_entry { |
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__le32 byte_4_pd_hop_st; |
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__le32 byte_8_mw_cnt_en; |
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__le32 byte_12_mw_pa; |
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__le32 bound_lkey; |
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__le32 len_l; |
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__le32 len_h; |
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__le32 lkey; |
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__le32 va_l; |
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__le32 va_h; |
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__le32 pbl_size; |
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__le32 pbl_ba_l; |
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__le32 byte_48_mode_ba; |
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__le32 pa0_l; |
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__le32 byte_56_pa0_h; |
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__le32 pa1_l; |
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__le32 byte_64_buf_pa1; |
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}; |
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#define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l) |
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#define MPT_ST MPT_FIELD_LOC(1, 0) |
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#define MPT_PBL_HOP_NUM MPT_FIELD_LOC(3, 2) |
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#define MPT_PBL_BA_PG_SZ MPT_FIELD_LOC(7, 4) |
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#define MPT_PD MPT_FIELD_LOC(31, 8) |
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#define MPT_RA_EN MPT_FIELD_LOC(32, 32) |
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#define MPT_R_INV_EN MPT_FIELD_LOC(33, 33) |
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#define MPT_L_INV_EN MPT_FIELD_LOC(34, 34) |
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#define MPT_BIND_EN MPT_FIELD_LOC(35, 35) |
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#define MPT_ATOMIC_EN MPT_FIELD_LOC(36, 36) |
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#define MPT_RR_EN MPT_FIELD_LOC(37, 37) |
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#define MPT_RW_EN MPT_FIELD_LOC(38, 38) |
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#define MPT_LW_EN MPT_FIELD_LOC(39, 39) |
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#define MPT_MW_CNT MPT_FIELD_LOC(63, 40) |
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#define MPT_FRE MPT_FIELD_LOC(64, 64) |
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#define MPT_PA MPT_FIELD_LOC(65, 65) |
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#define MPT_ZBVA MPT_FIELD_LOC(66, 66) |
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#define MPT_SHARE MPT_FIELD_LOC(67, 67) |
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#define MPT_MR_MW MPT_FIELD_LOC(68, 68) |
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#define MPT_BPD MPT_FIELD_LOC(69, 69) |
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#define MPT_BQP MPT_FIELD_LOC(70, 70) |
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#define MPT_INNER_PA_VLD MPT_FIELD_LOC(71, 71) |
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#define MPT_MW_BIND_QPN MPT_FIELD_LOC(95, 72) |
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#define MPT_BOUND_LKEY MPT_FIELD_LOC(127, 96) |
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#define MPT_LEN MPT_FIELD_LOC(191, 128) |
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#define MPT_LKEY MPT_FIELD_LOC(223, 192) |
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#define MPT_VA MPT_FIELD_LOC(287, 224) |
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#define MPT_PBL_SIZE MPT_FIELD_LOC(319, 288) |
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#define MPT_PBL_BA MPT_FIELD_LOC(380, 320) |
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#define MPT_BLK_MODE MPT_FIELD_LOC(381, 381) |
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#define MPT_RSV0 MPT_FIELD_LOC(383, 382) |
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#define MPT_PA0 MPT_FIELD_LOC(441, 384) |
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#define MPT_BOUND_VA MPT_FIELD_LOC(447, 442) |
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#define MPT_PA1 MPT_FIELD_LOC(505, 448) |
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#define MPT_PERSIST_EN MPT_FIELD_LOC(506, 506) |
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#define MPT_RSV2 MPT_FIELD_LOC(507, 507) |
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#define MPT_PBL_BUF_PG_SZ MPT_FIELD_LOC(511, 508) |
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#define V2_MPT_BYTE_4_MPT_ST_S 0 |
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#define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0) |
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#define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2 |
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#define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2) |
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#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4 |
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#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4) |
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#define V2_MPT_BYTE_4_PD_S 8 |
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#define V2_MPT_BYTE_4_PD_M GENMASK(31, 8) |
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#define V2_MPT_BYTE_8_RA_EN_S 0 |
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#define V2_MPT_BYTE_8_R_INV_EN_S 1 |
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#define V2_MPT_BYTE_8_L_INV_EN_S 2 |
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#define V2_MPT_BYTE_8_BIND_EN_S 3 |
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#define V2_MPT_BYTE_8_ATOMIC_EN_S 4 |
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#define V2_MPT_BYTE_8_RR_EN_S 5 |
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#define V2_MPT_BYTE_8_RW_EN_S 6 |
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#define V2_MPT_BYTE_8_LW_EN_S 7 |
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#define V2_MPT_BYTE_8_MW_CNT_S 8 |
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#define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8) |
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#define V2_MPT_BYTE_12_FRE_S 0 |
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#define V2_MPT_BYTE_12_PA_S 1 |
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#define V2_MPT_BYTE_12_MR_MW_S 4 |
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#define V2_MPT_BYTE_12_BPD_S 5 |
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#define V2_MPT_BYTE_12_BQP_S 6 |
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#define V2_MPT_BYTE_12_INNER_PA_VLD_S 7 |
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#define V2_MPT_BYTE_12_MW_BIND_QPN_S 8 |
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#define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8) |
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#define V2_MPT_BYTE_48_PBL_BA_H_S 0 |
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#define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0) |
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#define V2_MPT_BYTE_48_BLK_MODE_S 29 |
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#define V2_MPT_BYTE_56_PA0_H_S 0 |
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#define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0) |
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#define V2_MPT_BYTE_64_PA1_H_S 0 |
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#define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0) |
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#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28 |
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#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28) |
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#define V2_DB_BYTE_4_TAG_S 0 |
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#define V2_DB_BYTE_4_TAG_M GENMASK(23, 0) |
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#define V2_DB_BYTE_4_CMD_S 24 |
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#define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) |
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#define V2_DB_FLAG_S 31 |
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#define V2_DB_PARAMETER_IDX_S 0 |
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#define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) |
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#define V2_DB_PARAMETER_SL_S 16 |
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#define V2_DB_PARAMETER_SL_M GENMASK(18, 16) |
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#define V2_CQ_DB_BYTE_4_TAG_S 0 |
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#define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0) |
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#define V2_CQ_DB_BYTE_4_CMD_S 24 |
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#define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24) |
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#define V2_CQ_DB_PARAMETER_CONS_IDX_S 0 |
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#define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0) |
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#define V2_CQ_DB_PARAMETER_CMD_SN_S 25 |
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#define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25) |
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#define V2_CQ_DB_PARAMETER_NOTIFY_S 24 |
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struct hns_roce_v2_ud_send_wqe { |
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__le32 byte_4; |
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__le32 msg_len; |
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__le32 immtdata; |
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__le32 byte_16; |
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__le32 byte_20; |
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__le32 byte_24; |
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__le32 qkey; |
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__le32 byte_32; |
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__le32 byte_36; |
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__le32 byte_40; |
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u8 dmac[ETH_ALEN]; |
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u8 sgid_index; |
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u8 smac_index; |
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u8 dgid[GID_LEN_V2]; |
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}; |
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#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0 |
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#define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) |
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#define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7 |
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#define V2_UD_SEND_WQE_BYTE_4_CQE_S 8 |
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#define V2_UD_SEND_WQE_BYTE_4_SE_S 11 |
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#define V2_UD_SEND_WQE_BYTE_16_PD_S 0 |
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#define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0) |
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#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24 |
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#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) |
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#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 |
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#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) |
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#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16 |
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#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16) |
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#define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0 |
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#define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0) |
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#define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0 |
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#define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0) |
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#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16 |
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#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16) |
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#define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24 |
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#define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24) |
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#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0 |
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#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0) |
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#define V2_UD_SEND_WQE_BYTE_40_SL_S 20 |
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#define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20) |
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#define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30 |
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#define V2_UD_SEND_WQE_BYTE_40_LBI_S 31 |
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struct hns_roce_v2_rc_send_wqe { |
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__le32 byte_4; |
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__le32 msg_len; |
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union { |
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__le32 inv_key; |
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__le32 immtdata; |
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}; |
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__le32 byte_16; |
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__le32 byte_20; |
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__le32 rkey; |
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__le64 va; |
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}; |
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#define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 |
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#define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) |
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#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5 |
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#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5) |
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#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13 |
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#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13) |
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#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15 |
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#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15) |
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#define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 |
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#define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 |
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#define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9 |
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#define V2_RC_SEND_WQE_BYTE_4_SO_S 10 |
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#define V2_RC_SEND_WQE_BYTE_4_SE_S 11 |
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#define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 |
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#define V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S 10 |
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#define V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S 11 |
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#define V2_RC_FRMR_WQE_BYTE_40_RR_S 12 |
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#define V2_RC_FRMR_WQE_BYTE_40_RW_S 13 |
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#define V2_RC_FRMR_WQE_BYTE_40_LW_S 14 |
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#define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 |
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#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 |
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#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) |
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#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24 |
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#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) |
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#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 |
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#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) |
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#define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31 |
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struct hns_roce_wqe_frmr_seg { |
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__le32 pbl_size; |
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__le32 byte_40; |
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}; |
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#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4 |
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#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4) |
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#define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8 |
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struct hns_roce_v2_wqe_data_seg { |
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__le32 len; |
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__le32 lkey; |
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__le64 addr; |
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}; |
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struct hns_roce_v2_db { |
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__le32 byte_4; |
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__le32 parameter; |
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}; |
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struct hns_roce_query_version { |
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__le16 rocee_vendor_id; |
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__le16 rocee_hw_version; |
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__le32 rsv[5]; |
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}; |
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struct hns_roce_query_fw_info { |
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__le32 fw_ver; |
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__le32 rsv[5]; |
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}; |
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struct hns_roce_func_clear { |
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__le32 rst_funcid_en; |
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__le32 func_done; |
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__le32 rsv[4]; |
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}; |
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|
|
#define FUNC_CLEAR_RST_FUN_DONE_S 0 |
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/* Each physical function manages up to 248 virtual functions, it takes up to |
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* 100ms for each function to execute clear. If an abnormal reset occurs, it is |
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* executed twice at most, so it takes up to 249 * 2 * 100ms. |
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*/ |
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#define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100) |
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#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40 |
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#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20 |
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struct hns_roce_cfg_llm_a { |
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__le32 base_addr_l; |
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__le32 base_addr_h; |
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__le32 depth_pgsz_init_en; |
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__le32 head_ba_l; |
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__le32 head_ba_h_nxtptr; |
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__le32 head_ptr; |
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}; |
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#define CFG_LLM_QUE_DEPTH_S 0 |
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#define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0) |
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#define CFG_LLM_QUE_PGSZ_S 16 |
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#define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16) |
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#define CFG_LLM_INIT_EN_S 20 |
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#define CFG_LLM_INIT_EN_M GENMASK(20, 20) |
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#define CFG_LLM_HEAD_PTR_S 0 |
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#define CFG_LLM_HEAD_PTR_M GENMASK(11, 0) |
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struct hns_roce_cfg_llm_b { |
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__le32 tail_ba_l; |
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__le32 tail_ba_h; |
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__le32 tail_ptr; |
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__le32 rsv[3]; |
|
}; |
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#define CFG_LLM_TAIL_BA_H_S 0 |
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#define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0) |
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#define CFG_LLM_TAIL_PTR_S 0 |
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#define CFG_LLM_TAIL_PTR_M GENMASK(11, 0) |
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struct hns_roce_cfg_global_param { |
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__le32 time_cfg_udp_port; |
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__le32 rsv[5]; |
|
}; |
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|
#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0 |
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0) |
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16 |
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16) |
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struct hns_roce_pf_res_a { |
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__le32 rsv; |
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__le32 qpc_bt_idx_num; |
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__le32 srqc_bt_idx_num; |
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__le32 cqc_bt_idx_num; |
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__le32 mpt_bt_idx_num; |
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__le32 eqc_bt_idx_num; |
|
}; |
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#define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0 |
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#define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0) |
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#define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16 |
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#define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16) |
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#define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0 |
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#define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0) |
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#define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16 |
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#define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16) |
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#define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0 |
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#define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0) |
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#define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16 |
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#define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16) |
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#define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0 |
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#define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0) |
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#define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16 |
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#define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16) |
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#define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0 |
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#define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0) |
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#define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16 |
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#define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16) |
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struct hns_roce_pf_res_b { |
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__le32 rsv0; |
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__le32 smac_idx_num; |
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__le32 sgid_idx_num; |
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__le32 qid_idx_sl_num; |
|
__le32 sccc_bt_idx_num; |
|
__le32 gmv_idx_num; |
|
}; |
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|
#define PF_RES_DATA_1_PF_SMAC_IDX_S 0 |
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#define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0) |
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#define PF_RES_DATA_1_PF_SMAC_NUM_S 8 |
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#define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8) |
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#define PF_RES_DATA_2_PF_SGID_IDX_S 0 |
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#define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0) |
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|
#define PF_RES_DATA_2_PF_SGID_NUM_S 8 |
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#define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8) |
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|
#define PF_RES_DATA_3_PF_QID_IDX_S 0 |
|
#define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0) |
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|
#define PF_RES_DATA_3_PF_SL_NUM_S 16 |
|
#define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16) |
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|
#define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0 |
|
#define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0) |
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|
|
#define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9 |
|
#define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9) |
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|
|
#define PF_RES_DATA_5_PF_GMV_BT_IDX_S 0 |
|
#define PF_RES_DATA_5_PF_GMV_BT_IDX_M GENMASK(7, 0) |
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|
|
#define PF_RES_DATA_5_PF_GMV_BT_NUM_S 8 |
|
#define PF_RES_DATA_5_PF_GMV_BT_NUM_M GENMASK(16, 8) |
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|
|
struct hns_roce_pf_timer_res_a { |
|
__le32 rsv0; |
|
__le32 qpc_timer_bt_idx_num; |
|
__le32 cqc_timer_bt_idx_num; |
|
__le32 rsv[3]; |
|
}; |
|
|
|
#define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0 |
|
#define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0) |
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|
|
#define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16 |
|
#define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16) |
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|
|
#define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0 |
|
#define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0) |
|
|
|
#define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16 |
|
#define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16) |
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|
|
struct hns_roce_vf_res_a { |
|
__le32 vf_id; |
|
__le32 vf_qpc_bt_idx_num; |
|
__le32 vf_srqc_bt_idx_num; |
|
__le32 vf_cqc_bt_idx_num; |
|
__le32 vf_mpt_bt_idx_num; |
|
__le32 vf_eqc_bt_idx_num; |
|
}; |
|
|
|
#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0 |
|
#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0) |
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|
|
#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16 |
|
#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16) |
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|
|
#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0 |
|
#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0) |
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|
|
#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16 |
|
#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16) |
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|
|
#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0 |
|
#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0) |
|
|
|
#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16 |
|
#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16) |
|
|
|
#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0 |
|
#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0) |
|
|
|
#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16 |
|
#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16) |
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|
|
#define VF_RES_A_DATA_5_VF_EQC_IDX_S 0 |
|
#define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0) |
|
|
|
#define VF_RES_A_DATA_5_VF_EQC_NUM_S 16 |
|
#define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16) |
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|
|
struct hns_roce_vf_res_b { |
|
__le32 rsv0; |
|
__le32 vf_smac_idx_num; |
|
__le32 vf_sgid_idx_num; |
|
__le32 vf_qid_idx_sl_num; |
|
__le32 vf_sccc_idx_num; |
|
__le32 vf_gmv_idx_num; |
|
}; |
|
|
|
#define VF_RES_B_DATA_0_VF_ID_S 0 |
|
#define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0) |
|
|
|
#define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0 |
|
#define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0) |
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|
|
#define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8 |
|
#define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8) |
|
|
|
#define VF_RES_B_DATA_2_VF_SGID_IDX_S 0 |
|
#define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0) |
|
|
|
#define VF_RES_B_DATA_2_VF_SGID_NUM_S 8 |
|
#define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8) |
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|
|
#define VF_RES_B_DATA_3_VF_QID_IDX_S 0 |
|
#define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0) |
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|
|
#define VF_RES_B_DATA_3_VF_SL_NUM_S 16 |
|
#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16) |
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|
|
#define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0 |
|
#define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0) |
|
|
|
#define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9 |
|
#define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9) |
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|
|
#define VF_RES_B_DATA_5_VF_GMV_BT_IDX_S 0 |
|
#define VF_RES_B_DATA_5_VF_GMV_BT_IDX_M GENMASK(7, 0) |
|
|
|
#define VF_RES_B_DATA_5_VF_GMV_BT_NUM_S 16 |
|
#define VF_RES_B_DATA_5_VF_GMV_BT_NUM_M GENMASK(24, 16) |
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|
|
struct hns_roce_vf_switch { |
|
__le32 rocee_sel; |
|
__le32 fun_id; |
|
__le32 cfg; |
|
__le32 resv1; |
|
__le32 resv2; |
|
__le32 resv3; |
|
}; |
|
|
|
#define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3 |
|
#define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3) |
|
|
|
#define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1 |
|
#define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2 |
|
#define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3 |
|
|
|
struct hns_roce_post_mbox { |
|
__le32 in_param_l; |
|
__le32 in_param_h; |
|
__le32 out_param_l; |
|
__le32 out_param_h; |
|
__le32 cmd_tag; |
|
__le32 token_event_en; |
|
}; |
|
|
|
struct hns_roce_mbox_status { |
|
__le32 mb_status_hw_run; |
|
__le32 rsv[5]; |
|
}; |
|
|
|
struct hns_roce_cfg_bt_attr { |
|
__le32 vf_qpc_cfg; |
|
__le32 vf_srqc_cfg; |
|
__le32 vf_cqc_cfg; |
|
__le32 vf_mpt_cfg; |
|
__le32 vf_sccc_cfg; |
|
__le32 rsv; |
|
}; |
|
|
|
#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0 |
|
#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0) |
|
|
|
#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4 |
|
#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4) |
|
|
|
#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8 |
|
#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8) |
|
|
|
#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0 |
|
#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0) |
|
|
|
#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4 |
|
#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4) |
|
|
|
#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8 |
|
#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8) |
|
|
|
#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0 |
|
#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0) |
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|
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#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4 |
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#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4) |
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|
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#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8 |
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#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8) |
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#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0 |
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#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0) |
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|
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#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4 |
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#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4) |
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#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8 |
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#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8) |
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#define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0 |
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#define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0) |
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#define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4 |
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#define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4) |
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#define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8 |
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#define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8) |
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struct hns_roce_cfg_sgid_tb { |
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__le32 table_idx_rsv; |
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__le32 vf_sgid_l; |
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__le32 vf_sgid_ml; |
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__le32 vf_sgid_mh; |
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__le32 vf_sgid_h; |
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__le32 vf_sgid_type_rsv; |
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}; |
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|
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enum { |
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HNS_ROCE_CFG_QPC_SIZE = BIT(0), |
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HNS_ROCE_CFG_SCCC_SIZE = BIT(1), |
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}; |
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|
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struct hns_roce_cfg_entry_size { |
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__le32 type; |
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__le32 rsv[4]; |
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__le32 size; |
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}; |
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|
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#define CFG_SGID_TB_TABLE_IDX_S 0 |
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#define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0) |
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#define CFG_SGID_TB_VF_SGID_TYPE_S 0 |
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#define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0) |
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struct hns_roce_cfg_smac_tb { |
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__le32 tb_idx_rsv; |
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__le32 vf_smac_l; |
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__le32 vf_smac_h_rsv; |
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__le32 rsv[3]; |
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}; |
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#define CFG_SMAC_TB_IDX_S 0 |
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#define CFG_SMAC_TB_IDX_M GENMASK(7, 0) |
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#define CFG_SMAC_TB_VF_SMAC_H_S 0 |
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#define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0) |
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struct hns_roce_cfg_gmv_bt { |
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__le32 gmv_ba_l; |
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__le32 gmv_ba_h; |
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__le32 gmv_bt_idx; |
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__le32 rsv[3]; |
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}; |
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#define CFG_GMV_BA_H_S 0 |
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#define CFG_GMV_BA_H_M GENMASK(19, 0) |
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struct hns_roce_cfg_gmv_tb_a { |
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__le32 vf_sgid_l; |
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__le32 vf_sgid_ml; |
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__le32 vf_sgid_mh; |
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__le32 vf_sgid_h; |
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__le32 vf_sgid_type_vlan; |
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__le32 resv; |
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}; |
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#define CFG_GMV_TB_SGID_IDX_S 0 |
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#define CFG_GMV_TB_SGID_IDX_M GENMASK(7, 0) |
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#define CFG_GMV_TB_VF_SGID_TYPE_S 0 |
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#define CFG_GMV_TB_VF_SGID_TYPE_M GENMASK(1, 0) |
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#define CFG_GMV_TB_VF_VLAN_EN_S 2 |
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#define CFG_GMV_TB_VF_VLAN_ID_S 16 |
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#define CFG_GMV_TB_VF_VLAN_ID_M GENMASK(27, 16) |
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struct hns_roce_cfg_gmv_tb_b { |
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__le32 vf_smac_l; |
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__le32 vf_smac_h; |
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__le32 table_idx_rsv; |
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__le32 resv[3]; |
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}; |
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#define CFG_GMV_TB_SMAC_H_S 0 |
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#define CFG_GMV_TB_SMAC_H_M GENMASK(15, 0) |
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#define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5 |
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struct hns_roce_query_pf_caps_a { |
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u8 number_ports; |
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u8 local_ca_ack_delay; |
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__le16 max_sq_sg; |
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__le16 max_sq_inline; |
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__le16 max_rq_sg; |
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__le32 max_extend_sg; |
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__le16 num_qpc_timer; |
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__le16 num_cqc_timer; |
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__le16 max_srq_sges; |
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u8 num_aeq_vectors; |
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u8 num_other_vectors; |
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u8 max_sq_desc_sz; |
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u8 max_rq_desc_sz; |
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u8 max_srq_desc_sz; |
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u8 cqe_sz; |
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}; |
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|
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struct hns_roce_query_pf_caps_b { |
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u8 mtpt_entry_sz; |
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u8 irrl_entry_sz; |
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u8 trrl_entry_sz; |
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u8 cqc_entry_sz; |
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u8 srqc_entry_sz; |
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u8 idx_entry_sz; |
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u8 sccc_sz; |
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u8 max_mtu; |
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__le16 qpc_sz; |
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__le16 qpc_timer_entry_sz; |
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__le16 cqc_timer_entry_sz; |
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u8 min_cqes; |
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u8 min_wqes; |
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__le32 page_size_cap; |
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u8 pkey_table_len; |
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u8 phy_num_uars; |
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u8 ctx_hop_num; |
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u8 pbl_hop_num; |
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}; |
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|
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struct hns_roce_query_pf_caps_c { |
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__le32 cap_flags_num_pds; |
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__le32 max_gid_num_cqs; |
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__le32 cq_depth; |
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__le32 num_mrws; |
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__le32 ord_num_qps; |
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__le16 sq_depth; |
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__le16 rq_depth; |
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}; |
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|
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#define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0 |
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#define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0) |
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#define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20 |
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#define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20) |
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#define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0 |
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#define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0) |
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#define V2_QUERY_PF_CAPS_C_MAX_GID_S 20 |
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#define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20) |
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#define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0 |
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#define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0) |
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|
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#define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0 |
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#define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0) |
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|
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#define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0 |
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#define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0) |
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|
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#define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20 |
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#define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20) |
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|
|
struct hns_roce_query_pf_caps_d { |
|
__le32 wq_hop_num_max_srqs; |
|
__le16 srq_depth; |
|
__le16 cap_flags_ex; |
|
__le32 num_ceqs_ceq_depth; |
|
__le32 arm_st_aeq_depth; |
|
__le32 num_uars_rsv_pds; |
|
__le32 rsv_uars_rsv_qps; |
|
}; |
|
#define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0 |
|
#define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0) |
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|
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#define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20 |
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#define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20) |
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|
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#define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22 |
|
#define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22) |
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|
|
#define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24 |
|
#define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24) |
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|
|
|
|
#define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0 |
|
#define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0) |
|
|
|
#define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22 |
|
#define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22) |
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|
|
#define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0 |
|
#define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0) |
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|
|
#define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22 |
|
#define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22) |
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|
|
#define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24 |
|
#define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24) |
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|
|
#define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0 |
|
#define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0) |
|
|
|
#define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20 |
|
#define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20) |
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|
|
#define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0 |
|
#define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0) |
|
|
|
#define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20 |
|
#define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20) |
|
|
|
struct hns_roce_query_pf_caps_e { |
|
__le32 chunk_size_shift_rsv_mrws; |
|
__le32 rsv_cqs; |
|
__le32 rsv_srqs; |
|
__le32 rsv_lkey; |
|
__le16 ceq_max_cnt; |
|
__le16 ceq_period; |
|
__le16 aeq_max_cnt; |
|
__le16 aeq_period; |
|
}; |
|
|
|
#define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0 |
|
#define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0) |
|
|
|
#define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20 |
|
#define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20) |
|
|
|
#define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0 |
|
#define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0) |
|
|
|
#define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0 |
|
#define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0) |
|
|
|
#define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0 |
|
#define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0) |
|
|
|
struct hns_roce_cmq_desc { |
|
__le16 opcode; |
|
__le16 flag; |
|
__le16 retval; |
|
__le16 rsv; |
|
__le32 data[6]; |
|
}; |
|
|
|
#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000 |
|
|
|
#define HNS_ROCE_HW_RUN_BIT_SHIFT 31 |
|
#define HNS_ROCE_HW_MB_STATUS_MASK 0xFF |
|
|
|
struct hns_roce_v2_cmq_ring { |
|
dma_addr_t desc_dma_addr; |
|
struct hns_roce_cmq_desc *desc; |
|
u32 head; |
|
u16 buf_size; |
|
u16 desc_num; |
|
u8 flag; |
|
spinlock_t lock; /* command queue lock */ |
|
}; |
|
|
|
struct hns_roce_v2_cmq { |
|
struct hns_roce_v2_cmq_ring csq; |
|
struct hns_roce_v2_cmq_ring crq; |
|
u16 tx_timeout; |
|
}; |
|
|
|
enum hns_roce_link_table_type { |
|
TSQ_LINK_TABLE, |
|
TPQ_LINK_TABLE, |
|
}; |
|
|
|
struct hns_roce_link_table { |
|
struct hns_roce_buf_list table; |
|
struct hns_roce_buf_list *pg_list; |
|
u32 npages; |
|
u32 pg_sz; |
|
}; |
|
|
|
struct hns_roce_link_table_entry { |
|
u32 blk_ba0; |
|
u32 blk_ba1_nxt_ptr; |
|
}; |
|
#define HNS_ROCE_LINK_TABLE_BA1_S 0 |
|
#define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0) |
|
|
|
#define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20 |
|
#define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20) |
|
|
|
struct hns_roce_v2_priv { |
|
struct hnae3_handle *handle; |
|
struct hns_roce_v2_cmq cmq; |
|
struct hns_roce_link_table tsq; |
|
struct hns_roce_link_table tpq; |
|
}; |
|
|
|
struct hns_roce_eq_context { |
|
__le32 byte_4; |
|
__le32 byte_8; |
|
__le32 byte_12; |
|
__le32 eqe_report_timer; |
|
__le32 eqe_ba0; |
|
__le32 eqe_ba1; |
|
__le32 byte_28; |
|
__le32 byte_32; |
|
__le32 byte_36; |
|
__le32 byte_40; |
|
__le32 byte_44; |
|
__le32 rsv[5]; |
|
}; |
|
|
|
#define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0 |
|
#define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0 |
|
#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0 |
|
#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0 |
|
|
|
#define HNS_ROCE_V2_EQ_STATE_INVALID 0 |
|
#define HNS_ROCE_V2_EQ_STATE_VALID 1 |
|
#define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2 |
|
#define HNS_ROCE_V2_EQ_STATE_FAILURE 3 |
|
|
|
#define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0 |
|
#define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1 |
|
|
|
#define HNS_ROCE_V2_EQ_COALESCE_0 0 |
|
#define HNS_ROCE_V2_EQ_COALESCE_1 1 |
|
|
|
#define HNS_ROCE_V2_EQ_FIRED 0 |
|
#define HNS_ROCE_V2_EQ_ARMED 1 |
|
#define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3 |
|
|
|
#define HNS_ROCE_EQ_INIT_EQE_CNT 0 |
|
#define HNS_ROCE_EQ_INIT_PROD_IDX 0 |
|
#define HNS_ROCE_EQ_INIT_REPORT_TIMER 0 |
|
#define HNS_ROCE_EQ_INIT_MSI_IDX 0 |
|
#define HNS_ROCE_EQ_INIT_CONS_IDX 0 |
|
#define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0 |
|
|
|
#define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31 |
|
#define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31 |
|
|
|
#define HNS_ROCE_V2_COMP_EQE_NUM 0x1000 |
|
#define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000 |
|
|
|
#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0 |
|
#define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1 |
|
#define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2 |
|
|
|
#define HNS_ROCE_EQ_DB_CMD_AEQ 0x0 |
|
#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1 |
|
#define HNS_ROCE_EQ_DB_CMD_CEQ 0x2 |
|
#define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3 |
|
|
|
#define EQ_ENABLE 1 |
|
#define EQ_DISABLE 0 |
|
|
|
#define EQ_REG_OFFSET 0x4 |
|
|
|
#define HNS_ROCE_INT_NAME_LEN 32 |
|
#define HNS_ROCE_V2_EQN_M GENMASK(23, 0) |
|
|
|
#define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0) |
|
|
|
#define HNS_ROCE_V2_VF_ABN_INT_EN_S 0 |
|
#define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0) |
|
#define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0) |
|
#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) |
|
#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) |
|
|
|
/* WORD0 */ |
|
#define HNS_ROCE_EQC_EQ_ST_S 0 |
|
#define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0) |
|
|
|
#define HNS_ROCE_EQC_HOP_NUM_S 2 |
|
#define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2) |
|
|
|
#define HNS_ROCE_EQC_OVER_IGNORE_S 4 |
|
#define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4) |
|
|
|
#define HNS_ROCE_EQC_COALESCE_S 5 |
|
#define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5) |
|
|
|
#define HNS_ROCE_EQC_ARM_ST_S 6 |
|
#define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6) |
|
|
|
#define HNS_ROCE_EQC_EQN_S 8 |
|
#define HNS_ROCE_EQC_EQN_M GENMASK(15, 8) |
|
|
|
#define HNS_ROCE_EQC_EQE_CNT_S 16 |
|
#define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16) |
|
|
|
/* WORD1 */ |
|
#define HNS_ROCE_EQC_BA_PG_SZ_S 0 |
|
#define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0) |
|
|
|
#define HNS_ROCE_EQC_BUF_PG_SZ_S 4 |
|
#define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4) |
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|
|
#define HNS_ROCE_EQC_PROD_INDX_S 8 |
|
#define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8) |
|
|
|
/* WORD2 */ |
|
#define HNS_ROCE_EQC_MAX_CNT_S 0 |
|
#define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0) |
|
|
|
#define HNS_ROCE_EQC_PERIOD_S 16 |
|
#define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16) |
|
|
|
/* WORD3 */ |
|
#define HNS_ROCE_EQC_REPORT_TIMER_S 0 |
|
#define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0) |
|
|
|
/* WORD4 */ |
|
#define HNS_ROCE_EQC_EQE_BA_L_S 0 |
|
#define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0) |
|
|
|
/* WORD5 */ |
|
#define HNS_ROCE_EQC_EQE_BA_H_S 0 |
|
#define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0) |
|
|
|
/* WORD6 */ |
|
#define HNS_ROCE_EQC_SHIFT_S 0 |
|
#define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0) |
|
|
|
#define HNS_ROCE_EQC_MSI_INDX_S 8 |
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#define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8) |
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#define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16 |
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#define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16) |
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/* WORD7 */ |
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#define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0 |
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#define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0) |
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/* WORD8 */ |
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#define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0 |
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#define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0) |
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#define HNS_ROCE_EQC_CONS_INDX_S 8 |
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#define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8) |
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/* WORD9 */ |
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#define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0 |
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#define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0) |
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/* WORD10 */ |
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#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0 |
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#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0) |
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#define HNS_ROCE_EQC_EQE_SIZE_S 20 |
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#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20) |
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#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 |
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#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) |
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#define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0 |
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#define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0) |
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#define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8 |
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#define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8) |
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#define HNS_ROCE_V2_EQ_DB_CMD_S 16 |
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#define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16) |
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#define HNS_ROCE_V2_EQ_DB_TAG_S 0 |
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#define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0) |
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#define HNS_ROCE_V2_EQ_DB_PARA_S 0 |
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#define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0) |
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#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0 |
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#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0) |
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#define MAX_SERVICE_LEVEL 0x7 |
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struct hns_roce_wqe_atomic_seg { |
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__le64 fetchadd_swap_data; |
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__le64 cmp_data; |
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}; |
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struct hns_roce_sccc_clr { |
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__le32 qpn; |
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__le32 rsv[5]; |
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}; |
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struct hns_roce_sccc_clr_done { |
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__le32 clr_done; |
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__le32 rsv[5]; |
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}; |
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int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn, |
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int *buffer); |
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static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2], |
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void __iomem *dest) |
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{ |
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struct hns_roce_v2_priv *priv = hr_dev->priv; |
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struct hnae3_handle *handle = priv->handle; |
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops; |
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if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) |
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hns_roce_write64_k(val, dest); |
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} |
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#endif
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