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866 lines
22 KiB
866 lines
22 KiB
/* |
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* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef __T4_H__ |
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#define __T4_H__ |
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#include "t4_hw.h" |
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#include "t4_regs.h" |
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#include "t4_values.h" |
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#include "t4_msg.h" |
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#include "t4_tcb.h" |
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#include "t4fw_ri_api.h" |
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#define T4_MAX_NUM_PD 65536 |
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#define T4_MAX_MR_SIZE (~0ULL) |
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#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ |
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#define T4_STAG_UNSET 0xffffffff |
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#define T4_FW_MAJ 0 |
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#define PCIE_MA_SYNC_A 0x30b4 |
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struct t4_status_page { |
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__be32 rsvd1; /* flit 0 - hw owns */ |
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__be16 rsvd2; |
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__be16 qid; |
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__be16 cidx; |
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__be16 pidx; |
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u8 qp_err; /* flit 1 - sw owns */ |
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u8 db_off; |
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u8 pad[2]; |
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u16 host_wq_pidx; |
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u16 host_cidx; |
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u16 host_pidx; |
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u16 pad2; |
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u32 srqidx; |
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}; |
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#define T4_RQT_ENTRY_SHIFT 6 |
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#define T4_RQT_ENTRY_SIZE BIT(T4_RQT_ENTRY_SHIFT) |
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#define T4_EQ_ENTRY_SIZE 64 |
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#define T4_SQ_NUM_SLOTS 5 |
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#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) |
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#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ |
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sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) |
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#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ |
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sizeof(struct fw_ri_immd))) |
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#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ |
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sizeof(struct fw_ri_rdma_write_wr) - \ |
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sizeof(struct fw_ri_immd))) |
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#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ |
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sizeof(struct fw_ri_rdma_write_wr) - \ |
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sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) |
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#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ |
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sizeof(struct fw_ri_immd)) & ~31UL) |
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#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) |
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#define T4_MAX_FR_DSGL 1024 |
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#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) |
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static inline int t4_max_fr_depth(int use_dsgl) |
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{ |
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return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH; |
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} |
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#define T4_RQ_NUM_SLOTS 2 |
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#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) |
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#define T4_MAX_RECV_SGE 4 |
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#define T4_WRITE_CMPL_MAX_SGL 4 |
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#define T4_WRITE_CMPL_MAX_CQE 16 |
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union t4_wr { |
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struct fw_ri_res_wr res; |
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struct fw_ri_wr ri; |
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struct fw_ri_rdma_write_wr write; |
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struct fw_ri_send_wr send; |
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struct fw_ri_rdma_read_wr read; |
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struct fw_ri_bind_mw_wr bind; |
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struct fw_ri_fr_nsmr_wr fr; |
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struct fw_ri_fr_nsmr_tpte_wr fr_tpte; |
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struct fw_ri_inv_lstag_wr inv; |
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struct fw_ri_rdma_write_cmpl_wr write_cmpl; |
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struct t4_status_page status; |
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__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; |
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}; |
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union t4_recv_wr { |
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struct fw_ri_recv_wr recv; |
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struct t4_status_page status; |
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__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; |
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}; |
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static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, |
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enum fw_wr_opcodes opcode, u8 flags, u8 len16) |
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{ |
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wqe->send.opcode = (u8)opcode; |
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wqe->send.flags = flags; |
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wqe->send.wrid = wrid; |
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wqe->send.r1[0] = 0; |
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wqe->send.r1[1] = 0; |
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wqe->send.r1[2] = 0; |
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wqe->send.len16 = len16; |
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} |
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/* CQE/AE status codes */ |
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#define T4_ERR_SUCCESS 0x0 |
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#define T4_ERR_STAG 0x1 /* STAG invalid: either the */ |
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/* STAG is offlimt, being 0, */ |
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/* or STAG_key mismatch */ |
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#define T4_ERR_PDID 0x2 /* PDID mismatch */ |
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#define T4_ERR_QPID 0x3 /* QPID mismatch */ |
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#define T4_ERR_ACCESS 0x4 /* Invalid access right */ |
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#define T4_ERR_WRAP 0x5 /* Wrap error */ |
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#define T4_ERR_BOUND 0x6 /* base and bounds voilation */ |
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#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ |
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/* shared memory region */ |
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#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ |
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/* shared memory region */ |
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#define T4_ERR_ECC 0x9 /* ECC error detected */ |
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#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ |
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/* reading PSTAG for a MW */ |
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/* Invalidate */ |
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#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ |
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/* software error */ |
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#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ |
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#define T4_ERR_CRC 0x10 /* CRC error */ |
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#define T4_ERR_MARKER 0x11 /* Marker error */ |
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#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ |
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#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ |
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#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ |
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#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ |
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#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ |
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#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ |
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#define T4_ERR_MSN 0x18 /* MSN error */ |
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#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ |
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#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ |
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/* or READ_REQ */ |
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#define T4_ERR_MSN_GAP 0x1B |
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#define T4_ERR_MSN_RANGE 0x1C |
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#define T4_ERR_IRD_OVERFLOW 0x1D |
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#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ |
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/* software error */ |
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#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ |
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/* mismatch) */ |
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/* |
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* CQE defs |
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*/ |
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struct t4_cqe { |
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__be32 header; |
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__be32 len; |
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union { |
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struct { |
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__be32 stag; |
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__be32 msn; |
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} rcqe; |
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struct { |
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__be32 stag; |
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u16 nada2; |
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u16 cidx; |
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} scqe; |
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struct { |
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__be32 wrid_hi; |
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__be32 wrid_low; |
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} gen; |
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struct { |
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__be32 stag; |
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__be32 msn; |
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__be32 reserved; |
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__be32 abs_rqe_idx; |
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} srcqe; |
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struct { |
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__be32 mo; |
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__be32 msn; |
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/* |
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* Use union for immediate data to be consistent with |
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* stack's 32 bit data and iWARP spec's 64 bit data. |
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*/ |
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union { |
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struct { |
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__be32 imm_data32; |
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u32 reserved; |
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} ib_imm_data; |
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__be64 imm_data64; |
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} iw_imm_data; |
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} imm_data_rcqe; |
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u64 drain_cookie; |
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__be64 flits[3]; |
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} u; |
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__be64 reserved[3]; |
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__be64 bits_type_ts; |
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}; |
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/* macros for flit 0 of the cqe */ |
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#define CQE_QPID_S 12 |
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#define CQE_QPID_M 0xFFFFF |
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#define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M) |
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#define CQE_QPID_V(x) ((x)<<CQE_QPID_S) |
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#define CQE_SWCQE_S 11 |
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#define CQE_SWCQE_M 0x1 |
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#define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M) |
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#define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S) |
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#define CQE_DRAIN_S 10 |
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#define CQE_DRAIN_M 0x1 |
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#define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M) |
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#define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S) |
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#define CQE_STATUS_S 5 |
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#define CQE_STATUS_M 0x1F |
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#define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M) |
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#define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S) |
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#define CQE_TYPE_S 4 |
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#define CQE_TYPE_M 0x1 |
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#define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M) |
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#define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S) |
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#define CQE_OPCODE_S 0 |
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#define CQE_OPCODE_M 0xF |
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#define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M) |
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#define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S) |
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#define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header))) |
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#define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header))) |
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#define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header))) |
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#define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header))) |
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#define SQ_TYPE(x) (CQE_TYPE((x))) |
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#define RQ_TYPE(x) (!CQE_TYPE((x))) |
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#define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header))) |
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#define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header))) |
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#define CQE_SEND_OPCODE(x)( \ |
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(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ |
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(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ |
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(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ |
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(CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) |
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#define CQE_LEN(x) (be32_to_cpu((x)->len)) |
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/* used for RQ completion processing */ |
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#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) |
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#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) |
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#define CQE_ABS_RQE_IDX(x) (be32_to_cpu((x)->u.srcqe.abs_rqe_idx)) |
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#define CQE_IMM_DATA(x)( \ |
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(x)->u.imm_data_rcqe.iw_imm_data.ib_imm_data.imm_data32) |
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/* used for SQ completion processing */ |
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#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) |
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#define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag)) |
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/* generic accessor macros */ |
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#define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi)) |
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#define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low)) |
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#define CQE_DRAIN_COOKIE(x) ((x)->u.drain_cookie) |
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/* macros for flit 3 of the cqe */ |
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#define CQE_GENBIT_S 63 |
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#define CQE_GENBIT_M 0x1 |
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#define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M) |
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#define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S) |
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#define CQE_OVFBIT_S 62 |
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#define CQE_OVFBIT_M 0x1 |
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#define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M) |
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#define CQE_IQTYPE_S 60 |
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#define CQE_IQTYPE_M 0x3 |
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#define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M) |
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#define CQE_TS_M 0x0fffffffffffffffULL |
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#define CQE_TS_G(x) ((x) & CQE_TS_M) |
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#define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts))) |
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#define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts))) |
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#define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts))) |
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struct t4_swsqe { |
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u64 wr_id; |
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struct t4_cqe cqe; |
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int read_len; |
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int opcode; |
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int complete; |
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int signaled; |
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u16 idx; |
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int flushed; |
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ktime_t host_time; |
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u64 sge_ts; |
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}; |
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static inline pgprot_t t4_pgprot_wc(pgprot_t prot) |
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{ |
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#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) |
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return pgprot_writecombine(prot); |
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#else |
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return pgprot_noncached(prot); |
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#endif |
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} |
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enum { |
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T4_SQ_ONCHIP = (1<<0), |
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}; |
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struct t4_sq { |
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union t4_wr *queue; |
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dma_addr_t dma_addr; |
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DEFINE_DMA_UNMAP_ADDR(mapping); |
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unsigned long phys_addr; |
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struct t4_swsqe *sw_sq; |
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struct t4_swsqe *oldest_read; |
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void __iomem *bar2_va; |
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u64 bar2_pa; |
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size_t memsize; |
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u32 bar2_qid; |
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u32 qid; |
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u16 in_use; |
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u16 size; |
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u16 cidx; |
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u16 pidx; |
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u16 wq_pidx; |
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u16 wq_pidx_inc; |
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u16 flags; |
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short flush_cidx; |
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}; |
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struct t4_swrqe { |
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u64 wr_id; |
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ktime_t host_time; |
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u64 sge_ts; |
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int valid; |
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}; |
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struct t4_rq { |
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union t4_recv_wr *queue; |
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dma_addr_t dma_addr; |
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DEFINE_DMA_UNMAP_ADDR(mapping); |
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struct t4_swrqe *sw_rq; |
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void __iomem *bar2_va; |
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u64 bar2_pa; |
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size_t memsize; |
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u32 bar2_qid; |
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u32 qid; |
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u32 msn; |
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u32 rqt_hwaddr; |
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u16 rqt_size; |
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u16 in_use; |
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u16 size; |
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u16 cidx; |
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u16 pidx; |
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u16 wq_pidx; |
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u16 wq_pidx_inc; |
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}; |
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struct t4_wq { |
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struct t4_sq sq; |
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struct t4_rq rq; |
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void __iomem *db; |
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struct c4iw_rdev *rdev; |
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int flushed; |
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u8 *qp_errp; |
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u32 *srqidxp; |
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}; |
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struct t4_srq_pending_wr { |
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u64 wr_id; |
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union t4_recv_wr wqe; |
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u8 len16; |
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}; |
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struct t4_srq { |
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union t4_recv_wr *queue; |
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dma_addr_t dma_addr; |
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DEFINE_DMA_UNMAP_ADDR(mapping); |
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struct t4_swrqe *sw_rq; |
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void __iomem *bar2_va; |
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u64 bar2_pa; |
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size_t memsize; |
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u32 bar2_qid; |
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u32 qid; |
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u32 msn; |
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u32 rqt_hwaddr; |
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u32 rqt_abs_idx; |
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u16 rqt_size; |
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u16 size; |
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u16 cidx; |
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u16 pidx; |
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u16 wq_pidx; |
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u16 wq_pidx_inc; |
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u16 in_use; |
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struct t4_srq_pending_wr *pending_wrs; |
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u16 pending_cidx; |
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u16 pending_pidx; |
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u16 pending_in_use; |
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u16 ooo_count; |
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}; |
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static inline u32 t4_srq_avail(struct t4_srq *srq) |
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{ |
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return srq->size - 1 - srq->in_use; |
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} |
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static inline void t4_srq_produce(struct t4_srq *srq, u8 len16) |
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{ |
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srq->in_use++; |
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if (++srq->pidx == srq->size) |
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srq->pidx = 0; |
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srq->wq_pidx += DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE); |
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if (srq->wq_pidx >= srq->size * T4_RQ_NUM_SLOTS) |
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srq->wq_pidx %= srq->size * T4_RQ_NUM_SLOTS; |
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srq->queue[srq->size].status.host_pidx = srq->pidx; |
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} |
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static inline void t4_srq_produce_pending_wr(struct t4_srq *srq) |
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{ |
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srq->pending_in_use++; |
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srq->in_use++; |
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if (++srq->pending_pidx == srq->size) |
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srq->pending_pidx = 0; |
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} |
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static inline void t4_srq_consume_pending_wr(struct t4_srq *srq) |
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{ |
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srq->pending_in_use--; |
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srq->in_use--; |
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if (++srq->pending_cidx == srq->size) |
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srq->pending_cidx = 0; |
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} |
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static inline void t4_srq_produce_ooo(struct t4_srq *srq) |
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{ |
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srq->in_use--; |
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srq->ooo_count++; |
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} |
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static inline void t4_srq_consume_ooo(struct t4_srq *srq) |
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{ |
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srq->cidx++; |
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if (srq->cidx == srq->size) |
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srq->cidx = 0; |
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srq->queue[srq->size].status.host_cidx = srq->cidx; |
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srq->ooo_count--; |
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} |
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|
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static inline void t4_srq_consume(struct t4_srq *srq) |
|
{ |
|
srq->in_use--; |
|
if (++srq->cidx == srq->size) |
|
srq->cidx = 0; |
|
srq->queue[srq->size].status.host_cidx = srq->cidx; |
|
} |
|
|
|
static inline int t4_rqes_posted(struct t4_wq *wq) |
|
{ |
|
return wq->rq.in_use; |
|
} |
|
|
|
static inline int t4_rq_empty(struct t4_wq *wq) |
|
{ |
|
return wq->rq.in_use == 0; |
|
} |
|
|
|
static inline int t4_rq_full(struct t4_wq *wq) |
|
{ |
|
return wq->rq.in_use == (wq->rq.size - 1); |
|
} |
|
|
|
static inline u32 t4_rq_avail(struct t4_wq *wq) |
|
{ |
|
return wq->rq.size - 1 - wq->rq.in_use; |
|
} |
|
|
|
static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) |
|
{ |
|
wq->rq.in_use++; |
|
if (++wq->rq.pidx == wq->rq.size) |
|
wq->rq.pidx = 0; |
|
wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); |
|
if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) |
|
wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; |
|
} |
|
|
|
static inline void t4_rq_consume(struct t4_wq *wq) |
|
{ |
|
wq->rq.in_use--; |
|
if (++wq->rq.cidx == wq->rq.size) |
|
wq->rq.cidx = 0; |
|
} |
|
|
|
static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) |
|
{ |
|
return wq->rq.queue[wq->rq.size].status.host_wq_pidx; |
|
} |
|
|
|
static inline u16 t4_rq_wq_size(struct t4_wq *wq) |
|
{ |
|
return wq->rq.size * T4_RQ_NUM_SLOTS; |
|
} |
|
|
|
static inline int t4_sq_onchip(struct t4_sq *sq) |
|
{ |
|
return sq->flags & T4_SQ_ONCHIP; |
|
} |
|
|
|
static inline int t4_sq_empty(struct t4_wq *wq) |
|
{ |
|
return wq->sq.in_use == 0; |
|
} |
|
|
|
static inline int t4_sq_full(struct t4_wq *wq) |
|
{ |
|
return wq->sq.in_use == (wq->sq.size - 1); |
|
} |
|
|
|
static inline u32 t4_sq_avail(struct t4_wq *wq) |
|
{ |
|
return wq->sq.size - 1 - wq->sq.in_use; |
|
} |
|
|
|
static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) |
|
{ |
|
wq->sq.in_use++; |
|
if (++wq->sq.pidx == wq->sq.size) |
|
wq->sq.pidx = 0; |
|
wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); |
|
if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) |
|
wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; |
|
} |
|
|
|
static inline void t4_sq_consume(struct t4_wq *wq) |
|
{ |
|
if (wq->sq.cidx == wq->sq.flush_cidx) |
|
wq->sq.flush_cidx = -1; |
|
wq->sq.in_use--; |
|
if (++wq->sq.cidx == wq->sq.size) |
|
wq->sq.cidx = 0; |
|
} |
|
|
|
static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) |
|
{ |
|
return wq->sq.queue[wq->sq.size].status.host_wq_pidx; |
|
} |
|
|
|
static inline u16 t4_sq_wq_size(struct t4_wq *wq) |
|
{ |
|
return wq->sq.size * T4_SQ_NUM_SLOTS; |
|
} |
|
|
|
/* This function copies 64 byte coalesced work request to memory |
|
* mapped BAR2 space. For coalesced WRs, the SGE fetches data |
|
* from the FIFO instead of from Host. |
|
*/ |
|
static inline void pio_copy(u64 __iomem *dst, u64 *src) |
|
{ |
|
int count = 8; |
|
|
|
while (count) { |
|
writeq(*src, dst); |
|
src++; |
|
dst++; |
|
count--; |
|
} |
|
} |
|
|
|
static inline void t4_ring_srq_db(struct t4_srq *srq, u16 inc, u8 len16, |
|
union t4_recv_wr *wqe) |
|
{ |
|
/* Flush host queue memory writes. */ |
|
wmb(); |
|
if (inc == 1 && srq->bar2_qid == 0 && wqe) { |
|
pr_debug("%s : WC srq->pidx = %d; len16=%d\n", |
|
__func__, srq->pidx, len16); |
|
pio_copy(srq->bar2_va + SGE_UDB_WCDOORBELL, (u64 *)wqe); |
|
} else { |
|
pr_debug("%s: DB srq->pidx = %d; len16=%d\n", |
|
__func__, srq->pidx, len16); |
|
writel(PIDX_T5_V(inc) | QID_V(srq->bar2_qid), |
|
srq->bar2_va + SGE_UDB_KDOORBELL); |
|
} |
|
/* Flush user doorbell area writes. */ |
|
wmb(); |
|
} |
|
|
|
static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe) |
|
{ |
|
|
|
/* Flush host queue memory writes. */ |
|
wmb(); |
|
if (wq->sq.bar2_va) { |
|
if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) { |
|
pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx); |
|
pio_copy((u64 __iomem *) |
|
(wq->sq.bar2_va + SGE_UDB_WCDOORBELL), |
|
(u64 *)wqe); |
|
} else { |
|
pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx); |
|
writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid), |
|
wq->sq.bar2_va + SGE_UDB_KDOORBELL); |
|
} |
|
|
|
/* Flush user doorbell area writes. */ |
|
wmb(); |
|
return; |
|
} |
|
writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db); |
|
} |
|
|
|
static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, |
|
union t4_recv_wr *wqe) |
|
{ |
|
|
|
/* Flush host queue memory writes. */ |
|
wmb(); |
|
if (wq->rq.bar2_va) { |
|
if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) { |
|
pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx); |
|
pio_copy((u64 __iomem *) |
|
(wq->rq.bar2_va + SGE_UDB_WCDOORBELL), |
|
(void *)wqe); |
|
} else { |
|
pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx); |
|
writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid), |
|
wq->rq.bar2_va + SGE_UDB_KDOORBELL); |
|
} |
|
|
|
/* Flush user doorbell area writes. */ |
|
wmb(); |
|
return; |
|
} |
|
writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db); |
|
} |
|
|
|
static inline int t4_wq_in_error(struct t4_wq *wq) |
|
{ |
|
return *wq->qp_errp; |
|
} |
|
|
|
static inline void t4_set_wq_in_error(struct t4_wq *wq, u32 srqidx) |
|
{ |
|
if (srqidx) |
|
*wq->srqidxp = srqidx; |
|
*wq->qp_errp = 1; |
|
} |
|
|
|
static inline void t4_disable_wq_db(struct t4_wq *wq) |
|
{ |
|
wq->rq.queue[wq->rq.size].status.db_off = 1; |
|
} |
|
|
|
static inline void t4_enable_wq_db(struct t4_wq *wq) |
|
{ |
|
wq->rq.queue[wq->rq.size].status.db_off = 0; |
|
} |
|
|
|
static inline int t4_wq_db_enabled(struct t4_wq *wq) |
|
{ |
|
return !wq->rq.queue[wq->rq.size].status.db_off; |
|
} |
|
|
|
enum t4_cq_flags { |
|
CQ_ARMED = 1, |
|
}; |
|
|
|
struct t4_cq { |
|
struct t4_cqe *queue; |
|
dma_addr_t dma_addr; |
|
DEFINE_DMA_UNMAP_ADDR(mapping); |
|
struct t4_cqe *sw_queue; |
|
void __iomem *gts; |
|
void __iomem *bar2_va; |
|
u64 bar2_pa; |
|
u32 bar2_qid; |
|
struct c4iw_rdev *rdev; |
|
size_t memsize; |
|
__be64 bits_type_ts; |
|
u32 cqid; |
|
u32 qid_mask; |
|
int vector; |
|
u16 size; /* including status page */ |
|
u16 cidx; |
|
u16 sw_pidx; |
|
u16 sw_cidx; |
|
u16 sw_in_use; |
|
u16 cidx_inc; |
|
u8 gen; |
|
u8 error; |
|
u8 *qp_errp; |
|
unsigned long flags; |
|
}; |
|
|
|
static inline void write_gts(struct t4_cq *cq, u32 val) |
|
{ |
|
if (cq->bar2_va) |
|
writel(val | INGRESSQID_V(cq->bar2_qid), |
|
cq->bar2_va + SGE_UDB_GTS); |
|
else |
|
writel(val | INGRESSQID_V(cq->cqid), cq->gts); |
|
} |
|
|
|
static inline int t4_clear_cq_armed(struct t4_cq *cq) |
|
{ |
|
return test_and_clear_bit(CQ_ARMED, &cq->flags); |
|
} |
|
|
|
static inline int t4_arm_cq(struct t4_cq *cq, int se) |
|
{ |
|
u32 val; |
|
|
|
set_bit(CQ_ARMED, &cq->flags); |
|
while (cq->cidx_inc > CIDXINC_M) { |
|
val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7); |
|
write_gts(cq, val); |
|
cq->cidx_inc -= CIDXINC_M; |
|
} |
|
val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6); |
|
write_gts(cq, val); |
|
cq->cidx_inc = 0; |
|
return 0; |
|
} |
|
|
|
static inline void t4_swcq_produce(struct t4_cq *cq) |
|
{ |
|
cq->sw_in_use++; |
|
if (cq->sw_in_use == cq->size) { |
|
pr_warn("%s cxgb4 sw cq overflow cqid %u\n", |
|
__func__, cq->cqid); |
|
cq->error = 1; |
|
cq->sw_in_use--; |
|
return; |
|
} |
|
if (++cq->sw_pidx == cq->size) |
|
cq->sw_pidx = 0; |
|
} |
|
|
|
static inline void t4_swcq_consume(struct t4_cq *cq) |
|
{ |
|
cq->sw_in_use--; |
|
if (++cq->sw_cidx == cq->size) |
|
cq->sw_cidx = 0; |
|
} |
|
|
|
static inline void t4_hwcq_consume(struct t4_cq *cq) |
|
{ |
|
cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; |
|
if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) { |
|
u32 val; |
|
|
|
val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7); |
|
write_gts(cq, val); |
|
cq->cidx_inc = 0; |
|
} |
|
if (++cq->cidx == cq->size) { |
|
cq->cidx = 0; |
|
cq->gen ^= 1; |
|
} |
|
} |
|
|
|
static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) |
|
{ |
|
return (CQE_GENBIT(cqe) == cq->gen); |
|
} |
|
|
|
static inline int t4_cq_notempty(struct t4_cq *cq) |
|
{ |
|
return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]); |
|
} |
|
|
|
static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) |
|
{ |
|
int ret; |
|
u16 prev_cidx; |
|
|
|
if (cq->cidx == 0) |
|
prev_cidx = cq->size - 1; |
|
else |
|
prev_cidx = cq->cidx - 1; |
|
|
|
if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { |
|
ret = -EOVERFLOW; |
|
cq->error = 1; |
|
pr_err("cq overflow cqid %u\n", cq->cqid); |
|
} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { |
|
|
|
/* Ensure CQE is flushed to memory */ |
|
rmb(); |
|
*cqe = &cq->queue[cq->cidx]; |
|
ret = 0; |
|
} else |
|
ret = -ENODATA; |
|
return ret; |
|
} |
|
|
|
static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) |
|
{ |
|
if (cq->sw_in_use == cq->size) { |
|
pr_warn("%s cxgb4 sw cq overflow cqid %u\n", |
|
__func__, cq->cqid); |
|
cq->error = 1; |
|
return NULL; |
|
} |
|
if (cq->sw_in_use) |
|
return &cq->sw_queue[cq->sw_cidx]; |
|
return NULL; |
|
} |
|
|
|
static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) |
|
{ |
|
int ret = 0; |
|
|
|
if (cq->error) |
|
ret = -ENODATA; |
|
else if (cq->sw_in_use) |
|
*cqe = &cq->sw_queue[cq->sw_cidx]; |
|
else |
|
ret = t4_next_hw_cqe(cq, cqe); |
|
return ret; |
|
} |
|
|
|
static inline int t4_cq_in_error(struct t4_cq *cq) |
|
{ |
|
return *cq->qp_errp; |
|
} |
|
|
|
static inline void t4_set_cq_in_error(struct t4_cq *cq) |
|
{ |
|
*cq->qp_errp = 1; |
|
} |
|
#endif |
|
|
|
struct t4_dev_status_page { |
|
u8 db_off; |
|
u8 write_cmpl_supported; |
|
u16 pad2; |
|
u32 pad3; |
|
u64 qp_start; |
|
u64 qp_size; |
|
u64 cq_start; |
|
u64 cq_size; |
|
};
|
|
|