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514 lines
14 KiB
514 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Suspend support specific for i386/x86-64. |
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* |
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* Copyright (c) 2007 Rafael J. Wysocki <[email protected]> |
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* Copyright (c) 2002 Pavel Machek <[email protected]> |
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* Copyright (c) 2001 Patrick Mochel <[email protected]> |
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*/ |
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#include <linux/suspend.h> |
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#include <linux/export.h> |
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#include <linux/smp.h> |
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#include <linux/perf_event.h> |
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#include <linux/tboot.h> |
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#include <linux/dmi.h> |
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#include <linux/pgtable.h> |
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#include <asm/proto.h> |
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#include <asm/mtrr.h> |
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#include <asm/page.h> |
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#include <asm/mce.h> |
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#include <asm/suspend.h> |
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#include <asm/fpu/internal.h> |
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#include <asm/debugreg.h> |
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#include <asm/cpu.h> |
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#include <asm/mmu_context.h> |
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#include <asm/cpu_device_id.h> |
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#ifdef CONFIG_X86_32 |
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__visible unsigned long saved_context_ebx; |
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__visible unsigned long saved_context_esp, saved_context_ebp; |
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__visible unsigned long saved_context_esi, saved_context_edi; |
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__visible unsigned long saved_context_eflags; |
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#endif |
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struct saved_context saved_context; |
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static void msr_save_context(struct saved_context *ctxt) |
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{ |
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struct saved_msr *msr = ctxt->saved_msrs.array; |
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struct saved_msr *end = msr + ctxt->saved_msrs.num; |
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while (msr < end) { |
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msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q); |
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msr++; |
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} |
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} |
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static void msr_restore_context(struct saved_context *ctxt) |
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{ |
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struct saved_msr *msr = ctxt->saved_msrs.array; |
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struct saved_msr *end = msr + ctxt->saved_msrs.num; |
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while (msr < end) { |
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if (msr->valid) |
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wrmsrl(msr->info.msr_no, msr->info.reg.q); |
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msr++; |
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} |
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} |
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/** |
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* __save_processor_state - save CPU registers before creating a |
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* hibernation image and before restoring the memory state from it |
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* @ctxt - structure to store the registers contents in |
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* |
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* NOTE: If there is a CPU register the modification of which by the |
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* boot kernel (ie. the kernel used for loading the hibernation image) |
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* might affect the operations of the restored target kernel (ie. the one |
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* saved in the hibernation image), then its contents must be saved by this |
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* function. In other words, if kernel A is hibernated and different |
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* kernel B is used for loading the hibernation image into memory, the |
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* kernel A's __save_processor_state() function must save all registers |
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* needed by kernel A, so that it can operate correctly after the resume |
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* regardless of what kernel B does in the meantime. |
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*/ |
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static void __save_processor_state(struct saved_context *ctxt) |
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{ |
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#ifdef CONFIG_X86_32 |
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mtrr_save_fixed_ranges(NULL); |
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#endif |
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kernel_fpu_begin(); |
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/* |
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* descriptor tables |
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*/ |
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store_idt(&ctxt->idt); |
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/* |
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* We save it here, but restore it only in the hibernate case. |
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* For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit |
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* mode in "secondary_startup_64". In 32-bit mode it is done via |
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* 'pmode_gdt' in wakeup_start. |
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*/ |
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ctxt->gdt_desc.size = GDT_SIZE - 1; |
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ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id()); |
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store_tr(ctxt->tr); |
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/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ |
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/* |
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* segment registers |
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*/ |
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#ifdef CONFIG_X86_32_LAZY_GS |
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savesegment(gs, ctxt->gs); |
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#endif |
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#ifdef CONFIG_X86_64 |
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savesegment(gs, ctxt->gs); |
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savesegment(fs, ctxt->fs); |
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savesegment(ds, ctxt->ds); |
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savesegment(es, ctxt->es); |
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rdmsrl(MSR_FS_BASE, ctxt->fs_base); |
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rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); |
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rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); |
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mtrr_save_fixed_ranges(NULL); |
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rdmsrl(MSR_EFER, ctxt->efer); |
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#endif |
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/* |
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* control registers |
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*/ |
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ctxt->cr0 = read_cr0(); |
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ctxt->cr2 = read_cr2(); |
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ctxt->cr3 = __read_cr3(); |
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ctxt->cr4 = __read_cr4(); |
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ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, |
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&ctxt->misc_enable); |
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msr_save_context(ctxt); |
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} |
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/* Needed by apm.c */ |
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void save_processor_state(void) |
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{ |
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__save_processor_state(&saved_context); |
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x86_platform.save_sched_clock_state(); |
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} |
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#ifdef CONFIG_X86_32 |
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EXPORT_SYMBOL(save_processor_state); |
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#endif |
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static void do_fpu_end(void) |
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{ |
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/* |
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* Restore FPU regs if necessary. |
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*/ |
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kernel_fpu_end(); |
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} |
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static void fix_processor_context(void) |
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{ |
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int cpu = smp_processor_id(); |
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#ifdef CONFIG_X86_64 |
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struct desc_struct *desc = get_cpu_gdt_rw(cpu); |
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tss_desc tss; |
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#endif |
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/* |
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* We need to reload TR, which requires that we change the |
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* GDT entry to indicate "available" first. |
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* |
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* XXX: This could probably all be replaced by a call to |
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* force_reload_TR(). |
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*/ |
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set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
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#ifdef CONFIG_X86_64 |
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memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc)); |
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tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */ |
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write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS); |
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syscall_init(); /* This sets MSR_*STAR and related */ |
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#else |
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if (boot_cpu_has(X86_FEATURE_SEP)) |
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enable_sep_cpu(); |
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#endif |
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load_TR_desc(); /* This does ltr */ |
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load_mm_ldt(current->active_mm); /* This does lldt */ |
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initialize_tlbstate_and_flush(); |
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fpu__resume_cpu(); |
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/* The processor is back on the direct GDT, load back the fixmap */ |
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load_fixmap_gdt(cpu); |
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} |
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/** |
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* __restore_processor_state - restore the contents of CPU registers saved |
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* by __save_processor_state() |
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* @ctxt - structure to load the registers contents from |
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* |
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* The asm code that gets us here will have restored a usable GDT, although |
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* it will be pointing to the wrong alias. |
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*/ |
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static void notrace __restore_processor_state(struct saved_context *ctxt) |
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{ |
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struct cpuinfo_x86 *c; |
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if (ctxt->misc_enable_saved) |
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wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); |
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/* |
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* control registers |
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*/ |
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/* cr4 was introduced in the Pentium CPU */ |
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#ifdef CONFIG_X86_32 |
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if (ctxt->cr4) |
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__write_cr4(ctxt->cr4); |
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#else |
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/* CONFIG X86_64 */ |
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wrmsrl(MSR_EFER, ctxt->efer); |
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__write_cr4(ctxt->cr4); |
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#endif |
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write_cr3(ctxt->cr3); |
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write_cr2(ctxt->cr2); |
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write_cr0(ctxt->cr0); |
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/* Restore the IDT. */ |
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load_idt(&ctxt->idt); |
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/* |
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* Just in case the asm code got us here with the SS, DS, or ES |
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* out of sync with the GDT, update them. |
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*/ |
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loadsegment(ss, __KERNEL_DS); |
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loadsegment(ds, __USER_DS); |
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loadsegment(es, __USER_DS); |
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/* |
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* Restore percpu access. Percpu access can happen in exception |
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* handlers or in complicated helpers like load_gs_index(). |
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*/ |
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#ifdef CONFIG_X86_64 |
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wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); |
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#else |
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loadsegment(fs, __KERNEL_PERCPU); |
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loadsegment(gs, __KERNEL_STACK_CANARY); |
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#endif |
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/* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */ |
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fix_processor_context(); |
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/* |
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* Now that we have descriptor tables fully restored and working |
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* exception handling, restore the usermode segments. |
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*/ |
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#ifdef CONFIG_X86_64 |
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loadsegment(ds, ctxt->es); |
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loadsegment(es, ctxt->es); |
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loadsegment(fs, ctxt->fs); |
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load_gs_index(ctxt->gs); |
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/* |
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* Restore FSBASE and GSBASE after restoring the selectors, since |
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* restoring the selectors clobbers the bases. Keep in mind |
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* that MSR_KERNEL_GS_BASE is horribly misnamed. |
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*/ |
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wrmsrl(MSR_FS_BASE, ctxt->fs_base); |
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); |
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#elif defined(CONFIG_X86_32_LAZY_GS) |
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loadsegment(gs, ctxt->gs); |
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#endif |
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do_fpu_end(); |
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tsc_verify_tsc_adjust(true); |
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x86_platform.restore_sched_clock_state(); |
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mtrr_bp_restore(); |
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perf_restore_debug_store(); |
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msr_restore_context(ctxt); |
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c = &cpu_data(smp_processor_id()); |
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if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL)) |
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init_ia32_feat_ctl(c); |
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} |
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/* Needed by apm.c */ |
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void notrace restore_processor_state(void) |
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{ |
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__restore_processor_state(&saved_context); |
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} |
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#ifdef CONFIG_X86_32 |
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EXPORT_SYMBOL(restore_processor_state); |
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#endif |
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#if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU) |
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static void resume_play_dead(void) |
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{ |
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play_dead_common(); |
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tboot_shutdown(TB_SHUTDOWN_WFS); |
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hlt_play_dead(); |
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} |
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int hibernate_resume_nonboot_cpu_disable(void) |
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{ |
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void (*play_dead)(void) = smp_ops.play_dead; |
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int ret; |
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/* |
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* Ensure that MONITOR/MWAIT will not be used in the "play dead" loop |
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* during hibernate image restoration, because it is likely that the |
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* monitored address will be actually written to at that time and then |
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* the "dead" CPU will attempt to execute instructions again, but the |
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* address in its instruction pointer may not be possible to resolve |
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* any more at that point (the page tables used by it previously may |
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* have been overwritten by hibernate image data). |
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* |
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* First, make sure that we wake up all the potentially disabled SMT |
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* threads which have been initially brought up and then put into |
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* mwait/cpuidle sleep. |
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* Those will be put to proper (not interfering with hibernation |
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* resume) sleep afterwards, and the resumed kernel will decide itself |
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* what to do with them. |
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*/ |
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ret = cpuhp_smt_enable(); |
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if (ret) |
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return ret; |
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smp_ops.play_dead = resume_play_dead; |
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ret = freeze_secondary_cpus(0); |
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smp_ops.play_dead = play_dead; |
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return ret; |
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} |
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#endif |
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/* |
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* When bsp_check() is called in hibernate and suspend, cpu hotplug |
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* is disabled already. So it's unnessary to handle race condition between |
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* cpumask query and cpu hotplug. |
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*/ |
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static int bsp_check(void) |
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{ |
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if (cpumask_first(cpu_online_mask) != 0) { |
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pr_warn("CPU0 is offline.\n"); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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static int bsp_pm_callback(struct notifier_block *nb, unsigned long action, |
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void *ptr) |
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{ |
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int ret = 0; |
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switch (action) { |
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case PM_SUSPEND_PREPARE: |
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case PM_HIBERNATION_PREPARE: |
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ret = bsp_check(); |
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break; |
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#ifdef CONFIG_DEBUG_HOTPLUG_CPU0 |
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case PM_RESTORE_PREPARE: |
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/* |
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* When system resumes from hibernation, online CPU0 because |
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* 1. it's required for resume and |
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* 2. the CPU was online before hibernation |
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*/ |
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if (!cpu_online(0)) |
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_debug_hotplug_cpu(0, 1); |
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break; |
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case PM_POST_RESTORE: |
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/* |
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* When a resume really happens, this code won't be called. |
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* |
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* This code is called only when user space hibernation software |
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* prepares for snapshot device during boot time. So we just |
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* call _debug_hotplug_cpu() to restore to CPU0's state prior to |
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* preparing the snapshot device. |
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* |
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* This works for normal boot case in our CPU0 hotplug debug |
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* mode, i.e. CPU0 is offline and user mode hibernation |
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* software initializes during boot time. |
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* |
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* If CPU0 is online and user application accesses snapshot |
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* device after boot time, this will offline CPU0 and user may |
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* see different CPU0 state before and after accessing |
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* the snapshot device. But hopefully this is not a case when |
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* user debugging CPU0 hotplug. Even if users hit this case, |
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* they can easily online CPU0 back. |
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* |
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* To simplify this debug code, we only consider normal boot |
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* case. Otherwise we need to remember CPU0's state and restore |
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* to that state and resolve racy conditions etc. |
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*/ |
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_debug_hotplug_cpu(0, 0); |
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break; |
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#endif |
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default: |
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break; |
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} |
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return notifier_from_errno(ret); |
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} |
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static int __init bsp_pm_check_init(void) |
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{ |
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/* |
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* Set this bsp_pm_callback as lower priority than |
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* cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called |
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* earlier to disable cpu hotplug before bsp online check. |
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*/ |
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pm_notifier(bsp_pm_callback, -INT_MAX); |
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return 0; |
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} |
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core_initcall(bsp_pm_check_init); |
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static int msr_build_context(const u32 *msr_id, const int num) |
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{ |
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struct saved_msrs *saved_msrs = &saved_context.saved_msrs; |
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struct saved_msr *msr_array; |
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int total_num; |
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int i, j; |
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total_num = saved_msrs->num + num; |
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msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL); |
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if (!msr_array) { |
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pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n"); |
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return -ENOMEM; |
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} |
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if (saved_msrs->array) { |
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/* |
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* Multiple callbacks can invoke this function, so copy any |
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* MSR save requests from previous invocations. |
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*/ |
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memcpy(msr_array, saved_msrs->array, |
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sizeof(struct saved_msr) * saved_msrs->num); |
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kfree(saved_msrs->array); |
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} |
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for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) { |
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msr_array[i].info.msr_no = msr_id[j]; |
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msr_array[i].valid = false; |
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msr_array[i].info.reg.q = 0; |
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} |
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saved_msrs->num = total_num; |
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saved_msrs->array = msr_array; |
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return 0; |
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} |
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/* |
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* The following sections are a quirk framework for problematic BIOSen: |
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* Sometimes MSRs are modified by the BIOSen after suspended to |
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* RAM, this might cause unexpected behavior after wakeup. |
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* Thus we save/restore these specified MSRs across suspend/resume |
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* in order to work around it. |
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* |
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* For any further problematic BIOSen/platforms, |
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* please add your own function similar to msr_initialize_bdw. |
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*/ |
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static int msr_initialize_bdw(const struct dmi_system_id *d) |
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{ |
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/* Add any extra MSR ids into this array. */ |
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u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL }; |
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pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident); |
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return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id)); |
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} |
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static const struct dmi_system_id msr_save_dmi_table[] = { |
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{ |
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.callback = msr_initialize_bdw, |
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.ident = "BROADWELL BDX_EP", |
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.matches = { |
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DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"), |
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DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"), |
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}, |
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}, |
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{} |
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}; |
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static int msr_save_cpuid_features(const struct x86_cpu_id *c) |
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{ |
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u32 cpuid_msr_id[] = { |
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MSR_AMD64_CPUID_FN_1, |
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}; |
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pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n", |
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c->family); |
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return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id)); |
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} |
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static const struct x86_cpu_id msr_save_cpu_table[] = { |
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X86_MATCH_VENDOR_FAM(AMD, 0x15, &msr_save_cpuid_features), |
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X86_MATCH_VENDOR_FAM(AMD, 0x16, &msr_save_cpuid_features), |
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{} |
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}; |
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typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *); |
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static int pm_cpu_check(const struct x86_cpu_id *c) |
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{ |
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const struct x86_cpu_id *m; |
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int ret = 0; |
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m = x86_match_cpu(msr_save_cpu_table); |
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if (m) { |
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pm_cpu_match_t fn; |
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fn = (pm_cpu_match_t)m->driver_data; |
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ret = fn(m); |
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} |
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return ret; |
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} |
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static int pm_check_save_msr(void) |
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{ |
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dmi_check_system(msr_save_dmi_table); |
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pm_cpu_check(msr_save_cpu_table); |
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return 0; |
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} |
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device_initcall(pm_check_save_msr);
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