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393 lines
9.0 KiB
393 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* SGI RTC clock/timer routines. |
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* |
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* (C) Copyright 2020 Hewlett Packard Enterprise Development LP |
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* Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved. |
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* Copyright (c) Dimitri Sivanich |
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*/ |
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#include <linux/clockchips.h> |
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#include <linux/slab.h> |
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#include <asm/uv/uv_mmrs.h> |
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#include <asm/uv/uv_hub.h> |
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#include <asm/uv/bios.h> |
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#include <asm/uv/uv.h> |
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#include <asm/apic.h> |
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#include <asm/cpu.h> |
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#define RTC_NAME "sgi_rtc" |
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static u64 uv_read_rtc(struct clocksource *cs); |
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static int uv_rtc_next_event(unsigned long, struct clock_event_device *); |
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static int uv_rtc_shutdown(struct clock_event_device *evt); |
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static struct clocksource clocksource_uv = { |
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.name = RTC_NAME, |
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.rating = 299, |
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.read = uv_read_rtc, |
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.mask = (u64)UVH_RTC_REAL_TIME_CLOCK_MASK, |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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static struct clock_event_device clock_event_device_uv = { |
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.name = RTC_NAME, |
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.features = CLOCK_EVT_FEAT_ONESHOT, |
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.shift = 20, |
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.rating = 400, |
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.irq = -1, |
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.set_next_event = uv_rtc_next_event, |
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.set_state_shutdown = uv_rtc_shutdown, |
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.event_handler = NULL, |
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}; |
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static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); |
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/* There is one of these allocated per node */ |
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struct uv_rtc_timer_head { |
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spinlock_t lock; |
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/* next cpu waiting for timer, local node relative: */ |
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int next_cpu; |
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/* number of cpus on this node: */ |
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int ncpus; |
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struct { |
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int lcpu; /* systemwide logical cpu number */ |
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u64 expires; /* next timer expiration for this cpu */ |
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} cpu[]; |
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}; |
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/* |
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* Access to uv_rtc_timer_head via blade id. |
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*/ |
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static struct uv_rtc_timer_head **blade_info __read_mostly; |
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static int uv_rtc_evt_enable; |
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/* |
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* Hardware interface routines |
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*/ |
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/* Send IPIs to another node */ |
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static void uv_rtc_send_IPI(int cpu) |
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{ |
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unsigned long apicid, val; |
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int pnode; |
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apicid = cpu_physical_id(cpu); |
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pnode = uv_apicid_to_pnode(apicid); |
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val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
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(apicid << UVH_IPI_INT_APIC_ID_SHFT) | |
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(X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT); |
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
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} |
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/* Check for an RTC interrupt pending */ |
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static int uv_intr_pending(int pnode) |
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{ |
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return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED2) & |
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UVH_EVENT_OCCURRED2_RTC_1_MASK; |
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} |
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/* Setup interrupt and return non-zero if early expiration occurred. */ |
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static int uv_setup_intr(int cpu, u64 expires) |
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{ |
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u64 val; |
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unsigned long apicid = cpu_physical_id(cpu); |
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int pnode = uv_cpu_to_pnode(cpu); |
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uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, |
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UVH_RTC1_INT_CONFIG_M_MASK); |
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uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); |
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uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED2_ALIAS, |
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UVH_EVENT_OCCURRED2_RTC_1_MASK); |
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val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | |
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((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT); |
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/* Set configuration */ |
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uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val); |
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/* Initialize comparator value */ |
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uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); |
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if (uv_read_rtc(NULL) <= expires) |
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return 0; |
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return !uv_intr_pending(pnode); |
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} |
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/* |
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* Per-cpu timer tracking routines |
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*/ |
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static __init void uv_rtc_deallocate_timers(void) |
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{ |
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int bid; |
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for_each_possible_blade(bid) { |
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kfree(blade_info[bid]); |
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} |
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kfree(blade_info); |
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} |
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/* Allocate per-node list of cpu timer expiration times. */ |
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static __init int uv_rtc_allocate_timers(void) |
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{ |
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int cpu; |
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blade_info = kcalloc(uv_possible_blades, sizeof(void *), GFP_KERNEL); |
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if (!blade_info) |
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return -ENOMEM; |
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for_each_present_cpu(cpu) { |
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int nid = cpu_to_node(cpu); |
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int bid = uv_cpu_to_blade_id(cpu); |
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int bcpu = uv_cpu_blade_processor_id(cpu); |
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struct uv_rtc_timer_head *head = blade_info[bid]; |
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if (!head) { |
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head = kmalloc_node(struct_size(head, cpu, |
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uv_blade_nr_possible_cpus(bid)), |
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GFP_KERNEL, nid); |
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if (!head) { |
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uv_rtc_deallocate_timers(); |
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return -ENOMEM; |
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} |
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spin_lock_init(&head->lock); |
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head->ncpus = uv_blade_nr_possible_cpus(bid); |
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head->next_cpu = -1; |
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blade_info[bid] = head; |
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} |
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head->cpu[bcpu].lcpu = cpu; |
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head->cpu[bcpu].expires = ULLONG_MAX; |
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} |
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return 0; |
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} |
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/* Find and set the next expiring timer. */ |
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static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode) |
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{ |
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u64 lowest = ULLONG_MAX; |
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int c, bcpu = -1; |
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head->next_cpu = -1; |
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for (c = 0; c < head->ncpus; c++) { |
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u64 exp = head->cpu[c].expires; |
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if (exp < lowest) { |
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bcpu = c; |
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lowest = exp; |
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} |
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} |
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if (bcpu >= 0) { |
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head->next_cpu = bcpu; |
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c = head->cpu[bcpu].lcpu; |
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if (uv_setup_intr(c, lowest)) |
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/* If we didn't set it up in time, trigger */ |
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uv_rtc_send_IPI(c); |
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} else { |
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uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, |
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UVH_RTC1_INT_CONFIG_M_MASK); |
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} |
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} |
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/* |
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* Set expiration time for current cpu. |
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* |
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* Returns 1 if we missed the expiration time. |
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*/ |
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static int uv_rtc_set_timer(int cpu, u64 expires) |
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{ |
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int pnode = uv_cpu_to_pnode(cpu); |
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int bid = uv_cpu_to_blade_id(cpu); |
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struct uv_rtc_timer_head *head = blade_info[bid]; |
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int bcpu = uv_cpu_blade_processor_id(cpu); |
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u64 *t = &head->cpu[bcpu].expires; |
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unsigned long flags; |
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int next_cpu; |
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spin_lock_irqsave(&head->lock, flags); |
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next_cpu = head->next_cpu; |
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*t = expires; |
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/* Will this one be next to go off? */ |
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if (next_cpu < 0 || bcpu == next_cpu || |
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expires < head->cpu[next_cpu].expires) { |
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head->next_cpu = bcpu; |
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if (uv_setup_intr(cpu, expires)) { |
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*t = ULLONG_MAX; |
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uv_rtc_find_next_timer(head, pnode); |
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spin_unlock_irqrestore(&head->lock, flags); |
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return -ETIME; |
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} |
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} |
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spin_unlock_irqrestore(&head->lock, flags); |
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return 0; |
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} |
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/* |
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* Unset expiration time for current cpu. |
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* |
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* Returns 1 if this timer was pending. |
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*/ |
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static int uv_rtc_unset_timer(int cpu, int force) |
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{ |
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int pnode = uv_cpu_to_pnode(cpu); |
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int bid = uv_cpu_to_blade_id(cpu); |
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struct uv_rtc_timer_head *head = blade_info[bid]; |
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int bcpu = uv_cpu_blade_processor_id(cpu); |
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u64 *t = &head->cpu[bcpu].expires; |
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unsigned long flags; |
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int rc = 0; |
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spin_lock_irqsave(&head->lock, flags); |
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if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force) |
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rc = 1; |
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if (rc) { |
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*t = ULLONG_MAX; |
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/* Was the hardware setup for this timer? */ |
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if (head->next_cpu == bcpu) |
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uv_rtc_find_next_timer(head, pnode); |
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} |
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spin_unlock_irqrestore(&head->lock, flags); |
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return rc; |
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} |
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/* |
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* Kernel interface routines. |
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*/ |
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/* |
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* Read the RTC. |
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* |
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* Starting with HUB rev 2.0, the UV RTC register is replicated across all |
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* cachelines of it's own page. This allows faster simultaneous reads |
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* from a given socket. |
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*/ |
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static u64 uv_read_rtc(struct clocksource *cs) |
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{ |
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unsigned long offset; |
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if (uv_get_min_hub_revision_id() == 1) |
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offset = 0; |
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else |
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offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE; |
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return (u64)uv_read_local_mmr(UVH_RTC | offset); |
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} |
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/* |
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* Program the next event, relative to now |
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*/ |
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static int uv_rtc_next_event(unsigned long delta, |
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struct clock_event_device *ced) |
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{ |
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int ced_cpu = cpumask_first(ced->cpumask); |
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return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL)); |
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} |
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/* |
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* Shutdown the RTC timer |
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*/ |
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static int uv_rtc_shutdown(struct clock_event_device *evt) |
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{ |
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int ced_cpu = cpumask_first(evt->cpumask); |
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uv_rtc_unset_timer(ced_cpu, 1); |
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return 0; |
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} |
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static void uv_rtc_interrupt(void) |
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{ |
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int cpu = smp_processor_id(); |
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struct clock_event_device *ced = &per_cpu(cpu_ced, cpu); |
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if (!ced || !ced->event_handler) |
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return; |
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if (uv_rtc_unset_timer(cpu, 0) != 1) |
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return; |
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ced->event_handler(ced); |
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} |
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static int __init uv_enable_evt_rtc(char *str) |
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{ |
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uv_rtc_evt_enable = 1; |
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return 1; |
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} |
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__setup("uvrtcevt", uv_enable_evt_rtc); |
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static __init void uv_rtc_register_clockevents(struct work_struct *dummy) |
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{ |
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struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); |
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*ced = clock_event_device_uv; |
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ced->cpumask = cpumask_of(smp_processor_id()); |
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clockevents_register_device(ced); |
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} |
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static __init int uv_rtc_setup_clock(void) |
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{ |
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int rc; |
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if (!is_uv_system()) |
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return -ENODEV; |
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rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second); |
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if (rc) |
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printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc); |
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else |
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printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n", |
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sn_rtc_cycles_per_second/(unsigned long)1E6); |
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if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback) |
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return rc; |
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/* Setup and register clockevents */ |
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rc = uv_rtc_allocate_timers(); |
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if (rc) |
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goto error; |
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x86_platform_ipi_callback = uv_rtc_interrupt; |
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clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second, |
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NSEC_PER_SEC, clock_event_device_uv.shift); |
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clock_event_device_uv.min_delta_ns = NSEC_PER_SEC / |
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sn_rtc_cycles_per_second; |
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clock_event_device_uv.min_delta_ticks = 1; |
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clock_event_device_uv.max_delta_ns = clocksource_uv.mask * |
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(NSEC_PER_SEC / sn_rtc_cycles_per_second); |
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clock_event_device_uv.max_delta_ticks = clocksource_uv.mask; |
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rc = schedule_on_each_cpu(uv_rtc_register_clockevents); |
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if (rc) { |
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x86_platform_ipi_callback = NULL; |
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uv_rtc_deallocate_timers(); |
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goto error; |
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} |
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printk(KERN_INFO "UV RTC clockevents registered\n"); |
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return 0; |
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error: |
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clocksource_unregister(&clocksource_uv); |
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printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc); |
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return rc; |
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} |
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arch_initcall(uv_rtc_setup_clock);
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