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571 lines
15 KiB
571 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* IOSF-SB MailBox Interface Driver |
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* Copyright (c) 2013, Intel Corporation. |
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* |
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* The IOSF-SB is a fabric bus available on Atom based SOC's that uses a |
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* mailbox interface (MBI) to communicate with multiple devices. This |
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* driver implements access to this interface for those platforms that can |
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* enumerate the device using PCI. |
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*/ |
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|
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#include <linux/delay.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/spinlock.h> |
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#include <linux/pci.h> |
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#include <linux/debugfs.h> |
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#include <linux/capability.h> |
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#include <linux/pm_qos.h> |
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#include <linux/wait.h> |
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#include <asm/iosf_mbi.h> |
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0F00 |
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#define PCI_DEVICE_ID_INTEL_BRASWELL 0x2280 |
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000 0x0958 |
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#define PCI_DEVICE_ID_INTEL_TANGIER 0x1170 |
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static struct pci_dev *mbi_pdev; |
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static DEFINE_SPINLOCK(iosf_mbi_lock); |
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|
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/**************** Generic iosf_mbi access helpers ****************/ |
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|
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static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset) |
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{ |
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return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE; |
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} |
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static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr) |
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{ |
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int result; |
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if (!mbi_pdev) |
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return -ENODEV; |
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if (mcrx) { |
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result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET, |
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mcrx); |
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if (result < 0) |
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goto fail_read; |
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} |
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result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); |
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if (result < 0) |
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goto fail_read; |
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result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr); |
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if (result < 0) |
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goto fail_read; |
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return 0; |
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fail_read: |
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dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result); |
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return result; |
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} |
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static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr) |
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{ |
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int result; |
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if (!mbi_pdev) |
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return -ENODEV; |
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result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr); |
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if (result < 0) |
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goto fail_write; |
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if (mcrx) { |
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result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET, |
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mcrx); |
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if (result < 0) |
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goto fail_write; |
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} |
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result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); |
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if (result < 0) |
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goto fail_write; |
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return 0; |
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fail_write: |
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dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result); |
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return result; |
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} |
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int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr) |
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{ |
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u32 mcr, mcrx; |
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unsigned long flags; |
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int ret; |
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/* Access to the GFX unit is handled by GPU code */ |
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if (port == BT_MBI_UNIT_GFX) { |
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WARN_ON(1); |
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return -EPERM; |
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} |
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mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); |
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mcrx = offset & MBI_MASK_HI; |
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spin_lock_irqsave(&iosf_mbi_lock, flags); |
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ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr); |
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spin_unlock_irqrestore(&iosf_mbi_lock, flags); |
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return ret; |
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} |
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EXPORT_SYMBOL(iosf_mbi_read); |
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int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr) |
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{ |
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u32 mcr, mcrx; |
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unsigned long flags; |
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int ret; |
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/* Access to the GFX unit is handled by GPU code */ |
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if (port == BT_MBI_UNIT_GFX) { |
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WARN_ON(1); |
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return -EPERM; |
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} |
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mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); |
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mcrx = offset & MBI_MASK_HI; |
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spin_lock_irqsave(&iosf_mbi_lock, flags); |
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ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr); |
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spin_unlock_irqrestore(&iosf_mbi_lock, flags); |
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return ret; |
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} |
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EXPORT_SYMBOL(iosf_mbi_write); |
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) |
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{ |
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u32 mcr, mcrx; |
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u32 value; |
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unsigned long flags; |
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int ret; |
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/* Access to the GFX unit is handled by GPU code */ |
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if (port == BT_MBI_UNIT_GFX) { |
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WARN_ON(1); |
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return -EPERM; |
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} |
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mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); |
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mcrx = offset & MBI_MASK_HI; |
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spin_lock_irqsave(&iosf_mbi_lock, flags); |
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/* Read current mdr value */ |
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ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value); |
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if (ret < 0) { |
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spin_unlock_irqrestore(&iosf_mbi_lock, flags); |
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return ret; |
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} |
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/* Apply mask */ |
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value &= ~mask; |
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mdr &= mask; |
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value |= mdr; |
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/* Write back */ |
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ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value); |
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spin_unlock_irqrestore(&iosf_mbi_lock, flags); |
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return ret; |
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} |
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EXPORT_SYMBOL(iosf_mbi_modify); |
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bool iosf_mbi_available(void) |
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{ |
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/* Mbi isn't hot-pluggable. No remove routine is provided */ |
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return mbi_pdev; |
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} |
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EXPORT_SYMBOL(iosf_mbi_available); |
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/* |
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**************** P-Unit/kernel shared I2C bus arbritration **************** |
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* |
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* Some Bay Trail and Cherry Trail devices have the P-Unit and us (the kernel) |
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* share a single I2C bus to the PMIC. Below are helpers to arbitrate the |
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* accesses between the kernel and the P-Unit. |
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* |
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* See arch/x86/include/asm/iosf_mbi.h for kernel-doc text for each function. |
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*/ |
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#define SEMAPHORE_TIMEOUT 500 |
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#define PUNIT_SEMAPHORE_BYT 0x7 |
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#define PUNIT_SEMAPHORE_CHT 0x10e |
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#define PUNIT_SEMAPHORE_BIT BIT(0) |
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#define PUNIT_SEMAPHORE_ACQUIRE BIT(1) |
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static DEFINE_MUTEX(iosf_mbi_pmic_access_mutex); |
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static BLOCKING_NOTIFIER_HEAD(iosf_mbi_pmic_bus_access_notifier); |
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static DECLARE_WAIT_QUEUE_HEAD(iosf_mbi_pmic_access_waitq); |
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static u32 iosf_mbi_pmic_punit_access_count; |
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static u32 iosf_mbi_pmic_i2c_access_count; |
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static u32 iosf_mbi_sem_address; |
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static unsigned long iosf_mbi_sem_acquired; |
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static struct pm_qos_request iosf_mbi_pm_qos; |
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void iosf_mbi_punit_acquire(void) |
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{ |
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/* Wait for any I2C PMIC accesses from in kernel drivers to finish. */ |
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mutex_lock(&iosf_mbi_pmic_access_mutex); |
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while (iosf_mbi_pmic_i2c_access_count != 0) { |
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mutex_unlock(&iosf_mbi_pmic_access_mutex); |
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wait_event(iosf_mbi_pmic_access_waitq, |
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iosf_mbi_pmic_i2c_access_count == 0); |
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mutex_lock(&iosf_mbi_pmic_access_mutex); |
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} |
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/* |
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* We do not need to do anything to allow the PUNIT to safely access |
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* the PMIC, other then block in kernel accesses to the PMIC. |
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*/ |
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iosf_mbi_pmic_punit_access_count++; |
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mutex_unlock(&iosf_mbi_pmic_access_mutex); |
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} |
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EXPORT_SYMBOL(iosf_mbi_punit_acquire); |
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void iosf_mbi_punit_release(void) |
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{ |
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bool do_wakeup; |
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mutex_lock(&iosf_mbi_pmic_access_mutex); |
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iosf_mbi_pmic_punit_access_count--; |
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do_wakeup = iosf_mbi_pmic_punit_access_count == 0; |
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mutex_unlock(&iosf_mbi_pmic_access_mutex); |
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if (do_wakeup) |
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wake_up(&iosf_mbi_pmic_access_waitq); |
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} |
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EXPORT_SYMBOL(iosf_mbi_punit_release); |
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static int iosf_mbi_get_sem(u32 *sem) |
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{ |
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int ret; |
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ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, |
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iosf_mbi_sem_address, sem); |
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if (ret) { |
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dev_err(&mbi_pdev->dev, "Error P-Unit semaphore read failed\n"); |
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return ret; |
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} |
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*sem &= PUNIT_SEMAPHORE_BIT; |
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return 0; |
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} |
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static void iosf_mbi_reset_semaphore(void) |
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{ |
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if (iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, |
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iosf_mbi_sem_address, 0, PUNIT_SEMAPHORE_BIT)) |
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dev_err(&mbi_pdev->dev, "Error P-Unit semaphore reset failed\n"); |
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cpu_latency_qos_update_request(&iosf_mbi_pm_qos, PM_QOS_DEFAULT_VALUE); |
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blocking_notifier_call_chain(&iosf_mbi_pmic_bus_access_notifier, |
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MBI_PMIC_BUS_ACCESS_END, NULL); |
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} |
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/* |
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* This function blocks P-Unit accesses to the PMIC I2C bus, so that kernel |
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* I2C code, such as e.g. a fuel-gauge driver, can access it safely. |
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* |
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* This function may be called by I2C controller code while an I2C driver has |
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* already blocked P-Unit accesses because it wants them blocked over multiple |
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* i2c-transfers, for e.g. read-modify-write of an I2C client register. |
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* |
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* To allow safe PMIC i2c bus accesses this function takes the following steps: |
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* |
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* 1) Some code sends request to the P-Unit which make it access the PMIC |
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* I2C bus. Testing has shown that the P-Unit does not check its internal |
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* PMIC bus semaphore for these requests. Callers of these requests call |
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* iosf_mbi_punit_acquire()/_release() around their P-Unit accesses, these |
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* functions increase/decrease iosf_mbi_pmic_punit_access_count, so first |
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* we wait for iosf_mbi_pmic_punit_access_count to become 0. |
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* |
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* 2) Check iosf_mbi_pmic_i2c_access_count, if access has already |
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* been blocked by another caller, we only need to increment |
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* iosf_mbi_pmic_i2c_access_count and we can skip the other steps. |
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* |
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* 3) Some code makes such P-Unit requests from atomic contexts where it |
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* cannot call iosf_mbi_punit_acquire() as that may sleep. |
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* As the second step we call a notifier chain which allows any code |
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* needing P-Unit resources from atomic context to acquire them before |
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* we take control over the PMIC I2C bus. |
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* |
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* 4) When CPU cores enter C6 or C7 the P-Unit needs to talk to the PMIC |
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* if this happens while the kernel itself is accessing the PMIC I2C bus |
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* the SoC hangs. |
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* As the third step we call cpu_latency_qos_update_request() to disallow the |
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* CPU to enter C6 or C7. |
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* |
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* 5) The P-Unit has a PMIC bus semaphore which we can request to stop |
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* autonomous P-Unit tasks from accessing the PMIC I2C bus while we hold it. |
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* As the fourth and final step we request this semaphore and wait for our |
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* request to be acknowledged. |
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*/ |
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int iosf_mbi_block_punit_i2c_access(void) |
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{ |
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unsigned long start, end; |
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int ret = 0; |
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u32 sem; |
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if (WARN_ON(!mbi_pdev || !iosf_mbi_sem_address)) |
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return -ENXIO; |
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mutex_lock(&iosf_mbi_pmic_access_mutex); |
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while (iosf_mbi_pmic_punit_access_count != 0) { |
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mutex_unlock(&iosf_mbi_pmic_access_mutex); |
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wait_event(iosf_mbi_pmic_access_waitq, |
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iosf_mbi_pmic_punit_access_count == 0); |
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mutex_lock(&iosf_mbi_pmic_access_mutex); |
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} |
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if (iosf_mbi_pmic_i2c_access_count > 0) |
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goto success; |
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blocking_notifier_call_chain(&iosf_mbi_pmic_bus_access_notifier, |
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MBI_PMIC_BUS_ACCESS_BEGIN, NULL); |
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/* |
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* Disallow the CPU to enter C6 or C7 state, entering these states |
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* requires the P-Unit to talk to the PMIC and if this happens while |
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* we're holding the semaphore, the SoC hangs. |
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*/ |
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cpu_latency_qos_update_request(&iosf_mbi_pm_qos, 0); |
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/* host driver writes to side band semaphore register */ |
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ret = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, |
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iosf_mbi_sem_address, PUNIT_SEMAPHORE_ACQUIRE); |
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if (ret) { |
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dev_err(&mbi_pdev->dev, "Error P-Unit semaphore request failed\n"); |
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goto error; |
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} |
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/* host driver waits for bit 0 to be set in semaphore register */ |
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start = jiffies; |
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end = start + msecs_to_jiffies(SEMAPHORE_TIMEOUT); |
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do { |
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ret = iosf_mbi_get_sem(&sem); |
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if (!ret && sem) { |
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iosf_mbi_sem_acquired = jiffies; |
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dev_dbg(&mbi_pdev->dev, "P-Unit semaphore acquired after %ums\n", |
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jiffies_to_msecs(jiffies - start)); |
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goto success; |
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} |
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usleep_range(1000, 2000); |
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} while (time_before(jiffies, end)); |
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ret = -ETIMEDOUT; |
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dev_err(&mbi_pdev->dev, "Error P-Unit semaphore timed out, resetting\n"); |
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error: |
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iosf_mbi_reset_semaphore(); |
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if (!iosf_mbi_get_sem(&sem)) |
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dev_err(&mbi_pdev->dev, "P-Unit semaphore: %d\n", sem); |
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success: |
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if (!WARN_ON(ret)) |
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iosf_mbi_pmic_i2c_access_count++; |
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mutex_unlock(&iosf_mbi_pmic_access_mutex); |
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return ret; |
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} |
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EXPORT_SYMBOL(iosf_mbi_block_punit_i2c_access); |
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void iosf_mbi_unblock_punit_i2c_access(void) |
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{ |
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bool do_wakeup = false; |
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mutex_lock(&iosf_mbi_pmic_access_mutex); |
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iosf_mbi_pmic_i2c_access_count--; |
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if (iosf_mbi_pmic_i2c_access_count == 0) { |
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iosf_mbi_reset_semaphore(); |
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dev_dbg(&mbi_pdev->dev, "punit semaphore held for %ums\n", |
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jiffies_to_msecs(jiffies - iosf_mbi_sem_acquired)); |
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do_wakeup = true; |
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} |
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mutex_unlock(&iosf_mbi_pmic_access_mutex); |
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if (do_wakeup) |
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wake_up(&iosf_mbi_pmic_access_waitq); |
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} |
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EXPORT_SYMBOL(iosf_mbi_unblock_punit_i2c_access); |
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int iosf_mbi_register_pmic_bus_access_notifier(struct notifier_block *nb) |
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{ |
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int ret; |
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/* Wait for the bus to go inactive before registering */ |
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iosf_mbi_punit_acquire(); |
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ret = blocking_notifier_chain_register( |
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&iosf_mbi_pmic_bus_access_notifier, nb); |
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iosf_mbi_punit_release(); |
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return ret; |
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} |
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EXPORT_SYMBOL(iosf_mbi_register_pmic_bus_access_notifier); |
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int iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( |
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struct notifier_block *nb) |
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{ |
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iosf_mbi_assert_punit_acquired(); |
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return blocking_notifier_chain_unregister( |
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&iosf_mbi_pmic_bus_access_notifier, nb); |
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} |
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EXPORT_SYMBOL(iosf_mbi_unregister_pmic_bus_access_notifier_unlocked); |
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int iosf_mbi_unregister_pmic_bus_access_notifier(struct notifier_block *nb) |
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{ |
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int ret; |
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/* Wait for the bus to go inactive before unregistering */ |
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iosf_mbi_punit_acquire(); |
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ret = iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(nb); |
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iosf_mbi_punit_release(); |
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return ret; |
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} |
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EXPORT_SYMBOL(iosf_mbi_unregister_pmic_bus_access_notifier); |
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void iosf_mbi_assert_punit_acquired(void) |
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{ |
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WARN_ON(iosf_mbi_pmic_punit_access_count == 0); |
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} |
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EXPORT_SYMBOL(iosf_mbi_assert_punit_acquired); |
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|
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/**************** iosf_mbi debug code ****************/ |
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#ifdef CONFIG_IOSF_MBI_DEBUG |
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static u32 dbg_mdr; |
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static u32 dbg_mcr; |
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static u32 dbg_mcrx; |
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static int mcr_get(void *data, u64 *val) |
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{ |
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*val = *(u32 *)data; |
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return 0; |
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} |
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static int mcr_set(void *data, u64 val) |
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{ |
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u8 command = ((u32)val & 0xFF000000) >> 24, |
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port = ((u32)val & 0x00FF0000) >> 16, |
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offset = ((u32)val & 0x0000FF00) >> 8; |
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int err; |
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*(u32 *)data = val; |
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if (!capable(CAP_SYS_RAWIO)) |
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return -EACCES; |
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if (command & 1u) |
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err = iosf_mbi_write(port, |
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command, |
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dbg_mcrx | offset, |
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dbg_mdr); |
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else |
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err = iosf_mbi_read(port, |
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command, |
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dbg_mcrx | offset, |
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&dbg_mdr); |
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return err; |
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} |
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DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n"); |
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static struct dentry *iosf_dbg; |
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|
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static void iosf_sideband_debug_init(void) |
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{ |
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iosf_dbg = debugfs_create_dir("iosf_sb", NULL); |
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|
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/* mdr */ |
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debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr); |
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|
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/* mcrx */ |
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debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx); |
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|
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/* mcr - initiates mailbox tranaction */ |
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debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops); |
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} |
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static void iosf_debugfs_init(void) |
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{ |
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iosf_sideband_debug_init(); |
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} |
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static void iosf_debugfs_remove(void) |
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{ |
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debugfs_remove_recursive(iosf_dbg); |
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} |
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#else |
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static inline void iosf_debugfs_init(void) { } |
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static inline void iosf_debugfs_remove(void) { } |
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#endif /* CONFIG_IOSF_MBI_DEBUG */ |
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|
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static int iosf_mbi_probe(struct pci_dev *pdev, |
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const struct pci_device_id *dev_id) |
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{ |
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int ret; |
|
|
|
ret = pci_enable_device(pdev); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "error: could not enable device\n"); |
|
return ret; |
|
} |
|
|
|
mbi_pdev = pci_dev_get(pdev); |
|
iosf_mbi_sem_address = dev_id->driver_data; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct pci_device_id iosf_mbi_pci_ids[] = { |
|
{ PCI_DEVICE_DATA(INTEL, BAYTRAIL, PUNIT_SEMAPHORE_BYT) }, |
|
{ PCI_DEVICE_DATA(INTEL, BRASWELL, PUNIT_SEMAPHORE_CHT) }, |
|
{ PCI_DEVICE_DATA(INTEL, QUARK_X1000, 0) }, |
|
{ PCI_DEVICE_DATA(INTEL, TANGIER, 0) }, |
|
{ 0, }, |
|
}; |
|
MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids); |
|
|
|
static struct pci_driver iosf_mbi_pci_driver = { |
|
.name = "iosf_mbi_pci", |
|
.probe = iosf_mbi_probe, |
|
.id_table = iosf_mbi_pci_ids, |
|
}; |
|
|
|
static int __init iosf_mbi_init(void) |
|
{ |
|
iosf_debugfs_init(); |
|
|
|
cpu_latency_qos_add_request(&iosf_mbi_pm_qos, PM_QOS_DEFAULT_VALUE); |
|
|
|
return pci_register_driver(&iosf_mbi_pci_driver); |
|
} |
|
|
|
static void __exit iosf_mbi_exit(void) |
|
{ |
|
iosf_debugfs_remove(); |
|
|
|
pci_unregister_driver(&iosf_mbi_pci_driver); |
|
pci_dev_put(mbi_pdev); |
|
mbi_pdev = NULL; |
|
|
|
cpu_latency_qos_remove_request(&iosf_mbi_pm_qos); |
|
} |
|
|
|
module_init(iosf_mbi_init); |
|
module_exit(iosf_mbi_exit); |
|
|
|
MODULE_AUTHOR("David E. Box <[email protected]>"); |
|
MODULE_DESCRIPTION("IOSF Mailbox Interface accessor"); |
|
MODULE_LICENSE("GPL v2");
|
|
|