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350 lines
8.4 KiB
350 lines
8.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* FPU register's regset abstraction, for ptrace, core dumps, etc. |
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*/ |
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#include <asm/fpu/internal.h> |
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#include <asm/fpu/signal.h> |
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#include <asm/fpu/regset.h> |
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#include <asm/fpu/xstate.h> |
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#include <linux/sched/task_stack.h> |
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/* |
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* The xstateregs_active() routine is the same as the regset_fpregs_active() routine, |
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* as the "regset->n" for the xstate regset will be updated based on the feature |
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* capabilities supported by the xsave. |
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*/ |
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int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset) |
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{ |
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return regset->n; |
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} |
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int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset) |
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{ |
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if (boot_cpu_has(X86_FEATURE_FXSR)) |
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return regset->n; |
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else |
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return 0; |
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} |
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int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
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struct membuf to) |
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{ |
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struct fpu *fpu = &target->thread.fpu; |
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if (!boot_cpu_has(X86_FEATURE_FXSR)) |
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return -ENODEV; |
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fpu__prepare_read(fpu); |
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fpstate_sanitize_xstate(fpu); |
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return membuf_write(&to, &fpu->state.fxsave, sizeof(struct fxregs_state)); |
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} |
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int xfpregs_set(struct task_struct *target, const struct user_regset *regset, |
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unsigned int pos, unsigned int count, |
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const void *kbuf, const void __user *ubuf) |
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{ |
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struct fpu *fpu = &target->thread.fpu; |
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int ret; |
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if (!boot_cpu_has(X86_FEATURE_FXSR)) |
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return -ENODEV; |
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fpu__prepare_write(fpu); |
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fpstate_sanitize_xstate(fpu); |
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
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&fpu->state.fxsave, 0, -1); |
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/* |
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* mxcsr reserved bits must be masked to zero for security reasons. |
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*/ |
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fpu->state.fxsave.mxcsr &= mxcsr_feature_mask; |
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/* |
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* update the header bits in the xsave header, indicating the |
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* presence of FP and SSE state. |
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*/ |
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if (boot_cpu_has(X86_FEATURE_XSAVE)) |
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fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE; |
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return ret; |
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} |
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int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
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struct membuf to) |
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{ |
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struct fpu *fpu = &target->thread.fpu; |
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struct xregs_state *xsave; |
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if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
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return -ENODEV; |
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xsave = &fpu->state.xsave; |
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fpu__prepare_read(fpu); |
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if (using_compacted_format()) { |
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copy_xstate_to_kernel(to, xsave); |
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return 0; |
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} else { |
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fpstate_sanitize_xstate(fpu); |
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/* |
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* Copy the 48 bytes defined by the software into the xsave |
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* area in the thread struct, so that we can copy the whole |
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* area to user using one user_regset_copyout(). |
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*/ |
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memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); |
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/* |
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* Copy the xstate memory layout. |
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*/ |
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return membuf_write(&to, xsave, fpu_user_xstate_size); |
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} |
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} |
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int xstateregs_set(struct task_struct *target, const struct user_regset *regset, |
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unsigned int pos, unsigned int count, |
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const void *kbuf, const void __user *ubuf) |
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{ |
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struct fpu *fpu = &target->thread.fpu; |
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struct xregs_state *xsave; |
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int ret; |
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if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
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return -ENODEV; |
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/* |
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* A whole standard-format XSAVE buffer is needed: |
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*/ |
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if ((pos != 0) || (count < fpu_user_xstate_size)) |
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return -EFAULT; |
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xsave = &fpu->state.xsave; |
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fpu__prepare_write(fpu); |
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if (using_compacted_format()) { |
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if (kbuf) |
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ret = copy_kernel_to_xstate(xsave, kbuf); |
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else |
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ret = copy_user_to_xstate(xsave, ubuf); |
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} else { |
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
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if (!ret) |
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ret = validate_user_xstate_header(&xsave->header); |
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} |
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/* |
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* mxcsr reserved bits must be masked to zero for security reasons. |
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*/ |
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xsave->i387.mxcsr &= mxcsr_feature_mask; |
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/* |
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* In case of failure, mark all states as init: |
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*/ |
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if (ret) |
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fpstate_init(&fpu->state); |
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return ret; |
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} |
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#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
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/* |
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* FPU tag word conversions. |
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*/ |
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static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
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{ |
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unsigned int tmp; /* to avoid 16 bit prefixes in the code */ |
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/* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
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tmp = ~twd; |
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tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
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/* and move the valid bits to the lower byte. */ |
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tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ |
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tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ |
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tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ |
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return tmp; |
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} |
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#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
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#define FP_EXP_TAG_VALID 0 |
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#define FP_EXP_TAG_ZERO 1 |
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#define FP_EXP_TAG_SPECIAL 2 |
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#define FP_EXP_TAG_EMPTY 3 |
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static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave) |
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{ |
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struct _fpxreg *st; |
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u32 tos = (fxsave->swd >> 11) & 7; |
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u32 twd = (unsigned long) fxsave->twd; |
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u32 tag; |
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u32 ret = 0xffff0000u; |
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int i; |
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for (i = 0; i < 8; i++, twd >>= 1) { |
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if (twd & 0x1) { |
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st = FPREG_ADDR(fxsave, (i - tos) & 7); |
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switch (st->exponent & 0x7fff) { |
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case 0x7fff: |
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tag = FP_EXP_TAG_SPECIAL; |
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break; |
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case 0x0000: |
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if (!st->significand[0] && |
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!st->significand[1] && |
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!st->significand[2] && |
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!st->significand[3]) |
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tag = FP_EXP_TAG_ZERO; |
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else |
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tag = FP_EXP_TAG_SPECIAL; |
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break; |
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default: |
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if (st->significand[3] & 0x8000) |
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tag = FP_EXP_TAG_VALID; |
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else |
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tag = FP_EXP_TAG_SPECIAL; |
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break; |
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} |
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} else { |
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tag = FP_EXP_TAG_EMPTY; |
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} |
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ret |= tag << (2 * i); |
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} |
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return ret; |
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} |
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/* |
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* FXSR floating point environment conversions. |
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*/ |
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void |
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convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
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{ |
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struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave; |
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struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
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struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; |
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int i; |
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env->cwd = fxsave->cwd | 0xffff0000u; |
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env->swd = fxsave->swd | 0xffff0000u; |
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env->twd = twd_fxsr_to_i387(fxsave); |
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#ifdef CONFIG_X86_64 |
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env->fip = fxsave->rip; |
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env->foo = fxsave->rdp; |
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/* |
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* should be actually ds/cs at fpu exception time, but |
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* that information is not available in 64bit mode. |
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*/ |
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env->fcs = task_pt_regs(tsk)->cs; |
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if (tsk == current) { |
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savesegment(ds, env->fos); |
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} else { |
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env->fos = tsk->thread.ds; |
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} |
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env->fos |= 0xffff0000; |
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#else |
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env->fip = fxsave->fip; |
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env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
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env->foo = fxsave->foo; |
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env->fos = fxsave->fos; |
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#endif |
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for (i = 0; i < 8; ++i) |
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memcpy(&to[i], &from[i], sizeof(to[0])); |
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} |
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void convert_to_fxsr(struct fxregs_state *fxsave, |
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const struct user_i387_ia32_struct *env) |
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{ |
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struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
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struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; |
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int i; |
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fxsave->cwd = env->cwd; |
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fxsave->swd = env->swd; |
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fxsave->twd = twd_i387_to_fxsr(env->twd); |
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fxsave->fop = (u16) ((u32) env->fcs >> 16); |
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#ifdef CONFIG_X86_64 |
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fxsave->rip = env->fip; |
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fxsave->rdp = env->foo; |
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/* cs and ds ignored */ |
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#else |
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fxsave->fip = env->fip; |
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fxsave->fcs = (env->fcs & 0xffff); |
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fxsave->foo = env->foo; |
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fxsave->fos = env->fos; |
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#endif |
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for (i = 0; i < 8; ++i) |
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memcpy(&to[i], &from[i], sizeof(from[0])); |
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} |
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int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
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struct membuf to) |
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{ |
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struct fpu *fpu = &target->thread.fpu; |
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struct user_i387_ia32_struct env; |
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fpu__prepare_read(fpu); |
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if (!boot_cpu_has(X86_FEATURE_FPU)) |
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return fpregs_soft_get(target, regset, to); |
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if (!boot_cpu_has(X86_FEATURE_FXSR)) { |
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return membuf_write(&to, &fpu->state.fsave, |
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sizeof(struct fregs_state)); |
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} |
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fpstate_sanitize_xstate(fpu); |
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if (to.left == sizeof(env)) { |
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convert_from_fxsr(to.p, target); |
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return 0; |
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} |
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convert_from_fxsr(&env, target); |
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return membuf_write(&to, &env, sizeof(env)); |
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} |
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int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
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unsigned int pos, unsigned int count, |
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const void *kbuf, const void __user *ubuf) |
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{ |
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struct fpu *fpu = &target->thread.fpu; |
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struct user_i387_ia32_struct env; |
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int ret; |
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fpu__prepare_write(fpu); |
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fpstate_sanitize_xstate(fpu); |
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if (!boot_cpu_has(X86_FEATURE_FPU)) |
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return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
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if (!boot_cpu_has(X86_FEATURE_FXSR)) |
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return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
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&fpu->state.fsave, 0, |
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-1); |
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if (pos > 0 || count < sizeof(env)) |
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convert_from_fxsr(&env, target); |
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
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if (!ret) |
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convert_to_fxsr(&target->thread.fpu.state.fxsave, &env); |
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/* |
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* update the header bit in the xsave header, indicating the |
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* presence of FP. |
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*/ |
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if (boot_cpu_has(X86_FEATURE_XSAVE)) |
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fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP; |
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return ret; |
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} |
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#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
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