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238 lines
6.0 KiB
238 lines
6.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/syscore_ops.h> |
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#include <linux/suspend.h> |
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#include <linux/cpu.h> |
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#include <asm/msr.h> |
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#include <asm/mwait.h> |
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#define UMWAIT_C02_ENABLE 0 |
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#define UMWAIT_CTRL_VAL(max_time, c02_disable) \ |
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(((max_time) & MSR_IA32_UMWAIT_CONTROL_TIME_MASK) | \ |
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((c02_disable) & MSR_IA32_UMWAIT_CONTROL_C02_DISABLE)) |
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/* |
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* Cache IA32_UMWAIT_CONTROL MSR. This is a systemwide control. By default, |
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* umwait max time is 100000 in TSC-quanta and C0.2 is enabled |
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*/ |
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static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE); |
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/* |
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* Cache the original IA32_UMWAIT_CONTROL MSR value which is configured by |
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* hardware or BIOS before kernel boot. |
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*/ |
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static u32 orig_umwait_control_cached __ro_after_init; |
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/* |
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* Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL MSR in |
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* the sysfs write functions. |
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*/ |
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static DEFINE_MUTEX(umwait_lock); |
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static void umwait_update_control_msr(void * unused) |
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{ |
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lockdep_assert_irqs_disabled(); |
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wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0); |
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} |
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/* |
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* The CPU hotplug callback sets the control MSR to the global control |
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* value. |
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* |
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* Disable interrupts so the read of umwait_control_cached and the WRMSR |
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* are protected against a concurrent sysfs write. Otherwise the sysfs |
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* write could update the cached value after it had been read on this CPU |
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* and issue the IPI before the old value had been written. The IPI would |
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* interrupt, write the new value and after return from IPI the previous |
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* value would be written by this CPU. |
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* |
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* With interrupts disabled the upcoming CPU either sees the new control |
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* value or the IPI is updating this CPU to the new control value after |
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* interrupts have been reenabled. |
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*/ |
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static int umwait_cpu_online(unsigned int cpu) |
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{ |
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local_irq_disable(); |
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umwait_update_control_msr(NULL); |
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local_irq_enable(); |
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return 0; |
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} |
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/* |
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* The CPU hotplug callback sets the control MSR to the original control |
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* value. |
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*/ |
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static int umwait_cpu_offline(unsigned int cpu) |
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{ |
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/* |
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* This code is protected by the CPU hotplug already and |
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* orig_umwait_control_cached is never changed after it caches |
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* the original control MSR value in umwait_init(). So there |
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* is no race condition here. |
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*/ |
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wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0); |
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return 0; |
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} |
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/* |
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* On resume, restore IA32_UMWAIT_CONTROL MSR on the boot processor which |
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* is the only active CPU at this time. The MSR is set up on the APs via the |
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* CPU hotplug callback. |
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* |
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* This function is invoked on resume from suspend and hibernation. On |
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* resume from suspend the restore should be not required, but we neither |
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* trust the firmware nor does it matter if the same value is written |
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* again. |
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*/ |
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static void umwait_syscore_resume(void) |
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{ |
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umwait_update_control_msr(NULL); |
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} |
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static struct syscore_ops umwait_syscore_ops = { |
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.resume = umwait_syscore_resume, |
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}; |
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/* sysfs interface */ |
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/* |
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* When bit 0 in IA32_UMWAIT_CONTROL MSR is 1, C0.2 is disabled. |
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* Otherwise, C0.2 is enabled. |
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*/ |
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static inline bool umwait_ctrl_c02_enabled(u32 ctrl) |
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{ |
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return !(ctrl & MSR_IA32_UMWAIT_CONTROL_C02_DISABLE); |
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} |
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static inline u32 umwait_ctrl_max_time(u32 ctrl) |
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{ |
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return ctrl & MSR_IA32_UMWAIT_CONTROL_TIME_MASK; |
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} |
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static inline void umwait_update_control(u32 maxtime, bool c02_enable) |
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{ |
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u32 ctrl = maxtime & MSR_IA32_UMWAIT_CONTROL_TIME_MASK; |
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if (!c02_enable) |
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ctrl |= MSR_IA32_UMWAIT_CONTROL_C02_DISABLE; |
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WRITE_ONCE(umwait_control_cached, ctrl); |
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/* Propagate to all CPUs */ |
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on_each_cpu(umwait_update_control_msr, NULL, 1); |
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} |
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static ssize_t |
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enable_c02_show(struct device *dev, struct device_attribute *attr, char *buf) |
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{ |
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u32 ctrl = READ_ONCE(umwait_control_cached); |
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return sprintf(buf, "%d\n", umwait_ctrl_c02_enabled(ctrl)); |
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} |
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static ssize_t enable_c02_store(struct device *dev, |
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struct device_attribute *attr, |
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const char *buf, size_t count) |
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{ |
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bool c02_enable; |
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u32 ctrl; |
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int ret; |
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ret = kstrtobool(buf, &c02_enable); |
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if (ret) |
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return ret; |
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mutex_lock(&umwait_lock); |
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ctrl = READ_ONCE(umwait_control_cached); |
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if (c02_enable != umwait_ctrl_c02_enabled(ctrl)) |
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umwait_update_control(ctrl, c02_enable); |
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mutex_unlock(&umwait_lock); |
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return count; |
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} |
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static DEVICE_ATTR_RW(enable_c02); |
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static ssize_t |
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max_time_show(struct device *kobj, struct device_attribute *attr, char *buf) |
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{ |
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u32 ctrl = READ_ONCE(umwait_control_cached); |
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return sprintf(buf, "%u\n", umwait_ctrl_max_time(ctrl)); |
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} |
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static ssize_t max_time_store(struct device *kobj, |
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struct device_attribute *attr, |
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const char *buf, size_t count) |
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{ |
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u32 max_time, ctrl; |
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int ret; |
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ret = kstrtou32(buf, 0, &max_time); |
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if (ret) |
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return ret; |
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/* bits[1:0] must be zero */ |
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if (max_time & ~MSR_IA32_UMWAIT_CONTROL_TIME_MASK) |
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return -EINVAL; |
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mutex_lock(&umwait_lock); |
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ctrl = READ_ONCE(umwait_control_cached); |
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if (max_time != umwait_ctrl_max_time(ctrl)) |
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umwait_update_control(max_time, umwait_ctrl_c02_enabled(ctrl)); |
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mutex_unlock(&umwait_lock); |
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return count; |
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} |
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static DEVICE_ATTR_RW(max_time); |
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static struct attribute *umwait_attrs[] = { |
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&dev_attr_enable_c02.attr, |
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&dev_attr_max_time.attr, |
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NULL |
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}; |
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static struct attribute_group umwait_attr_group = { |
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.attrs = umwait_attrs, |
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.name = "umwait_control", |
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}; |
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static int __init umwait_init(void) |
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{ |
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struct device *dev; |
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int ret; |
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if (!boot_cpu_has(X86_FEATURE_WAITPKG)) |
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return -ENODEV; |
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/* |
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* Cache the original control MSR value before the control MSR is |
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* changed. This is the only place where orig_umwait_control_cached |
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* is modified. |
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*/ |
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rdmsrl(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); |
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online", |
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umwait_cpu_online, umwait_cpu_offline); |
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if (ret < 0) { |
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/* |
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* On failure, the control MSR on all CPUs has the |
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* original control value. |
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*/ |
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return ret; |
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} |
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register_syscore_ops(&umwait_syscore_ops); |
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/* |
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* Add umwait control interface. Ignore failure, so at least the |
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* default values are set up in case the machine manages to boot. |
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*/ |
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dev = cpu_subsys.dev_root; |
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return sysfs_create_group(&dev->kobj, &umwait_attr_group); |
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} |
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device_initcall(umwait_init);
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